Power-on reset circuit, LED drive circuit and micro-processing chip

Abstract

The embodiment of the utility model provides a power-on reset circuit, an LED drive circuit and a micro-processing chip. The power-on reset circuit comprises a current mirror module, a reset signal control module and a reset signal generation module. The first end of the current mirror module is connected with a first power supply, the first output end of the current mirror module is connected with the reset signal generation module, and the second output end of the current mirror module is connected with the first end of the reset signal control module; the reset signal generation module is used for generating a reset signal according to the first voltage output by the first output end of the current mirror module; the second end of the reset signal control module is connected with the reset signal generation module, the reset signal control module is used for outputting a control signal according to the second voltage of the second output end of the current mirror module, and the control signal is used for controlling the reset signal generation module to stop generating the reset signal. Active devices in the current mirror module replace part of divider resistors, so that the power consumption of the power-on reset circuit is reduced, and meanwhile, the system is prevented from running under an unstable voltage condition.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply systems, in particular to a power-on reset circuit, an LED driving circuit and a micro-processing chip. BACKGROUND

[0002] A power-on reset circuit (POR) is a circuit used to generate a reset signal when an electronic device is powered on. Its main function is to ensure that the processor or other critical circuits of the system start running from a known initial state when the device is powered on, which is crucial to avoid random states or uncertain behaviors when powered on.

[0003] The power consumption of the resistance voltage dividing branch of the power-on reset circuit in the prior art is too large. If the power consumption of the resistance voltage dividing branch is to be reduced, a large resistance value resistor needs to be used, which will increase the chip area. CONTENT OF THE INVENTION

[0004] The embodiments of the present application provide a power-on reset circuit, an LED driving circuit and a micro-processing chip to reduce power consumption and chip area.

[0005] In a first aspect, the embodiments of the present application provide a power-on reset circuit, comprising: a current mirror module, a reset signal control module and a reset signal generation module;

[0006] The first end of the current mirror module is connected with a first power supply, the first output end of the current mirror module is connected with the reset signal generation module, and the second output end of the current mirror module is connected with the first end of the reset signal control module;

[0007] The reset signal generation module is configured to generate a reset signal according to a first voltage output by the first output end of the current mirror module;

[0008] The second end of the reset signal control module is connected with the reset signal generation module, and the reset signal control module is configured to output a control signal according to a second voltage of the second output end of the current mirror module, and the control signal is configured to control the reset signal generation module to stop generating the reset signal.

[0009] In one of the embodiments, the current mirror module comprises a first switch and a second switch.

[0010] The first end of the first switch is connected with the first power supply, the second end of the first switch is the second output end of the current mirror module, the second end of the first switch is connected with the first end of the reset signal control module and the control end of the first switch, and the control end of the first switch is connected with the control end of the second switch.

[0011] The first end of the second switch is connected with the first power supply, the second end of the second switch is the first output end of the current mirror module, and the second end of the second switch is connected with the reset signal generation module.

[0012] In one of the embodiments, the reset signal generation module comprises a trigger unit and an inverting unit.

[0013] The first end of the trigger unit is connected with the first output end of the current mirror module, and the second end of the trigger unit is connected with the first end of the inverting unit.

[0014] The trigger unit outputs a first signal when the first voltage is greater than a first trigger threshold, and the inverting unit generates a reset signal by inverting the first signal.

[0015] The trigger unit outputs a second signal when the control signal is less than a second trigger threshold, and the inverting unit outputs a voltage value of the first power supply according to the second signal.

[0016] The first trigger threshold is greater than the second trigger threshold.

[0017] In one of the embodiments, the reset signal control module comprises a detection unit and a switch unit, and the detection unit comprises a first resistor and a second resistor.

[0018] The first end of the first resistor is the first end of the reset signal control module, the first end of the first resistor is connected with the second output end of the current mirror module and the control end of the switch unit, the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is grounded. The first end of the switch unit is connected with the first output end of the current mirror module and the reset signal generation module, the second end of the switch unit is grounded, the switch unit is turned on when the second voltage is greater than a third preset value, a second signal is output, and the reset signal generation module generates a first signal according to the second signal.

[0019] In one of the embodiments, the first switch is a first PMOS tube, the second switch is a second PMOS tube, and the switch unit is an NMOS tube. The trigger unit is a Schmitt trigger circuit, and the inverting unit is a NOT gate.

[0020] The first voltage output by the second PMOS tube is greater than the first trigger threshold of the Schmitt trigger circuit, the Schmitt trigger circuit outputs a first signal, and the NOT gate outputs a reset signal according to the first signal.

[0021] In one of the embodiments, the NMOS tube is turned on when the second voltage is greater than a third preset value, and outputs a second signal.

[0022] The second signal is less than the second trigger threshold of the Schmitt trigger circuit, the Schmitt trigger circuit outputs a second signal, and the NOT gate outputs a first signal according to the second signal.

[0023] In one of the embodiments, the power-on reset circuit further comprises a third switch;

[0024] The first end of the third switch is connected with the first end of the second resistor, the second end of the third switch is connected with the second end of the second resistor, and the control end of the third switch is connected with the output end of the reset signal generation module;

[0025] The third switch is used for being turned on when the reset signal generation module outputs the reset signal and being turned off when the reset signal generation module outputs the first signal.

[0026] In one of the embodiments, the detection unit further comprises a third resistor;

[0027] The second end of the first resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the first end of the second resistor, and the second end of the second resistor is grounded;

[0028] The third resistor is a resistor with a positive temperature coefficient.

[0029] The first resistor and the third resistor are positive and negative temperature trimming, the second resistor needs to be set to be small, and cannot be used as a reference for improving the temperature coefficient trimming of the first resistor and the third resistor. The second resistor is not considered when designing the first resistor and the third resistor, otherwise the first resistor and the third resistor cannot play an accurate trimming role. The second resistor and the third switch play a role in the hysteresis process, generate a resistance close to zero temperature characteristics, and improve the resistance that changes with temperature to solve the shortcoming that the POR detection point changes in a large range.

[0030] In a second aspect, the embodiments of the present application provide an LED driving circuit comprising the power-on reset circuit as any of the above.

[0031] In a third aspect, the embodiments of the present application provide a micro processing chip comprising the power-on reset circuit as any of the above.

[0032] The power-on reset circuit, the LED driving circuit and the micro processing chip provided by the embodiments of the present application, the power-on reset circuit comprises a current mirror module, a reset signal control module and a reset signal generation module; the first end of the current mirror module is connected with a first power supply, the first output end of the current mirror module is connected with the reset signal generation module, and the second output end of the current mirror module is connected with the first end of the reset signal control module; the reset signal generation module is used for generating a reset signal according to the first voltage output by the first output end of the current mirror module; the second end of the reset signal control module is connected with the reset signal generation module, and the reset signal control module is used for outputting a control signal according to the second voltage of the second output end of the current mirror module, and the control signal is used for controlling the reset signal generation module to stop generating the reset signal. The active device in the current mirror module is used to replace part of the voltage dividing resistor, so that the power consumption of the power-on reset circuit can be reduced, the chip area can be reduced, and the reset signal generation can be realized, thereby avoiding the operation of the system under unstable voltage conditions. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0034] Figure 1 A structure schematic diagram of a power-on reset circuit is provided for an embodiment of the present application;

[0035] Figure 2 A structure schematic diagram of a power-on reset circuit is provided for another embodiment of the present application;

[0036] Figure 3 A structure schematic diagram of a power-on reset circuit is provided for an embodiment of the present application;

[0037] Figure 4 A structure schematic diagram of an LED driving circuit is provided for an embodiment of the present application;

[0038] Figure 5 A structure schematic diagram of a micro processing chip is provided for an embodiment of the present application.

[0039] Reference signs:

[0040] 210, current mirror module; 220, reset signal generation module; 230, reset signal control module; M1, first switch; M2, second switch; M3, third switch; M4, switch unit; R1, first resistor; R2, second resistor; R3, third resistor; Q1, trigger unit; Q2, inverting unit.

[0041] The specific embodiments of the application have been shown by the above drawings, and will be described in more detail hereinafter. These drawings and detailed description are not intended to limit the scope of the concept of the application in any way, but to illustrate the concept of the application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0042] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The same numbers are used in different drawings to represent the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application.

[0043] A Power-On Reset (POR) circuit is a circuit used to generate a reset signal when an electronic device is powered on. Its main function is to ensure that the processor or other critical circuits of the system start running from a known initial state when the device is powered on, which is crucial to avoid random states or uncertain behavior at power-on.

[0044] The power consumption of the resistance voltage dividing branch of the prior art power-on reset circuit is too large. If the power consumption of the resistance voltage dividing branch is to be reduced, a large resistance value resistor needs to be used, which will increase the chip area.

[0045] The application provides a power-on reset circuit, which comprises a current mirror module, a reset signal control module and a reset signal generation module; the first end of the current mirror module is connected with a first power supply, the first output end of the current mirror module is connected with the reset signal generation module, and the second output end of the current mirror module is connected with the first end of the reset signal control module; the reset signal generation module is used to generate a reset signal according to the first voltage output by the first output end of the current mirror module; the second end of the reset signal control module is connected with the reset signal generation module, and the reset signal control module is used to output a control signal according to the second voltage of the second output end of the current mirror module, and the control signal is used to control the reset signal generation module to stop generating the reset signal. The application can reduce the power consumption of the power-on reset circuit by using active devices in the current mirror module to replace part of the voltage dividing resistors, while reducing the chip area, and can also realize reset signal generation, avoiding the operation of the system under unstable voltage conditions.

[0046] The technical solutions of the application and how the technical solutions of the application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the application will be described below with reference to the drawings.

[0047] AsFigure 1 as shown, Figure 1 A structural diagram of a power-on reset circuit is provided for an embodiment of the present application. The power-on reset circuit includes a current mirror module 210 and a reset signal generation module 220. The first end of the current mirror module 210 is connected with a first power supply, and the first output end of the current mirror module 210 is connected with the reset signal generation module 220. The reset signal generation module 220 is configured to generate a reset signal according to a first voltage V1 output by the first output end of the current mirror module 210.

[0048] Specifically, when the first power supply is turned on, the current mirror module 210 starts to work, and the first output end of the current mirror module 210 outputs the first voltage V1, i.e., the voltage at point B. The first voltage is a voltage related to the first power supply. The reset signal output module is configured to monitor the output voltage of the first output end of the current mirror module 210. When the first voltage V1 reaches a preset threshold, a reset signal is generated. The reset signal ensures that the system has sufficient time to stabilize, i.e., the reset signal will not disappear before the system voltage reaches a stable state, thereby avoiding the system running under unstable voltage conditions. The current mirror module 210 is configured to copy the current and provide stable current or voltage to the reset signal generation module 220. Secondly, compared with the prior art, the active device of the current mirror module 210 is used to replace part of the voltage dividing resistor, thereby reducing the power consumption of the power-on reset circuit and reducing the chip area.

[0049] In one embodiment, as shown, Figure 1 The power-on reset circuit further includes a reset signal control module 230. The current mirror module 210 includes a second output end. The first end of the reset signal control module 230 is connected with the second output end of the current mirror module 210, and the second end of the reset signal control module 230 is connected with the reset signal generation module 220. The reset signal control module 230 is configured to output a control signal according to a second voltage V2 of the second output end of the current mirror module 210. The control signal is configured to control the reset signal generation module 220 to stop generating the reset signal.

[0050] Specifically, when the first power supply is turned on, the current mirror module 210 starts to work and provides voltages at the first output end and the second output end, respectively. The reset signal generation module 220 generates a reset signal according to the voltage of the first output end of the current mirror module 210, thereby ensuring system initialization. Meanwhile, the reset signal control module 230 monitors the voltage of the second output end of the current mirror module 210, i.e., the second voltage. When it is detected that the second voltage reaches a certain preset threshold, a control signal is generated. At this time, the system voltage has reached a stable state, and the control signal acts on the reset signal generation module 220, instructing it to stop generating the reset signal, thereby allowing the system to enter a normal operating state.

[0051] In one embodiment, please refer to Figure 1The current mirror module 210 comprises a first switch M1 and a second switch M2; a first end of the first switch M1 is connected with the first power supply, a second end of the first switch M1 is a second output end of the current mirror module 210, the second end of the first switch M1 is connected with a first end of the reset signal control module 230 and a control end of the first switch M1, the control end of the first switch M1 is connected with a control end of the second switch M2; a first end of the second switch M2 is connected with the first power supply, a second end of the second switch M2 is a first output end of the current mirror module 210, the second end of the second switch M2 is connected with the reset signal generation module 220.

[0052] Optionally, the first switch M1 and the second switch M2 are PMOS tubes.

[0053] In one of the embodiments, please refer to Figure 1 The reset signal generation module 220 comprises a trigger unit Q1 and an inverting unit Q2; a first end of the trigger unit Q1 is connected with the first output end of the current mirror module 210, a second end of the trigger unit Q1 is connected with a first end of the inverting unit Q2; the trigger unit Q1 outputs a first signal when the first voltage is greater than a first trigger threshold, the inverting unit Q2 generates a reset signal by inverting the first signal; the trigger unit Q1 outputs a second signal when the control signal is less than a second trigger threshold, the inverting unit Q2 outputs a voltage value of the first power supply according to the second signal; wherein the first trigger threshold is greater than the second trigger threshold.

[0054] In one of the embodiments, the first switch is a first PMOS tube, the second switch is a second PMOS tube, and the switch unit is an NMOS tube; the trigger unit is a Schmitt trigger circuit, and the inverting unit is a NOT gate;

[0055] When the first voltage output by the second PMOS tube is greater than a first trigger threshold of the Schmitt trigger circuit, the Schmitt trigger circuit outputs a first signal, and the NOT gate outputs a reset signal according to the first signal.

[0056] In one of the embodiments, the NMOS tube is turned on when the second voltage is greater than a third preset value, and outputs a second signal.

[0057] When the second signal is less than a second trigger threshold of the Schmitt trigger circuit, the Schmitt trigger circuit outputs the second signal, and the NOT gate outputs the first signal according to the second signal. Optionally, the first signal is a high level, and the second signal is a low level.

[0058] In one of the embodiments, please refer to Figure 1The reset signal control module 230 comprises a detection unit and a switch unit M4, the detection unit comprises a first resistor R1 and a second resistor R2, and the detection unit is configured to obtain a second voltage at a second output end of the current mirror module 210; a first end of the first resistor R1 is a first end of the reset signal control module 230, the first end of the first resistor R1 is connected to the second output end of the current mirror module 210 and a control end of the switch unit M4, a second end of the first resistor R1 is connected to a first end of the second resistor R2, and a second end of the second resistor R2 is grounded; a first end of the switch unit M4 is connected to a first output end of the current mirror module 210 and the reset signal generation module 220, a second end of the switch unit M4 is grounded, the switch unit M4 is turned on when the second voltage is greater than a third preset value, and a second signal is output, and the reset signal generation module 220 generates a first signal according to the second signal.

[0059] Specifically, when the first power supply VDD is turned on and the voltage starts to rise, the first switch M1 and the second switch M2 are turned on, and the first voltage rises with the rising VDD voltage, when the first voltage is greater than a first trigger threshold of the trigger unit Q1, the output end of the trigger unit Q1 switches to the VDD voltage, and the VDD voltage can be considered as a logic high level, at this time, the inverting unit inverts the logic high level output of the trigger unit Q1 and outputs a reset signal. The reset signal is low, which ensures the initialization of the system and avoids the instability of the system voltage.

[0060] With the continuous rise of the first power supply VDD voltage, the current flowing through the first switch M1 also flows through the detection unit, and the detection unit obtains the second voltage at the second output end of the current mirror module 210 through the first resistor R1 and the second resistor R2. The second voltage rises with the first power supply VDD, and when the second voltage is greater than a third preset value, the switch unit M4 is turned on, which will pull down the point B to the ground potential, the voltage at the point B drops, and the voltage at the point B eventually drops below the second trigger threshold of the trigger unit Q1, at this time, the output end of the trigger unit Q1 is converted to ground, and the inverting unit inverts the low level output of the trigger unit Q1 and outputs a first signal, which provides a stable VDD voltage for the system. In one embodiment, as shown in Figure 2 , Figure 2 The structure diagram of the power-on reset circuit provided by another embodiment of the present application also comprises a third switch M3; a first end of the third switch M3 is connected to the first end of the second resistor R2, a second end of the third switch M3 is connected to the second end of the second resistor R2, and a control end of the third switch is connected to an output end of the reset signal generation module 220; the third switch M3 is used to be turned on when the reset signal generation module 220 outputs a reset signal, and is turned off when the reset signal generation module 220 outputs a first signal.

[0061] Specifically, when the reset signal generation module 220 outputs a high level, the third switch M3 is turned on, and the second resistor R2 is short-circuited, at this time, the second resistor R2 does not participate in voltage division; when the reset signal generation module 220 outputs a reset signal, i.e. a low level, at this time, the third switch M3 is turned off, the second resistor R2 participates in voltage division, the second voltage detected by the detection unit becomes low, and the reset signal output by the reset signal generation module 220 will remain for a period of time to ensure that the system has enough time to stabilize, thereby realizing the hysteresis function of the power-on reset circuit.

[0062] In one embodiment, as shown in Figure 3 , Figure 3 The structure diagram of the power-on reset circuit provided by the embodiment of the application, the detection unit further includes a third resistor R3; a second end of the first resistor R1 is connected with a first end of the third resistor R3; a second end of the third resistor R3 is connected with a first end of the second resistor R2, and a second end of the second resistor R2 is grounded; and the third resistor R3 is a resistor with a positive temperature coefficient.

[0063] Optionally, the resistance value of the third resistor R3 is adjustable.

[0064] Specifically, the first switch M1 in the current mirror module 210 generates a current with a negative temperature coefficient, the current passes through the first resistor R1 to generate a voltage with a negative temperature coefficient, the third resistor R3 with a negative temperature coefficient is set, the resistance value of the third resistor R3 is adjusted to neutralize the negative temperature coefficient of the first resistor R1, and then the temperature coefficient of the second voltage is zero, thereby reducing the change range of the detection unit voltage. When the reset signal generation module 220 outputs a reset signal, the third switch M3 is turned off, and the second resistor R2 participates in voltage division, but the resistance value of the second resistor R2 is much smaller than that of the first resistor R1 and the third resistor R3, so the temperature characteristics of the first switch M1, the first resistor R1 and the third resistor R3 are considered in the embodiment of the application. The temperature coefficient of the resistor can be improved to generate a resistor with a temperature characteristic close to zero, thereby improving the disadvantage that the range of the detection unit detection voltage changes greatly with temperature.

[0065] The first resistor and the third resistor are positive and negative temperature adjustment, the second resistor needs to be set to be small, and cannot be used as a reference for improving the temperature coefficient adjustment of the first resistor and the third resistor, the second resistor is not considered when designing the first resistor and the third resistor, otherwise the first resistor and the third resistor cannot play an accurate adjustment role; the second resistor and the third switch play a role in the hysteresis process, generate a resistor with a temperature characteristic close to zero, and improve the disadvantage that the POR detection point changes greatly in range with temperature.

[0066] The embodiment of the application provides an LED driving circuit, as shown in Figure 4 , Figure 4The structure schematic diagram of the LED driving circuit provided by an embodiment of the present application, the LED driving circuit comprises the power-on reset circuit as any of the above.

[0067] Optionally, the LED driving circuit further comprises a voltage stabilizer, an input end of the voltage stabilizer is connected with the positive input end of the Schmitt trigger circuit a, the frequency jitter, the correction inductor and the diode D1 in sequence, the correction inductor is connected with the frequency jitter, the inverting input end of the Schmitt trigger circuit a is connected with the 21.6V or 9.74V power supply; the output end of the voltage stabilizer, the output end of the Schmitt trigger circuit a and the input end of the NAND gate of the power-on reset circuit are connected; the correction inductor is connected with the feedback end of the integrated operational amplifier U2, the connection node between the correction inductor and the feedback end of the integrated operational amplifier U2 is further connected with the oscillator, the automatic restart unit and the output end of the NAND gate; the inverting input end of the integrated operational amplifier U2 is connected with the output end of the integrated operational amplifier U1, the non-inverting input end of the integrated operational amplifier U1 is connected with the correction inductor, the non-inverting input end of the integrated operational amplifier U2 is connected with the power supply and the non-inverting input end of the integrated operational amplifier U3 in sequence, the feedback end of the integrated operational amplifier U3 is connected with the connection node of the correction inductor and the feedback end of the integrated operational amplifier U2, the inverting input end of the integrated operational amplifier U3 is connected with the 0.3V power supply, the output ends of the integrated operational amplifier U3 and the integrated operational amplifier U2 are connected with the OR gate, the output end of the OR gate is connected with the S end of the RS flip-flop, the R end of the RS flip-flop is connected with the oscillator, the connection node of the oscillator and the R end of the RS flip-flop, the automatic restart unit, the Q end of the RS flip-flop and the connection node between the automatic restart unit and the output end of the NAND gate are all connected with the NAND gate, the output end of the NAND gate is connected with the input end of the driver, the output end of the driver is connected with the PWM dimming control module; the correction inductor and the frequency jitter are both grounded, and the voltage stabilizer is further connected with the power supply.

[0068] The PWM dimming control module can realize PWM digital dimming and variable resistance dimming by adopting the LED driving circuit in the formula (1) to change the illumination brightness of the LED lamp bead. Figure 4 The present embodiment can realize PWM digital dimming by adjusting the duty cycle of the high and low level output of the LED driving circuit to change the LED conduction time, can provide high power factor and constant current output, has excellent conduction characteristics, wide dimming range and can quickly start the driver.

[0069] The present embodiment provides a micro processing chip, as shown in the formula (2), Figure 5 The present embodiment provides a micro processing chip, as shown in the formula (2), Figure 5 The structure schematic diagram of the micro processing chip provided by an embodiment of the present application, the micro processing chip comprises the power-on reset circuit as any of the above.

[0070] The micro-processing chip can be a control module, a DSP, an MPU, a micro CPU, and the like, which can process digital signals, analog signals, or function as a micro central control chip, a system-on-chip, and the like, which can perform signal control, instruction processing, and operation.

[0071] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, and the like. For convenience of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0072] The division of units is only a logical function division, and in actual implementation, there can be another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0073] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., can be located in one place or can be distributed to a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0074] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0075] Finally, it should be noted that: other embodiments of the present application will be easily conceived by those skilled in the art after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include known or customary technical means in the art which are not disclosed in the present application, and is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is only limited by the appended claims.

Claims

1. A power-on reset circuit, characterized by comprising: The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device.

2. The power-on reset circuit of claim 1, wherein, The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device.

3. The power-on reset circuit of claim 1, wherein, The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device.

4. The power-on reset circuit of claim 2, wherein, The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation method and device. The application relates to a reset signal generation 5. The power-on reset circuit of claim 4, wherein, The first switch is a first PMOS tube, the second switch is a second PMOS tube, and the switch unit is an NMOS tube; the reset signal generation module comprises a trigger unit and an inverting unit; the trigger unit is a Schmitt trigger circuit, and the inverting unit is a non-gate; When the first voltage output by the second PMOS tube is greater than a first trigger threshold of the Schmitt trigger circuit, the Schmitt trigger circuit outputs a first signal, and the non-gate outputs the reset signal according to the first signal.

6. The power-on reset circuit of claim 5, wherein, The NMOS tube is turned on when the second voltage is greater than a third preset value, and outputs a second signal; When the second signal is less than a second trigger threshold of the Schmitt trigger circuit, the Schmitt trigger circuit outputs a second signal, and the non-gate outputs a first signal according to the second signal.

7. The power-on reset circuit of claim 4, wherein, The power-on reset circuit further comprises a third switch; The first end of the third switch is connected with the first end of the second resistor, the second end of the third switch is connected with the second end of the second resistor, and the control end of the third switch is connected with the output end of the reset signal generation module; The third switch is used for being turned on when the reset signal generation module outputs a reset signal, and being turned off when the reset signal generation module outputs a first signal.

8. The power-on reset circuit according to claim 4 or 7, wherein The detection unit further comprises a third resistor; The second end of the first resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the first end of the second resistor, and the second end of the second resistor is grounded; The third resistor is a resistor with a positive temperature coefficient.

9. An LED driving circuit, characterized by, The power-on reset circuit comprises any one of claims 1-8.

10. A microprocessing chip, characterized by The power-on reset circuit comprises any one of claims 1-8.

Images