High-reliability trench gate silicon carbide VDMOS

Abstract

The utility model provides a highly reliable trench gate silicon carbide VDMOS. The highly reliable trench gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; a lug boss is arranged on the drift layer; the first P-type well region is connected to the drift layer, and the first P-type well region is connected to the lug boss; a low-resistance region is arranged in the first P-type well region, and a groove is formed in the low-resistance region; the second P-type well region is arranged in the groove; the insulating dielectric layer is connected to the second P-type well region, and the lower part of the insulating dielectric layer is arranged in the groove; a groove is formed in the insulating medium layer; the P-type source region is connected to the first P-type well region; the N-type source region is connected to the low-resistance region, the P-type source region and the insulating dielectric layer; the conductive region is connected to the P-type well region, the lug boss and the insulating dielectric layer; the protection region is connected to the conductive region and the insulating dielectric layer; the gate metal layer is arranged in the groove; the source metal layer is connected to the P-type source region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of high-reliability trench gate silicon carbide VDMOS. BACKGROUND

[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, its performance requirements in different fields are different, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss. In aerospace and other fields, the high reliability of silicon carbide VDMOS becomes the key to application. SUMMARY

[0003] The technical problem to be solved by the utility model is to provide a kind of high-reliability trench gate silicon carbide VDMOS, which realizes the purpose of improving device reliability by optimizing the design of gate structure and source structure.

[0004] In the first aspect, the utility model provides a kind of high-reliability trench gate silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;The upper side of the drift layer is provided with a protruding part;

[0007] First P-type well region, the lower side of the first P-type well region is connected to the upper side of the drift layer, and the inner side of the first P-type well region is connected to the outer side of the protruding part;The first P-type well region is provided with low resistance zone, and the low resistance zone is provided with recess;

[0008] Second P-type well region, the second P-type well region is provided in the recess;

[0009] Insulating medium layer, the lower side of the insulating medium layer is connected to the upper side of the second P-type well region, and the lower part of the insulating medium layer is provided in the recess;The insulating medium layer is provided with trench;

[0010] P-type source region, the lower side of the P-type source region is connected to the upper side of the first P-type well region;

[0011] N-type source region, the lower side of the N-type source region is connected to the upper side of the low resistance zone, the outer side of the N-type source region is connected to the inner side of the P-type source region, and the inner side of the N-type source region is connected to the outer side of the insulating medium layer;

[0012] Conductive region, the lower side of the conductive region is connected to the upper side of the P-type well region and the upper side of the protruding part, and the outer side of the conductive region is connected to the inner side of the insulating medium layer;

[0013] Protection area, the lower side of the protection area is connected to the upper side of the conductive region, and the outer side of the protection area is connected to the inner side of the insulating medium layer;

[0014] Gate metal layer, the gate metal layer is arranged in the groove;

[0015] Source metal layer, the source metal layer is connected to the P-type source region and the N-type source region;

[0016] And, the drain metal layer is connected to the lower side of the silicon carbide substrate.

[0017] The utility model discloses the advantages are:

[0018] One, the utility model discloses the source metal layer current is introduced to the device middle, and the conductive region flows to the middle after then carries out longitudinal flow, realizes the gate control ability of device;

[0019] Two, the utility model discloses the first P-type well region and the second P-type well region are wrapped to the gate structure and the source structure of device close to the drain direction, thereby when the drain bears high voltage, the first P-type well region and the second P-type well region realize the protection of device gate and source, improve the reliability of device;

[0020] Three, the utility model discloses the middle JFET area of device, builds two layers of structure of conductive region and protection area, and the electron from the device gate structure can be introduced to the device JFET area by the conductive region, thereby can reduce the on-resistance of device, and the protection area is the voltage from the drain of device distribution in the device top, thereby can avoid the voltage influence device gate structure due to the middle electric field, improve the reliability of device;

[0021] Four, the utility model discloses the second P-type well region is built in the insulating medium layer directly below, and the second P-type well region can protect the electric field concentration of device gate corner, further improve the reliability of device. BRIEF DESCRIPTION OF DRAWINGS

[0022] The utility model will be further explained in connection with the embodiments with reference to the drawings.

[0023] Figure 1 It is the schematic diagram of the utility model high reliability trench gate silicon carbide VDMOS.

[0024] Figure 2 It is the process section of the utility model high reliability trench gate silicon carbide VDMOS Figure 1 .

[0025] Figure 3 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 2 .

[0026] Figure 4 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 3 .

[0027] Figure 5 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 4 .

[0028] Figure 6 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 5 .

[0029] Figure 7 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 6 .

[0030] Figure 8 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 7 .

[0031] Figure 9 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 8 .

[0032] Figure 10 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 9 .

[0033] Figure 11 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 10 .

[0034] Figure 12 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 10 One.

[0035] Figure 13 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 10 Two.

[0036] Figure 14 For the process section of a high-reliability trench gate silicon carbide VDMOS of the utility model Figure 10 Three.

[0037] Figure 15The utility model discloses a high reliability trench gate silicon carbide VDMOS's process section view Figure 10 Four. DETAILED DESCRIPTION

[0038] For the convenience of understanding the present application, the present application will be described more fully below with reference to the accompanying drawings. The drawings illustrate embodiments of the present application. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0040] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0041] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the included spatial description terminology can be interpreted accordingly.

[0042] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or "has" and / or "having", as used herein, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0043] As shown in Figure 1 The embodiment of the present application provides a high-reliability trench gate silicon carbide VDMOS, which comprises:

[0044] a silicon carbide substrate 101,

[0045] a drift layer 102, a lower side of the drift layer 102 being connected to an upper side of the silicon carbide substrate 101, and a protruding part 1021 being arranged on the drift layer 102;

[0046] a first P-type well region 103, an upper side of the first P-type well region 103 being connected to a lower side of the drift layer 102, and an inner side of the first P-type well region 103 being connected to an outer side of the protruding part 1021, and a low-resistance region 1031 being arranged in the first P-type well region 103, and a groove 10311 being arranged in the low-resistance region 1031;

[0047] a second P-type well region 104, the second P-type well region 104 being arranged in the groove 10311;

[0048] an insulating medium layer 105, a lower side of the insulating medium layer 105 being connected to an upper side of the second P-type well region 104, and a lower part of the insulating medium layer 105 being arranged in the groove 10311, and a trench 1051 being arranged in the insulating medium layer 105;

[0049] a P-type source region 106, a lower side of the P-type source region 106 being connected to an upper side of the first P-type well region 103;

[0050] an N-type source region 107, a lower side of the N-type source region 107 being connected to an upper side of the low-resistance region 1031, an outer side of the N-type source region 107 being connected to an inner side of the P-type source region 106, and an inner side of the N-type source region 107 being connected to an outer side of the insulating medium layer 105;

[0051] a conductive region 108, a lower side of the conductive region 108 being connected to an upper side of the P-type well region 103 and an upper side of the protruding part 1021, and an outer side of the conductive region 108 being connected to an inner side of the insulating medium layer 105;

[0052] a protection region 109, which is connected to the upper side of the conductive region 108, and is connected to the inner side of the insulating medium layer 105;

[0053] a gate metal layer 110, which is arranged in the trench 1051;

[0054] a source metal layer 111, which is connected to the P-type source region 106 and the N-type source region 107;

[0055] and a drain metal layer 112, which is connected to the lower side of the silicon carbide substrate 101.

[0056] In this embodiment, preferably, the silicon carbide substrate 101, the drift layer 102, the low-resistance region 1031 and the conductive region 108 are all N-type, and the protection region 109 is P-type.

[0057] In this embodiment, preferably, the doping concentration of the first P-type well region 103 is equal to the doping concentration of the low-resistance region 1031.

[0058] In this embodiment, preferably, the doping concentration of the conductive region 108 is less than the doping concentration of the protection region 109.

[0059] In this embodiment, preferably, the doping concentration of the P-type source region 106 is greater than the doping concentration of the N-type source region 107.

[0060] In this embodiment, preferably, the thickness of the conductive region 108 is 200 nm.

[0061] In this embodiment, preferably, the thickness of the protection region 109 is 300 nm.

[0062] As shown in FIG. 1, the silicon carbide VDMOS includes a silicon carbide substrate 101, a drift layer 102, a low-resistance region 1031, a first P-type well region 103, a protection region 109, a conductive region 108, a gate metal layer 110, a source metal layer 111 and a drain metal layer 112. Figures 1 to 15 The preparation method of the silicon carbide VDMOS includes the following steps:

[0063] Step 1, depositing a metal on the lower side of the silicon carbide substrate 101 to form the drain metal layer 112, and epitaxially growing on the upper side of the silicon carbide substrate 101 to form the drift layer 102;

[0064] Step 2, forming a barrier layer 113 on the drift layer 102, etching the barrier layer 113 to form a through hole, and performing ion implantation on the drift layer 102 to form the first P-type well region 103 and a protruding portion 1021;

[0065] Step 3, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, and performing ion implantation on the first P-type well region 103 to form a low-resistance region 114;

[0066] Step 4, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, ion implantation to the first P-type well region 103 to form a low resistance two area 115;

[0067] Step 5, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, ion implantation to the first P-type well region 103 to form a low resistance three area 116, the low resistance area 1031 including the low resistance one area 114, the low resistance two area 115 and the low resistance three area 116;

[0068] Step 6, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, ion implantation to the drift layer 102 to form a P-type source region 106;

[0069] Step 7, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, ion implantation to the drift layer 102 to form an N-type source region 107;

[0070] Step 8, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, ion implantation to the drift layer 102 to form a conductive region 108;

[0071] Step 9, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, ion implantation to the drift layer 102 to form a protection area 109;

[0072] Step 10, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, etching the drift layer 102 and the first P-type well region 103 to form a groove 10311 and a second P-type well region 104, and oxidizing to form an insulating medium layer 105, wherein the insulating medium layer 105 is provided with a groove 1051;

[0073] Step 11, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, depositing metal to form a gate metal layer 110;

[0074] Step 12, removing the original barrier layer 113, re-forming the barrier layer 113, etching the barrier layer 113 to form a through hole, depositing metal to form a source metal layer 111, and removing the barrier layer 113 to complete the preparation.

[0075] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , and the doping concentration of the N-type drift layer 102 is 1-5e16cm -3, the doping concentration of the N-type low resistance region 1031 is 1-5e17cm -3 , the doping concentration of the first P-type well region 103 and the second P-type well region 104 is 1-5e17cm -3 , the doping concentration of the N-type source region 107 is 2-8e18cm -3 , the doping concentration of the P-type source region 106 is 1-5e19cm -3 , the doping concentration of the N-type conductive region 108 is 5-9e17cm -3 , the doping concentration of the P-type protection region 109 is 1-5e18cm -3 , the insulating medium layer 105 can be silicon dioxide; the doping concentration of the silicon carbide substrate 101 is to ensure the formation of a low resistance ohmic contact with the drain metal layer 112 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the first P-type well region 103 and the second P-type well region 104 is mainly considered in two aspects, one is to protect the gate and source structure of the device, and to ensure a higher doping concentration, and the other is to ensure a smaller charge of the gate, and to ensure a lower concentration, a compromise between the two is made to select this concentration; the doping concentration of the low resistance region 1031 is mainly to reduce the on-resistance of the device, while not affecting the protection effect of the first P-type well region 103 and the second P-type well region 104 on the device structure; the N-type source region 107 and the P-type source region 106 are to reduce the ohmic contact resistance of the device source, while not damaging the device lattice due to too high concentration ion implantation, affecting the stability of the device; the concentration of the conductive region 108 is to guide the electrons from the source of the device to the JFET region, reduce the on-resistance of the device, but too high concentration will affect the gate inversion region of the device, and then affect the gate control ability of the device; the doping concentration of the protection region 109 is to prevent the electric field from spreading to the gate structure when the device is in reverse withstand voltage, and to protect the gate structure;

[0076] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the N-type drift layer 102 is 30-100 μm, which is adjusted in the above range according to different requirements of the voltage resistance characteristics of the device, the thickness of the first P-type well region 103 is 1 μm below the low resistance region 1031, 2 μm below the P-type source region 106, and 2 μm below the N-type conductive region 107; the thickness of the second P-type well region 104 is 100 nm, the thickness of the first P-type well region 103 between the low resistance region 1031 and the conductive region 108 is 200 nm; the thickness of the low resistance region 1031 is 1 μm below the N-type source region 106, 300 nm in the region directly below the second P-type well region 104, and 900 nm in the region below the conductive region 108; the bottom thickness of the insulating medium layer is 50 nm; the thicknesses of the N-type source region 107 and the P-type source region 106 are both 300 nm, and the thickness of the source metal layer 111 is 200 nm; the thickness of the conductive region 108 is 200 nm; the thickness of the protection region 109 is 300 nm; the width of the first P-type well region 103 of the device accounts for 60-70% of the total width of the device, so as to ensure that the on-resistance of the low resistance region 1031 of the device is small enough to ensure the conduction performance of the device.

[0077] The utility model discloses the current of the source metal layer 111 of the both sides of device is introduced to the middle of device, and the N-type conductive region 108 flows to the middle again after longitudinal flow, realizes the gate control ability of device, this mode realizes the first P-type well region 103 and the second P-type well region 104 to the package of the gate structure and the source structure of device close to the drain direction, thereby when the drain bears high voltage, the first P-type well region 103 and the second P-type well region 104 realize the protection of the gate and the source of device, improve the reliability of device.

[0078] In the middle JFET area of the device, the N-type conductive region 108 and the P-type protection region 109 two-layer structure are constructed, the N-type conductive region 108 can guide the electrons from the gate structure of the device into the JFET area of the device, so as to reduce the on-resistance of the device, and the P-type protection region 109 can inhibit the voltage distribution caused by the drain of the device on the top of the device, so as to avoid the influence of the voltage of the middle electric field on the gate structure of the device, improve the reliability of the device, and the second P-type well region 104 is constructed below the insulating medium layer 105 of the device, which can protect the electric field concentration at the corner of the gate of the device, and further improve the reliability of the device.

[0079] Through the design of the device structure, the first P-type well region 103 and the second P-type well region 104 can realize the package protection of the gate and the source structure of the device, so as to effectively inhibit the damage of the device caused by the voltage impact of the drain, improve the reliability of the device, and the P-type protection region 109 can complete the protection of the gate structure of the device from the perspective of the conductive channel of the device, and realize the high reliability of the device.

[0080] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A high-reliability trench-gate silicon carbide VDMOS, characterized in that: The application relates to a silicon carbide substrate, a drift layer connected to the upper side of the silicon carbide substrate, a convex part provided on the drift layer, a first P-type well region connected to the upper side of the drift layer and connected to the outer side of the convex part, a low-resistance region provided in the first P-type well region, a groove provided in the low-resistance region, a second P-type well region provided in the groove, an insulating medium layer connected to the upper side of the second P-type well region and provided in the groove, a groove provided in the insulating medium layer, a P-type source region connected to the upper side of the first P-type well region, an N-type source region connected to the upper side of the low-resistance region, the inner side of the N-type source region connected to the inner side of the P-type source region, the inner side of the N-type source region connected to the outer side of the insulating medium layer, a conductive region connected to the upper side of the P-type well region and the upper side of the convex part, the outer side of the conductive region connected to the inner side of the insulating medium layer, a protection region connected to the upper side of the conductive region and the inner side of the insulating medium layer, a gate metal layer provided in the groove, a source metal layer connected to the P-type source region and the N-type source region, and a drain metal layer connected to the lower side of the silicon carbide substrate. The silicon carbide substrate, the drift layer, the low-resistance region and the conductive region are all N-type, and the protection region is P-type. The doping concentration of the first P-type well region is equal to the doping concentration of the low-resistance region. The doping concentration of the conductive region is less than the doping concentration of the protection region. The doping concentration of the P-type source region is greater than the doping concentration of the N-type source region. The thickness of the conductive region is 200 nm. The thickness of the protection region is 300 nm. ​ ​ ​ ​ ​ ​ 2. The high-reliability trench-gate silicon carbide VDMOS of claim 1, wherein: ​ 3. The high reliability trench gate silicon carbide VDMOS of claim 1, wherein: ​ 4. A high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: ​ 5. A high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: ​ 6. The high reliability trench gate silicon carbide VDMOS of claim 1, wherein: the n- drift region has a first doping concentration; the p-body region has a second doping concentration; and the second doping concentration is greater than the first doping concentration. ​ 7. A high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: ​

Images