IPD capacitor for optimizing layout design

Abstract

The utility model relates to an IPD capacitor with an optimized layout design. The IPD capacitor comprises a PAD, a capacitor action area, an equipotential ring, a grounding area and a scribing channel. The scribing channel and the equipotential ring are both closed contour lines, and the equipotential ring is arranged in the scribing channel; at least one grounding area is arranged on the inner side of the equipotential ring, and a grounding hole is formed in the grounding area. And the PAD and the capacitance action region are arranged in the equipotential ring. The capacitance action region comprises a long-strip-shaped capacitance value realization region and an extension part; the extension part is arranged on the side edge of one side, far away from the PAD, of the capacitance value realization area; the extension part is provided with a via hole arranged along the length direction of the capacitance value realization area. A circle of equipotential ring is arranged on the inner side of the scribing channel of the IPD capacitor and is grounded, so that potential migration of silver ions can be effectively blocked when the capacitor is powered up. The extension part is arranged on the side edge of the capacitance value realization area, and the through hole is arranged on the extension part for grounding, so that only the non-capacitance value realization area is influenced when the through hole is deformed due to stress, the influence on the capacitance value of the capacitor is reduced, and the reliability risk of medium cracking is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of integrated circuit, especially to an IPD capacitor with optimized layout design. BACKGROUND

[0002] IPD refers to a technology for manufacturing metal traces and passive devices such as capacitors, inductors, resistors, and baluns on a specific substrate material using semiconductor processes. IPD capacitors are fabricated using semiconductor processes and can achieve relatively large capacitance values with a small active area.

[0003] RF power amplifiers are an important component of wireless communication systems. The pre-matching scheme of RF power amplifiers usually uses capacitors, inductors, and other components to build a matching network. Compared with the IPD capacitors (typical size ≤ 0.3mm*0.3mm) commonly used in filters and monolithic microwave integrated circuits, the IPD capacitors used in the matching network of power tubes have larger sizes (typical size ≥ 3.6mm*1.3mm), so the reliability risk of the latter is also increased compared with the former.

[0004] The reliability risks of IPD capacitors in the prior art include: 1. During power-on, silver ions in the conductive silver paste at the bottom of the capacitor may migrate, causing device failure. 2. During the bonding process of the IPD capacitor and in actual use scenarios, the via is usually directly connected from the lower plate under the capacitance implementation area to the back gold ground through the substrate. The via will be subjected to thermal stress impact, resulting in thermal expansion and contraction deformation, ultimately causing the lower plate and dielectric layer of the capacitance implementation area to deform, causing the capacitance value to deviate from the design value, and even causing the dielectric layer to crack, resulting in capacitor failure. UTILITY MODEL CONTENTS

[0005] To solve the problems of device failure caused by silver ion migration at the bottom of the capacitor in the prior art, deformation of the lower plate and dielectric layer caused by the existing via processing method, and deviation of the capacitance value from the design value, the utility model provides an IPD capacitor with optimized layout design, which comprises a PAD, a capacitor action area, an equipotential ring, a grounding area, and a scribe lane.

[0006] The scribe lane and the equipotential ring are both closed contour lines, and the equipotential ring is arranged in the scribe lane. At least one grounding area is arranged on the inner side of the equipotential ring. The equipotential ring and the grounding area are consistent, and sequentially comprise a lower plate, a substrate, and a back gold from top to bottom. A grounding hole is arranged in the grounding area, and the grounding hole penetrates the substrate and the back gold. The grounding hole and the equipotential ring are connected through the respective lower plates.

[0007] The PAD and the capacitive area are arranged in the equipotential ring, and the number of the PAD and the capacitive area is determined according to the capacitance value and the design requirement of the capacitive cell.

[0008] The capacitive area comprises a long strip-shaped capacitance value realizing area and an extension part; the capacitance value realizing area comprises, from top to bottom, an upper electrode plate, a dielectric layer, a lower electrode plate, a substrate and a back metal; the lower electrode plate, the substrate and the back metal extend to form the extension part, which is arranged at a side edge of the capacitance value realizing area away from the PAD; the extension part is provided with a via arranged along the length direction of the capacitance value realizing area, and the via penetrates the substrate and the back metal.

[0009] Further, the PAD and the capacitive area are connected through the upper electrode plate.

[0010] Further, at least one PAD is arranged in the equipotential ring, and the single PAD is connected with at least one capacitive area.

[0011] Further, the upper electrode plate and the lower electrode plate are made of a high-conductivity metal material.

[0012] Further, the dielectric layer is made of SiN material.

[0013] Further, the substrate is made of GaAs material.

[0014] Compared with the prior art, the utility model has the following beneficial effects:

[0015] I. By arranging an equipotential ring in the inside of the IPD capacitor's scribing channel and grounding the inside of the equipotential ring, the potential migration of silver ions in the conductive silver adhesive at the bottom of the capacitor can be effectively blocked when the capacitor is powered, thereby avoiding the risk of device failure caused by silver ion migration.

[0016] II. By extending the lower electrode plate, the substrate and the back metal layer of the capacitance value realizing area to form an extension part, and leading the via from the lower electrode plate of the extension part to the back metal through the substrate, this kind of mode can only affect the non-capacitance value realizing area when the via is deformed due to stress, thereby reducing the influence on the capacitance value, avoiding the reliability risk of dielectric cracking, and ensuring the normal transmission of radio frequency signals.

[0017] Through the above technical means, the reliability of the IPD capacitor is greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a plan view of a single IPD capacitor form one in the embodiment of the utility model;

[0019] Figure 2The plane view of the single IPD capacitor form two in the embodiment of the utility model;

[0020] Figure 3 The structure layer schematic view of the capacitor action area in the embodiment of the utility model;

[0021] Figure 4 The structure layer schematic view of the equipotential ring and grounding area in the embodiment of the utility model;

[0022] In the drawing: 1, PAD; 2, capacitor action area; 3, equipotential ring; 4, grounding point; 5, capacitance realization area; 6, extension; 7, upper pole plate; 8, dielectric layer; 9, lower pole plate; 10, substrate; 11, back gold; 12, via hole; 13, equipotential ring; 14, grounding area; 15, scribing path. DETAILED DESCRIPTION

[0023] In order to make the person skilled in the art better understand the utility model scheme, the technical scheme in the embodiment of the utility model will be described clearly and completely below in combination with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment in the utility model, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the utility model.

[0024] It should be noted that the terms "first", "second" and the like in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. The terms "up", "down", "front", "back", "top", "bottom" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the utility model and simplify the description, and do not indicate or imply that the device or part referred to must have a particular orientation, be constructed and operated in a particular orientation, so it cannot be understood as a limitation on the utility model. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the utility model described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0025] As Figure 1 and Figure 2 shown, an IPD capacitor for optimizing layout design includes PAD 1, capacitor action area 2, equipotential ring 3, grounding area 14 and scribing path 15. Wherein PAD 1 is used for gold wire bonding.

[0026] Scribing path 15 and equipotential ring 3 are both closed contour lines, and equipotential ring 3 is arranged inside scribing path 15; At least one grounding area 14 is arranged inside equipotential ring 3. AsFigure 4 As shown, the equipotential ring 3 and the grounding area 14 are consistent, and sequentially include the lower plate 9, the substrate 10 and the back gold 11 from top to bottom; the grounding hole 4 is arranged in the grounding area 14, and the grounding hole 4 penetrates the substrate 10 and the back gold 11; the grounding hole 4 and the equipotential ring 3 are connected through the respective lower plate 9.

[0027] By arranging a circle of equipotential ring 3 inside the scribe lane 15 of the IPD capacitor and grounding inside the equipotential ring 3, the potential migration of silver ions in the conductive silver adhesive at the bottom of the capacitor can be effectively blocked when the capacitor is powered on, thereby avoiding the risk of device failure caused by silver ion migration.

[0028] The PAD 1 and the capacitor action area 2 are arranged inside the equipotential ring 3, and the number of the PAD 1 and the capacitor action area 2 is determined according to the capacitance size and the capacitor cell design requirement.

[0029] The capacitor action area 2 includes a long strip-shaped capacitance implementation area 5 and an extension 6. As shown, Figure 3 The capacitance implementation area 5 sequentially includes the upper plate 7, the dielectric layer 8, the lower plate 9, the substrate 10 and the back gold 11 from top to bottom. As shown, Figure 3 and Figure 1 The lower plate 9, the substrate 10 and the back gold layer 11 are extended to form the extension 6, and the extension 6 is arranged at the side edge away from the PAD 1 along the capacitance implementation area 5. The extension 6 is provided with a via hole 12 arranged along the length direction of the capacitance implementation area 5, and the via hole 12 penetrates the substrate 10 and the back gold 11.

[0030] By extending the lower plate 9, the substrate 10 and the back gold layer 11 of the capacitor action area to form the extension, and leading the via hole 12 out from the lower plate 9 of the extension and through the substrate 10 to the back gold 11 for grounding, when the via hole 12 is deformed due to stress, only the non-capacitor action area is affected, the influence on the capacitance is reduced, the reliability risk of dielectric cracking is avoided, and the normal transmission of the radio frequency signal is ensured.

[0031] The PAD 1 and the capacitor action area 2 are connected through the upper plate 7.

[0032] At least one PAD 1 is arranged in the equipotential ring 3, and a single PAD 1 is connected with at least one capacitor action area 2.

[0033] As shown, Figure 1 Two capacitance carrying areas with capacitances of 15pF and 20pF are arranged in the equipotential ring 3. It is defined that the capacitance carrying area with the capacitance of 15pF is located in the upper part of the Figure 1 equipotential ring 3, and the capacitance carrying area with the capacitance of 20pF is located in the Figure 1The lower part of the equipotential ring 3. To save space, the two capacitance values ​​are arranged symmetrically vertically within the equipotential ring 3, with a total of four PADs 1. Each PAD 1 is connected to a capacitor function area 2, so the two capacitor function areas 2 at the top each bear a capacitance value of 7.5pF, and the two capacitor function areas 2 at the bottom each bear a capacitance value of 10pF.

[0034] like Figure 2 As shown, two capacitance carrying regions with capacitance values ​​of 25pF and 30pF are set within the equipotential ring 3. The capacitance carrying region with a capacitance value of 25pF is now defined as located in... Figure 2 The upper part of the intermediate potential ring 3, the capacitive carrying area with a capacitance of 30pF is located in Figure 2 The lower part of the equipotential ring 3. To save space, two capacitance carrying areas are symmetrically arranged vertically within the equipotential ring 3, with a total of four PADs 1. Each PAD 1 in the capacitance carrying area with a capacitance value of 25pF is connected to a capacitance function area 2, so the two capacitance function areas 2 in the upper part each bear a capacitance value of 12.5pF. Alternatively, a cell design can be implemented, which is achieved by connecting multiple capacitance values ​​to a single PAD 1 to area 5. For example... Figure 2 In the diagram, each PAD 1 within the 30pF capacitance-carrying region is connected to two capacitor function regions 2, thus each capacitor function region 2 in the lower part carries a capacitance of 7.5pF. It's important to note that cell-based design is not necessary; it's only required when the corresponding inner matching network needs stability optimization. In other cases, a single-cell design (a single PAD 1 connected to a single capacitance implementation region 5) is sufficient.

[0035] The upper electrode 7 and the lower electrode 9 are made of highly conductive metallic materials to reduce the series resistance of the capacitor. For example, gold and cobalt are metals with good conductivity and chemical stability, high mechanical strength, and are not easily deformed, which can effectively improve the stability and reliability of the electrode structure.

[0036] The dielectric layer 8 is made of SiN material. SiN has a high dielectric constant and low loss. Using SiN as the insulating dielectric layer in IPD capacitors can improve the energy storage capacity of the capacitor while reducing its size. In addition, it has good chemical stability, high hardness, and high mechanical strength, which can effectively improve the reliability and service life of IPD capacitors.

[0037] Substrate 10 is made of GaAs material. GaAs material itself has excellent high-frequency characteristics, and the IPD process of GaAs substrate can achieve low cost, low loss, miniaturization and high integration.

[0038] The above merely describes preferred embodiments of the present application, and is not intended to limit the scope of the present application. It should be noted that, for those of ordinary skill in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should be encompassed within the scope of protection of the present application.

Claims

1. An IPD capacitance for optimizing layout design, characterized in that, The PAD (1), the capacitive area (2), the equipotential ring (3), the grounding area (14) and the scribe lane (15) are included. The scribe lane (15) and the equipotential ring (3) are both closed contour lines, and the equipotential ring (3) is arranged in the scribe lane (15); at least one grounding area (14) is arranged inside the equipotential ring (3); the equipotential ring (3) and the grounding area (14) are consistent, and sequentially include the lower plate (9), the substrate (10) and the back gold (11) from top to bottom; a grounding hole (4) is arranged in the grounding area (14), and the grounding hole (4) penetrates the substrate (10) and the back gold (11); the grounding hole (4) and the equipotential ring (3) are connected through the respective lower plate (9). The PAD (1) and the capacitive area (2) are arranged in the equipotential ring (3), and the number of the PAD (1) and the capacitive area (2) is determined according to the capacitance value and the design requirement of the capacitive cell. The capacitive area (2) includes a long strip-shaped capacitance value realization area (5) and an extension part (6); the capacitance value realization area (5) sequentially includes the upper plate (7), the dielectric layer (8), the lower plate (9), the substrate (10) and the back gold (11) from top to bottom; the lower plate (9), the substrate (10) and the back gold (11) extend to form the extension part (6), and the extension part (6) is arranged at the side edge away from the PAD (1) along the capacitance value realization area (5); the extension part (6) is provided with a via (12) arranged along the length direction of the capacitance value realization area (5), and the via (12) penetrates the substrate (10) and the back gold (11).

2. The IPD capacitor of claim 1, wherein, The PAD (1) and the capacitive area (2) are connected through the upper plate (7).

3. The IPD capacitor of claim 1, wherein, At least one PAD (1) is arranged in the equipotential ring (3), and a single PAD (1) is connected with at least one capacitive area (2).

4. The IPD capacitor of claim 1, wherein, The upper plate (7) and the lower plate (9) are made of a high-conductivity metal material.

5. The IPD capacitor of claim 1, wherein, The dielectric layer (8) is made of SiN material.

6. The IPD capacitor of claim 1, wherein, The substrate (10) is made of GaAs material.

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