Semiconductor power device packaging structure

Abstract

The utility model discloses a packaging structure of a semiconductor power device. The packaging structure comprises a lead frame, three half-bridge branches, a copper bridge, leads and a packaging body, each half-bridge branch comprises two switch chips which are connected in series; the lead frame comprises three half-bridge midpoint end copper sheets, a power supply end copper sheet, a plurality of source electrode lead-out copper sheets and a plurality of grid electrode lead-out copper sheets; the copper bridges comprise three two-point supporting copper bridges and three three-point supporting copper bridges; each source electrode lead-out copper sheet comprises edge pins arranged in pairs, and the bottom surfaces of the edge pins arranged in pairs are exposed out of the packaging body and are communicated on the bonding pad surface. According to the utility model, the integration level of the chip is improved by adopting a 6in 1 sealing mode, the internal interconnection structure is optimized and the parasitic inductance / capacitance is reduced in the integrated packaging, so that the switching speed of a power device is improved, the dynamic loss is reduced by more than 30%, the packaging volume is reduced by 60% compared with that of the traditional scheme, and the packaging structure is suitable for high-density scenes such as mobile equipment, vehicle-mounted electronics and the like.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip technical field, especially a kind of semiconductor power device packaging structure. BACKGROUND

[0002] The packaging structure of electronic component mainly includes chip and pin etc. arranged in package body, and pin is used to lead out the internal circuit of chip, so as to connect chip with external circuit or external device through pin.

[0003] With the development of computer, communication, automobile electronics, aerospace industry and other consumer system field, high integration power packaging form effectively integrates and packages multiple power devices on a substrate by optimizing packaging structure and process. This packaging form significantly improves the integration of chip, so that the power handling capacity in unit area is greatly improved. A common MOS switch circuit is shown in Figure 1 As the switch chip needs better heat dissipation under the working condition of large working current, how to package 6 MOS in one packaging structure and optimize the resistance of each chip electrode leading out to pin and heat dissipation channel is a problem to be solved. SUMMARY

[0004] Therefore, the utility model provides a packaging structure, which leads out the source electrode and gate electrode of each switch to the first edge / third edge, uses copper sheet lead frame and copper bridge to realize the electrical / thermal connection between chip and outer surface of packaging structure, can reduce resistance, fully and uniformly dissipate heat of chip, and each source electrode of chip is provided with a pair of adjacent edge pins connected on pad surface, to further increase welding area, so as to solve the above problems.

[0005] Based on the above purpose, the utility model provides a semiconductor power device packaging structure, which comprises lead frame, three half-bridge branches, copper bridge, lead wire and package body.

[0006] Each half-bridge branch comprises two switch chips connected in series; the two switch chips comprise upper switch and lower switch; the switch chip has first surface and second surface, the drain electrode of the switch chip is arranged on the first surface, and the source electrode and gate electrode of the switch chip are arranged on the second surface.

[0007] The lead frame comprises three half-bridge midpoint end copper sheets, one power end copper sheet, a plurality of source lead-out copper sheets and a plurality of gate lead-out copper sheets, the upper switch corresponding to each half-bridge branch is arranged on the power end copper sheet, and the lower switch corresponding to each half-bridge branch is arranged on the corresponding half-bridge midpoint end copper sheet; the first surface of the switch chip is arranged towards the lead frame; the semiconductor power device package structure has a pad surface, the pad surface has first to fourth edges in sequence, and the first edge and the third edge are parallel; the power end copper sheet extends from the second edge to the fourth edge; the half-bridge midpoint end copper sheet array is arranged on the side of the power end copper sheet facing the third edge; the source lead-out copper sheet and the gate lead-out copper sheet corresponding to the upper switch are arranged along the first edge; and the source lead-out copper sheet and the gate lead-out copper sheet corresponding to the lower switch are arranged along the third edge.

[0008] The copper bridge comprises three two-point support copper bridges and three three-point support copper bridges; one end of the two-point support copper bridge is electrically connected with the source electrode of the lower switch, and the other end is electrically connected with the corresponding source lead-out copper sheet; the middle part of the three-point support copper bridge is electrically connected with the source electrode of the upper switch, one end of the three-point support copper bridge is electrically connected with the corresponding half-bridge midpoint end, and the other end is electrically connected with the corresponding source lead-out copper sheet; the gate electrode of the switch chip is electrically connected with the corresponding gate lead-out copper sheet through a lead wire.

[0009] The package body covers the lead frame, the switch chip, the copper bridge and the lead wire; the bottom surfaces of the half-bridge midpoint end copper sheet and the power end copper sheet are exposed to the package body; each source lead-out copper sheet comprises a pair of edge pins arranged in pairs, and the bottom surfaces of the pair of edge pins are exposed to the package body and are in communication with the pad surface.

[0010] Preferably, each gate lead-out copper sheet comprises one edge pin; the side end surface of the corresponding edge pin of the source lead-out copper sheet and the gate lead-out copper sheet is provided with a concave area in the middle, and the concave area is used for increasing the contact area with solder during welding.

[0011] Preferably, the power end copper sheet and the half-bridge midpoint end copper sheet are provided with edge pins, and the corresponding edge pins of the power end copper sheet and the half-bridge midpoint end copper sheet are arranged along the second edge and the fourth edge.

[0012] Preferably, the edge pins are arranged in the same position along the first edge and the third edge.

[0013] Preferably, the concave area is formed by dividing the hole wall area after punching.

[0014] Preferably, a shallow groove is arranged on the chip arrangement surface of the lead frame.

[0015] In conclusion, the utility model has the following beneficial effects:

[0016] 1) The utility model discloses a 6in1 sealing form is improved the integration of chip, and the integrated package passes through the optimization internal interconnection structure, reduces parasitic inductance / capacitance, makes power device switching speed promotion, dynamic loss reduces more than 30%, and the package volume reduces 60% than traditional scheme, is applicable to mobile device, vehicle-mounted electronic etc. High density scene. The source and the grid of each switch are led out to the first edge / third edge in the vicinity, and the copper sheet lead frame and copper bridge are used to realize the electric / thermal connection between the chip and the outer surface of the package structure, which can reduce the resistance while more fully and uniformly dissipating heat from the chip.

[0017] 2) The utility model discloses a pair of adjacent edge pins of each chip source are arranged on the pad surface, which can increase the welding area, reduce the thermal resistance and further make the equivalent R dson Uniform;

[0018] 3) The utility model discloses a recessed area is arranged in the middle of the side end face of each edge pin of the first edge and the third edge of the package structure, which can increase the contact area between the pin and the solder during welding, make the molten solder further climb under the action of surface tension, and make the welding more firm. DRAWINGS

[0019] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0020] Figure 1 The circuit diagram of the embodiment of the utility model;

[0021] Figure 2 The pad surface pin distribution diagram of the embodiment of the utility model;

[0022] Figure 3 The top view and side view of the internal structure of the embodiment of the utility model. DETAILED DESCRIPTION

[0023] The technical scheme in the embodiments of the utility model will be described clearly and completely in combination with the drawings in the embodiments of the utility model, and obviously, the described embodiments are only some embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the utility model.

[0024] Figure 1The circuit diagram of the embodiment is shown, the semiconductor power device package structure of the embodiment includes a first half-bridge branch, a second half-bridge branch and a third half-bridge branch, each half-bridge branch includes two series-connected semiconductor power devices (all are N-type MOS switch chips, two switch chips are respectively marked as upper switch and lower switch); the first half-bridge branch includes the sixth switch Q6 (upper switch) and the first switch Q1 (lower switch), the source S6 of the sixth switch Q6 and the drain D1 of the first switch Q1 are electrically connected to form a half-bridge midpoint A end; the second half-bridge branch includes the fifth switch Q5 (upper switch) and the second switch Q2 (lower switch), the source S5 of the fifth switch Q5 and the drain D2 of the second switch Q2 are electrically connected to form a half-bridge midpoint B end; the third half-bridge branch includes the fourth switch Q4 (upper switch) and the third switch Q3 (lower switch), the source S4 of the fourth switch Q4 and the drain D3 of the third switch Q3 are electrically connected to form a half-bridge midpoint C end; the drain D6 / 5 / 4 of the upper switch is electrically connected to form a power supply D end; the source S1 / 2 / 3 / 4 / 5 / 6 and the gate G1 / 2 / 3 / 4 / 5 / 6 of each switch are respectively led out to form corresponding edge pins.

[0025] Figure 2The pin layout of the pad surface of the present embodiment is shown, the pad surface has first to fourth edges in turn adjacent, the first and third edges are parallel, and the second and fourth edges are parallel; the pad corresponding to the power supply D end (i.e. drain D4 / 5 / 6) extends horizontally from the second edge to the large-area middle pad of the fourth edge, and two edge pins are arranged on the second and fourth edges respectively. The middle pad array corresponding to the half-bridge midpoint C end (i.e. source S4 / drain D3), the half-bridge midpoint B end (i.e. source S5 / drain D2) and the half-bridge midpoint A end (i.e. source S6 / drain D1) is arranged on the side of the middle pad corresponding to the power supply D end towards the third edge; the pads corresponding to the half-bridge midpoint A / B / C ends are rectangular, the pad of the half-bridge midpoint C end extends to the second edge and two edge pins are arranged on the second edge, and the pad of the half-bridge midpoint A end extends to the fourth edge and two edge pins are arranged on the fourth edge. The edge pins corresponding to the sources S4 / 5 / 6 and gates G4 / 5 / 6 of the upper switches are arranged in the order of S4, S4, G4, S5, S5, G5, S6, S6 and G6 on the first edge; the edge pins corresponding to the sources S1 / 2 / 3 and gates G1 / 2 / 3 of the lower switches are arranged in the order of G3, S3, S3, G2, S2, S2, G1, S1 and S1 on the third edge; the pads corresponding to the sources S1 / 2 / 3 / 4 / 5 / 6 of the respective switches are arranged as a pair of pads in communication on the pad surface, and a concave area is arranged in the middle of the side end face of each edge pin (i.e. the pin corresponding to the extracted source S1 / 2 / 3 / 4 / 5 / 6 and gate G1 / 2 / 3 / 4 / 5 / 6) on the first and third edges, which is used to increase the contact area between the pin and the solder when the packaging structure of the present embodiment is welded with the external circuit board, so that the molten solder can further climb under the action of its surface tension, and the welding is more firm. In a preferred embodiment, the array of edge pins is arranged in the same position along the first and third edges, which is convenient for connecting with the adjacent structure unit in the continuous sheet structure, and the concave area at the side end face of the edge pin can be formed by punching the corresponding connecting part and cutting the board after the hole wall area.

[0026] Figure 3 The top view and side view of the internal structure of the present embodiment are shown, and the semiconductor power device packaging structure further includes a lead frame 1, a copper bridge, a lead wire 4 and a packaging body 5. The lead frame 1 includes copper sheets 1-A / 1-B / 1-C corresponding to the half-bridge midpoint A / B / C ends, a copper sheet 1-D corresponding to the power supply D end, source lead-out copper sheets 1-S corresponding to the sources S1 / 2 / 3 / 4 / 5 / 6 of the respective switches, and gate lead-out copper sheets 1-G corresponding to the gates G1 / 2 / 3 / 4 / 5 / 6 of the respective switches. The arrangement positions of the respective copper sheets and the pad positions of Figure 2 correspond (since Figure 2 is the bottom view of the pad surface, and therefore corresponds to Figure 3The copper sheet 1-A / 1-B / 1-C / 1-D is provided with a shallow groove 6 on the chip setting surface (the surface facing the inside of the packaging structure), which can increase the bonding between the package 5 and the lead frame 1 and prevent the two from delaminating when the packaging structure is used in a high-temperature environment. The first to sixth switches Q1 / 2 / 3 / 4 / 5 / 6 are all longitudinal devices, each having a first surface and a second surface, the drain D1 / 2 / 3 / 4 / 5 / 6 being provided on the first surface, the source S1 / 2 / 3 / 4 / 5 / 6 and the gate G1 / 2 / 3 / 4 / 5 / 6 being provided on the second surface, and the first surface of each switch facing the lead frame 1; the copper bridge includes first to sixth copper bridges corresponding to each switch chip, wherein the first to third copper bridges corresponding to the lower switches are two-point support copper bridges 2, and the fourth to sixth copper bridges corresponding to the upper switches are three-point support copper bridges 3 (i.e., the copper bridge is used for electrical connection between three places). The first switch Q1 is provided on the copper sheet 1-A, the second switch Q2 is provided on the copper sheet 1-B, and the third switch Q3 is provided on the copper sheet 1-C. The two ends of each two-point support copper bridge 2 are respectively electrically connected to the source S1 / 2 / 3 of the corresponding switch chip and the source lead-out copper sheet 1-S corresponding thereto. The sixth switch Q6, the fifth switch Q5, and the fourth switch Q4 are sequentially provided on the copper sheet 1-D; the middle part of each three-point support copper bridge 3 is respectively electrically connected to the source S6 / 5 / 4 of the corresponding switch chip, one end of each three-point support copper bridge 3 is electrically connected to the half-bridge midpoint copper sheet 1-A / 1-B / 1-C corresponding to the half-bridge branch of the same half-bridge branch, and the other end is electrically connected to the source lead-out copper sheet 1-S corresponding to the switch chip. Therefore, each switch chip can directly dissipate heat from the first surface to the pad surface on one hand, and can also dissipate heat from the second surface to the edge pin corresponding to the source through the copper bridge on the other hand, so that each switch can more evenly dissipate heat to the outside. The gate G1 / 2 / 3 / 4 / 5 / 6 of each switch chip and the corresponding gate lead-out copper sheet 1-G are electrically connected through the lead wire 4. The package 5 covers the lead frame 1, the first to sixth switches Q1 / 2 / 3 / 4 / 5 / 6, the copper bridge, and the lead wire 4, each pad of the pad surface is exposed to the package 5, and each edge pin is exposed to the package 5 on the side surface.

[0027] The size of the semiconductor power device package structure of the embodiment is 10*12mm, the source and the gate of each switch are led out to the first edge / third edge, and the copper sheet lead frame and the copper bridge are used to realize the electrical / thermal connection between the chip and the outer surface of the package structure, so that the heat dissipation of the chip can be more fully and uniformly while reducing the resistance and the parasitic inductance / capacitance, on the other hand, the source of each chip is led out and is provided with a pair of adjacent edge pins which are in communication on the pad surface, so that the welding area can be increased and the equivalent R dson is further reduced, and the uniformity is improved. The middle of the side end surface of each edge pin of the first edge and the third edge is provided with a concave area, so that the contact area between the pin and the tin climbing can be increased during welding, the molten solder is further climbed under the action of the surface tension, and the welding is more firm.

[0028] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor power device package structure, characterized by, The semiconductor power device package structure comprises a lead frame, three half-bridge branches, a copper bridge, leads and a package body. Each of the half-bridge branches comprises two switch chips connected in series; the two switch chips comprise an upper switch and a lower switch; the switch chips have a first face and a second face, the drain of the switch chip is arranged on the first face, and the source and the gate of the switch chip are arranged on the second face. The lead frame comprises three half-bridge midpoint end copper sheets, one power end copper sheet, a plurality of source lead-out copper sheets and a plurality of gate lead-out copper sheets, the upper switch of each half-bridge branch is arranged on the power end copper sheet, and the lower switch of each half-bridge branch is arranged on the corresponding half-bridge midpoint end copper sheet; the first face of the switch chip faces the lead frame; the semiconductor power device package structure has a pad face, the pad face has a first edge to a fourth edge arranged in sequence, the first edge and the third edge are parallel; the power end copper sheet extends from the second edge to the fourth edge; the half-bridge midpoint end copper sheet array is arranged on the side of the power end copper sheet facing the third edge; the source lead-out copper sheet and the gate lead-out copper sheet corresponding to the upper switch are arranged along the first edge; the source lead-out copper sheet and the gate lead-out copper sheet corresponding to the lower switch are arranged along the third edge. The copper bridge comprises three two-point support copper bridges and three three-point support copper bridges. One end of the two-point support copper bridge is electrically connected with the source of the lower switch, and the other end is electrically connected with the corresponding source lead-out copper sheet; the middle part of the three-point support copper bridge is electrically connected with the source of the upper switch, one end of the three-point support copper bridge is electrically connected with the corresponding half-bridge midpoint end, and the other end is electrically connected with the corresponding source lead-out copper sheet; the gate of the switch chip is electrically connected with the corresponding gate lead-out copper sheet through the lead. The package body covers the lead frame, the switch chip, the copper bridge and the lead; the bottom surface of the half-bridge midpoint end copper sheet and the power end copper sheet is exposed to the package body; each of the source lead-out copper sheets comprises a pair of edge pins arranged in pairs, and the bottom surface of the pair of edge pins is exposed to the package body and communicates with the pad face.

2. The semiconductor power device package structure of claim 1, wherein, Each of the gate lead-out copper sheets comprises an edge pin; the middle part of the side end face of the corresponding edge pin of the source lead-out copper sheet and the gate lead-out copper sheet is provided with a concave area, and the concave area is used for increasing the contact area with the solder during welding.

3. The semiconductor power device package structure of claim 1, wherein, The power end copper sheet and the half-bridge midpoint end copper sheet are provided with edge pins, and the corresponding edge pins of the power end copper sheet and the half-bridge midpoint end copper sheet are arranged along the second edge and the fourth edge.

4. The semiconductor power device package structure of claim 2, wherein, The arrangement positions of the edge pins along the first edge and the third edge are the same.

5. The semiconductor power device package structure of claim 2, wherein, The concave area is formed by dividing the hole wall area after punching.

6. The semiconductor power device package structure of claim 1, wherein, The chip arrangement surface of the lead frame is provided with a shallow groove.

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