Display device

Abstract

A display device includes: a display panel including a display area and a non-display area; a plurality of light emitting elements in the display area; and a current detection device in the non-display area. The current detection device includes a controller and a current detection circuit configured to be controlled by the controller. The current detection circuit comprises a first driver and a second driver; the first driver includes a first dummy light emitting element corresponding to a first light emitting element configured to provide light of a first color among the plurality of light emitting elements; and the second driver includes a second dummy light emitting element corresponding to a second light emitting element configured to provide light of a second color among the plurality of light emitting elements.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0019575, filed on February 8, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to display devices, and more specifically, to display devices capable of quantitatively measuring the value of lateral leakage current between pixels. Background Technology

[0004] Organic light-emitting display devices include display elements, such as organic light-emitting diodes, whose brightness is changed by electric current. Utility Model Content

[0005] One or more embodiments of this disclosure may relate to a display device capable of quantitatively measuring the value of lateral leakage current between pixels.

[0006] According to one or more embodiments of this disclosure, a display device includes: a display panel including a display area and a non-display area; a plurality of light-emitting elements in the display area; and a current detection device in the non-display area. The current detection device includes a controller and a current detection circuit configured to be controlled by the controller. The current detection circuit includes a first driver and a second driver; the first driver includes a first dummy light-emitting element corresponding to a first light-emitting element among the plurality of light-emitting elements configured to provide light of a first color; and the second driver includes a second dummy light-emitting element corresponding to a second light-emitting element among the plurality of light-emitting elements configured to provide light of a second color.

[0007] In an embodiment, the first driver may further include a first dummy transistor connected between the first terminal and the first dummy light-emitting element.

[0008] In an embodiment, the current detection device may further include a second terminal connected to the first gate electrode of the first dummy transistor.

[0009] In an embodiment, the current detection device may further include a third terminal connected to the first anode electrode of the first dummy light-emitting element.

[0010] In an embodiment, the current detection device may further include a fourth terminal connected to the first cathode electrode of the first dummy light-emitting element.

[0011] In an embodiment, the second driver may further include a second dummy transistor connected between the fifth terminal and the second dummy light-emitting element.

[0012] In one embodiment, the current detection device may further include a sixth terminal connected to the second gate electrode of the second dummy transistor.

[0013] In an embodiment, the current detection device may further include a seventh terminal connected to the second anode electrode of the second dummy light-emitting element.

[0014] In an embodiment, the second cathode electrode of the second dummy light-emitting element can be connected to the fourth terminal.

[0015] In an embodiment, the display device may further include a resistor connected between the first anode electrode of the first dummy light-emitting element and the second anode electrode of the second dummy light-emitting element.

[0016] In this embodiment, the first color of light can be red light, and the second color of light can be green light.

[0017] In one embodiment, the first driver and the second driver may be connected in parallel with each other.

[0018] In an embodiment, the first driver of the current detection circuit may include a plurality of first drivers; and the second driver of the current detection circuit may include a plurality of second drivers.

[0019] In an embodiment, the first anode electrode of the first dummy light-emitting element of each of the plurality of first drivers can be connected to each other, and the first cathode electrode of the first dummy light-emitting element of each of the plurality of first drivers can be connected to each other.

[0020] In an embodiment, each of the plurality of first drivers may further include a first dummy transistor. The first gate electrode of the first dummy transistor of each of the plurality of first drivers may be connected to each other, the first drain electrode of the first dummy transistor of each of the plurality of first drivers may be connected to each other, and the first source electrode of the first dummy transistor of each of the plurality of first drivers may be connected to each other.

[0021] In an embodiment, the second anode electrode of the second dummy light-emitting element of each of the plurality of second drivers can be connected to each other, and the second cathode electrode of the second dummy light-emitting element of each of the plurality of second drivers can be connected to each other.

[0022] In an embodiment, each of the plurality of second drivers may further include a second dummy transistor. The second gate electrodes of the second dummy transistors of each of the plurality of second drivers may be connected to each other, the second drain electrodes of the second dummy transistors of each of the plurality of second drivers may be connected to each other, and the second source electrodes of the second dummy transistors of each of the plurality of second drivers may be connected to each other.

[0023] In an embodiment, the first dummy light-emitting element of each of the plurality of first drivers can be configured to provide light of a first color.

[0024] In an embodiment, the second dummy light-emitting element of each of the plurality of second drivers can be configured to provide light of a second color.

[0025] In an embodiment, the display device may further include a light-blocking layer on the current detection device in a non-display area.

[0026] According to some embodiments of this disclosure, the display device can quantitatively measure the value of the lateral leakage current between pixels. Therefore, it is possible to accurately determine whether the display panel is good or bad based on the lateral leakage current.

[0027] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part in the following detailed description with reference to the accompanying drawings, and in part will be apparent from the detailed description, or may be learned by practicing one or more of the embodiments presented in this disclosure. Attached Figure Description

[0028] The above and other aspects and features of this disclosure will become more clearly understood from the following detailed description of exemplary, non-limiting embodiments, with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a schematic perspective view of an electronic device according to an embodiment;

[0030] Figure 2 This is a perspective view showing a display device included in an electronic device according to an embodiment;

[0031] Figure 3 It was viewed from the side. Figure 2 A cross-sectional view of the display device;

[0032] Figure 4 This is a plan view showing the display layer of a display device according to an embodiment;

[0033] Figure 5 This is a plan view showing the arrangement of the color filter and the emission area in the display area of ​​the display device according to an embodiment;

[0034] Figure 6 This is a cross-sectional view showing a portion of the display device according to an embodiment;

[0035] Figure 7 It is shown Figure 6 An enlarged view of the first launch area;

[0036] Figure 8 This is a block diagram of the current detection device of the display device according to an embodiment;

[0037] Figure 9 This is a detailed block diagram of the current detection unit according to an embodiment;

[0038] Figure 10 This is a detailed block diagram of the current detection unit according to an embodiment;

[0039] Figure 11 This is an array diagram of the current detection unit of the display device according to an embodiment;

[0040] Figure 12 yes Figure 11 A magnified view of part A;

[0041] Figure 13 It is shown Figure 12 The view of the first pattern layer;

[0042] Figure 14 It is shown Figure 12 Views of the first and second pattern layers;

[0043] Figure 15 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, and the first type of contact hole;

[0044] Figure 16 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, and the first type of contact hole;

[0045] Figure 17 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, the first type of contact hole, and the second type of contact hole;

[0046] Figure 18 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, the fourth pattern layer, the first type of contact hole, and the second type of contact hole; and

[0047] Figure 19 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, the fourth pattern layer, the first type of contact hole, the second type of contact hole, and the emission area. Detailed Implementation

[0048] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout refer to the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, unnecessary processes, elements, and techniques required for a complete understanding of the aspects and features of this disclosure may not be described. Unless otherwise indicated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, redundant descriptions may not be repeated.

[0049] When an embodiment can be implemented differently, the specific order of processing may differ from the order described. For example, two consecutively described processes may be executed simultaneously or substantially simultaneously, or they may be executed in the reverse order of the described process.

[0050] Furthermore, as those skilled in the art will understand, unless otherwise stated or implied, in view of the entirety of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or may be combined with each other, and may be technically linked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in any suitable combination with each other.

[0051] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatially relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “below” other elements or features would then be positioned “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein should be interpreted accordingly.

[0052] Furthermore, it should be anticipated that the shapes shown in the figures may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the figures, and should be interpreted in light of possible changes in shape, for example, due to manufacturing processes. Thus, the shapes shown in the figures may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0053] In the accompanying figures, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0054] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the terms “first element,” “first component,” “first area,” “first layer,” or “first part” described below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second part.”

[0055] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediary elements or layers may exist. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element can be directly electrically connected to the other layer, region, or element, and / or one or more intermediary layers, regions, or elements may be indirectly electrically connected between the layer, region, or element and the other layer, region, or element. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediary elements or layers may exist.

[0056] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that, when used in this specification, the terms “comprises / comprising,” “includes / including,” and “has / have / having” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When following a list of elements, expressions such as “at least one of…” modify the entire list of elements, rather than individual elements of the list. For example, the expressions “at least one of a, b and c” and “at least one selected from the group consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0057] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to describe the inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. Additionally, in describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the terms “use / using / used” can be considered synonymous with the terms “utilize / utilizing / utilized,” respectively.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant field and / or their meaning in this specification, and should not be interpreted in an idealized or overly formal sense.

[0059] Figure 1 This is a schematic perspective view of electronic device 1 according to an embodiment.

[0060] Reference Figure 1Electronic device 1 displays moving or still images. Electronic device 1 can refer to any suitable electronic device that provides a display screen. Some examples of electronic device 1 providing a display screen may include televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and portable video cameras, etc.

[0061] Electronic device 1 may include a display device for providing a display screen (e.g., see...). Figure 2 The display device 10 in the text refers to an organic light-emitting diode (OLED) display device, an organic light-emitting diode (OLED) display device, a quantum dot (QD) light-emitting diode (OLED) display device, a plasma display device, and a field emission display device. In the following description, for ease of illustration, an organic light-emitting diode (OLED) display device may be described in more detail as a representative example of a display device; however, this disclosure is not limited thereto, and other suitable display devices may be applied as needed or desired.

[0062] The shape of electronic device 1 can be modified in various ways as needed or desired. For example, electronic device 1 can have any suitable shape such as a rectangle extending in the horizontal direction, a rectangle extending in the vertical direction, a square shape, a quadrilateral shape with rounded corners (e.g., vertices), other suitable polygonal shapes, circular shapes, or elliptical shapes. The shape of the display area DA of electronic device 1 can also be similar to the overall shape of electronic device 1. Figure 1 An electronic device 1 having a rectangular shape extending in the second direction DR2 is shown.

[0063] Electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is the area where an image can be displayed, and the non-display area NDA is the area where no image is displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a passive area. The display area DA may occupy or substantially occupy the center of electronic device 1.

[0064] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may be areas where components are set for adding various suitable functions to the electronic device 1. Thus, the second display area DA2 and the third display area DA3 may correspond to component areas.

[0065] Figure 2 This is a perspective view showing the display device 10 included in the electronic device 1 according to an embodiment.

[0066] Reference Figure 2 According to the embodiment, electronic device 1 (for example, see...) Figure 1 The electronic device 1 may include a display device 10. The display device 10 can provide an image displayed by the electronic device 1 (e.g., displaying an image). The display device 10 may have a planar shape or a substantially planar shape similar to the shape of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle, having a short side extending in a first direction DR1 and a long side extending in a second direction DR2. The edges where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect each other may be rounded to have curvature, but this disclosure is not limited thereto, and the edges may be formed at right angles. The planar shape of the display device 10 is not limited to a quadrilateral shape and may be formed in any suitable shape similar to another polygonal shape, a circular shape, or an elliptical shape, etc.

[0067] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0068] Display panel 100 may include a main area MA and a sub-area SBA.

[0069] The main area MA may include a display area DA containing pixels for displaying images and a non-display area NDA disposed around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from multiple emission areas or multiple aperture areas. For example, the display panel 100 may include pixel circuitry containing switching elements, a pixel defining layer defining the emission area or aperture area, and self-emissive elements.

[0070] For example, a self-emissive element may include at least one of an organic light-emitting diode (LED) containing an organic light-emitting layer, a quantum dot LED containing a quantum dot light-emitting layer, an inorganic LED containing an inorganic semiconductor, and a micro LED, but this disclosure is not limited thereto.

[0071] The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies gate signals to the gate lines and a fan-out line that connects the display driver 200 to the display area DA.

[0072] A sub-region SBA can be a region extending from one side of a main region MA. The sub-region SBA can include a flexible material that can be bent, folded, or rolled. For example, when the sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (e.g., third direction DR3). The sub-region SBA can include a display driver 200 and pad portions connected to the circuit board 300. In another embodiment, the sub-region SBA can be omitted as needed or desired, and the display driver 200 and pad portions can be located in a non-display area NDA.

[0073] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to data lines. The display driver 200 can supply power voltages to power lines and can supply gate control signals to the gate driver. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be disposed in a sub-region SBA and can overlap with the main region MA in the thickness direction by bending the sub-region SBA. As another example, the display driver 200 can be mounted on a circuit board 300.

[0074] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0075] Touch driver 400 can be mounted on circuit board 300. Touch driver 400 can be connected to touch sensing unit (e.g., touch sensor, touch sensing layer, or touch sensing panel) of display panel 100. Touch driver 400 can supply touch drive signals to multiple touch electrodes of touch sensing unit and can sense the amount of change in capacitance between multiple touch electrodes. For example, the touch drive signal can be a pulse signal with a suitable frequency (e.g., a predetermined frequency). Touch driver 400 can determine whether an input has been made and can calculate input coordinates based on the amount of change in capacitance between multiple touch electrodes. Touch driver 400 can be formed as an integrated circuit (IC).

[0076] Figure 3 It was viewed from the side. Figure 2 A cross-sectional view of the display device 10.

[0077] Reference Figure 3 The display panel 100 may include a display layer DU, a touch sensing layer TSU, and a color filter layer CFL (see, for example, see...). Figure 6The display layer DU may include a substrate SUB, a thin film transistor layer (TFTL), a light-emitting element layer (EML), and a thin film encapsulation layer (TFEL).

[0078] The substrate SUB can be a matrix substrate or a matrix component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but this disclosure is not limited thereto. In another embodiment, the substrate SUB can include a glass material or a metal material.

[0079] A thin-film transistor layer (TFTL) can be disposed on a substrate SUB. The TFTL can include multiple thin-film transistors constituting pixel circuitry. The TFTL can also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad portion. Each of the thin-film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver can include multiple thin-film transistors.

[0080] Thin-film transistor (TFTL) layers can be disposed in the display area (DA), the non-display area (NDA), and the sub-area (SBA). The thin-film transistors, gate lines, data lines, and power lines for each pixel of the TFTL can be disposed in the display area (DA). The gate control lines and fan-out lines of the TFTL can be disposed in the non-display area (NDA). The leads of the TFTL can be disposed in the sub-area (SBA).

[0081] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The EML can include multiple light-emitting elements, each of which includes a first electrode, a second electrode, a light-emitting layer for emitting light, and a pixel defining layer for defining a pixel. The multiple light-emitting elements of the EML can be disposed in the display area (DA).

[0082] In this embodiment, the light-emitting layer may be an organic light-emitting layer comprising organic materials. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer (TFTL) and the second electrode receives a cathode voltage, holes and electrons can be transferred to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and can combine with each other to emit light in the organic light-emitting layer.

[0083] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, or a micro light-emitting diode.

[0084] The display device 10 according to the embodiment may include a plurality of color filters CF1, CF2 and CF3 disposed on the light-emitting elements of the light-emitting element layer EML (for example, see...). Figure 5 and Figure 6 Each of the color filters CF1, CF2, and CF3 can selectively transmit light of a desired wavelength (e.g., a specific wavelength or a predetermined wavelength) and can block or absorb light of different wavelengths. The color filters CF1, CF2, and CF3 can absorb a portion of the light from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filters can prevent or substantially prevent color distortion caused by the reflection of external light.

[0085] Because color filters CF1, CF2, and CF3 are disposed on the light-emitting element, the display device 10 does not need to use a separate substrate for the color filters. Therefore, the thickness of the display device 10 can be reduced (e.g., it can be relatively small).

[0086] The thin-film encapsulation layer TFEL can cover the top and side surfaces of the light-emitting element layer EML and protect the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light-emitting element layer EML.

[0087] The touch sensing layer (TSU) can be disposed on the encapsulation layer (TFEL). The touch sensing layer (TSU) may include multiple touch electrodes for capacitively sensing a user's touch and touch lines connecting the multiple touch electrodes to the touch driver 400. For example, the touch sensing layer (TSU) can sense a user's touch using mutual capacitance or self-capacitance methods.

[0088] In another embodiment, the touch sensing layer TSU can be disposed on a separate substrate disposed on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU can be a substrate component that encapsulates the display layer DU.

[0089] Multiple touch electrodes of the touch sensing layer (TSU) can be positioned in the touch sensor area overlapping the display area (DA). Touch lines of the touch sensing layer (TSU) can be positioned in the touch periphery area overlapping the non-display area (NDA).

[0090] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in a second display area DA2 or a third display area DA3. The optical device 500 may emit or receive light in the infrared, ultraviolet and / or visible light bands. For example, the optical device 500 may be an optical sensor such as a proximity sensor, an illuminance sensor and / or a camera sensor (e.g., an image sensor) that detects light incident on the display device 10.

[0091] Color filter layer CFL (for example, see Figure 6 The color filter layer (CFL) can be disposed on the thin-film encapsulation layer (TFEL). The CFL can include multiple color filters, each corresponding to a plurality of emission regions. Each of the color filters can selectively transmit light of a desired wavelength (e.g., a specific wavelength or a predetermined wavelength) and can block or absorb light of different wavelengths. The CFL can absorb a portion of the light from outside the display device 10 to reduce reflected light caused by external light. Therefore, the CFL can prevent or substantially prevent color distortion that may be caused by reflection of external light.

[0092] Because the color filter layer CFL can be directly disposed on the thin-film encapsulation layer TFEL, the display device 10 does not need to use a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be reduced (e.g., it can be relatively small).

[0093] Figure 4 This is a plan view showing the display layer DU of a display device according to an embodiment.

[0094] Reference Figure 4 The display layer DU can include the display area DA and the non-display area NDA.

[0095] The display area DA can be set in the display panel 100 (for example, see...). Figure 2 The center of the display area DA. Multiple pixels PX, multiple gate lines GL, multiple data lines DL, and multiple power lines VL can be set in the display area DA. Each of the multiple pixels PX can be defined as the smallest unit for emitting light.

[0096] Multiple gate lines GL can supply gate signals received from gate driver 210 to multiple pixels PX. The multiple gate lines GL can extend in a first direction DR1 and can be spaced apart from each other in a second direction DR2 that intersects or crosses the first direction DR1.

[0097] Multiple data lines DL can supply data voltage received from the display driver 200 to multiple pixels PX. The multiple data lines DL can extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1.

[0098] Multiple power lines VL can supply power voltage received from the display driver 200 to multiple pixels PX. The power voltage can be at least one of a drive voltage, an initialization voltage, a reference voltage, and a low potential voltage (e.g., a common voltage). The multiple power lines VL can extend in a second direction DR2 and can be spaced apart from each other in a first direction DR1.

[0099] The non-display area NDA may surround (e.g., around the display area DA) the display area DA. Gate driver 210, fan-out line FOL, and gate control line GCL may be located within the non-display area NDA. Gate driver 210 may generate multiple gate signals based on a gate control signal and may sequentially supply the multiple gate signals to multiple gate lines GL according to a suitable order (e.g., a set or predetermined order).

[0100] The fan-out line FOL can extend from the display driver 200 to the display area DA. The fan-out line FOL can supply the data voltage received from the display driver 200 to multiple data lines DL.

[0101] The gate control line GCL can extend from the display driver 200 to the gate driver 210. The gate control line GCL can supply the gate control signal received from the display driver 200 to the gate driver 210.

[0102] The sub-area SBA may include a display driver 200, a pad area PA, a first touch pad area TPA1, and a second touch pad area TPA2. The first touch pad area TPA1 may include a plurality of first touch pads TP1, and the second touch pad area TPA2 may include a plurality of first touch pads TP2.

[0103] The display driver 200 can output signals and voltages to the fan-out line FOL for driving the display panel 100. The display driver 200 can supply data voltage to the data line DL via the fan-out line FOL. The data voltage can be supplied to multiple pixels PX, and the brightness of the multiple pixels PX can be controlled. The display driver 200 can supply gate control signals to the gate driver 210 via the gate control line GCL.

[0104] Pad area PA, first touch pad area TPA1, and second touch pad area TPA2 can be located at the edge of sub-area SBA. Pad area PA, first touch pad area TPA1, and second touch pad area TPA2 can be electrically connected to circuit board 300 using suitable materials such as self-assembly anisotropic conductive paste (SACP) or anisotropic conductive film (see, for example, see...). Figure 2 ).

[0105] The pad area PA can include multiple display pad portions DP. These multiple display pad portions DP can be connected to the graphics system via circuit board 300. The multiple display pad portions DP can be connected to circuit board 300 to receive digital video data and can supply digital video data to display driver 200.

[0106] Figure 5This is a plan view showing the arrangement of color filters CF1, CF2 and CF3 and emission areas EA1, EA2 and EA3 in the display area DA of the display device 10 according to an embodiment.

[0107] Reference Figure 5 Also refer to Figure 1 The display device 10 may include multiple emission areas EA1, EA2 and EA3 disposed in the display area DA. Figure 5 The display area DA shown can correspond to the first display area DA1, and multiple emission areas EA1, EA2, and EA3 can be set in the first display area DA1. However, multiple emission areas EA1, EA2, and EA3 can also be set in the second display area DA2 and the third display area DA3 of the display area DA.

[0108] The emitting regions EA1, EA2, and EA3 may include a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3 for emitting light of different colors from each other. The first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 may emit red light, green light, and blue light, respectively. This is based on the light-emitting elements ED1, ED2, and ED3 disposed at the light-emitting element layer EML (e.g., in or on the light-emitting element layer EML), which will be described in more detail below (see, for example, see...). Figure 6 The color of the light emitted from each of the emission regions EA1, EA2, and EA3 can be different. In an embodiment, the first emission region EA1 can emit red light, the second emission region EA2 can emit green light, and the third emission region EA3 can emit blue light. However, this disclosure is not limited thereto.

[0109] Multiple emission zones EA1, EA2, and EA3 can be arranged in a diamond pattern (e.g., Arrangement, such as diamonds arrangement, (This is a registered trademark of Samsung Display Co., Ltd.) For example, the first emission area EA1 and the third emission area EA3 can be spaced apart from each other along the first direction DR1, and can be alternately arranged along the first direction DR1 and the second direction DR2. In the arrangement of emission areas EA1, EA2, and EA3, the first emission area EA1 and the third emission area EA3 can be alternately arranged along the first direction DR1 in the first row R1 and the third row R3. In the first column C1 and the third column C3, the first emission area EA1 and the third emission area EA3 can be alternately arranged along the second direction DR2.

[0110] The second transmission area EA2 can be spaced apart from another adjacent second transmission area EA2 along the first direction DR1 and the second direction DR2, and can be spaced apart from the adjacent first transmission area EA1 and the adjacent third transmission area EA3 along the fourth direction DR4 or the fifth direction DR5. Multiple second transmission areas EA2 can be repeatedly arranged along the first direction DR1 and the second direction DR2, and second transmission areas EA2 and first transmission areas EA1, or second transmission areas EA2 and third transmission areas EA3, can be alternately arranged along the fourth direction DR4 or the fifth direction DR5. In the arrangement of transmission areas EA1, EA2, and EA3, the second transmission area EA2 can be repeatedly arranged along the first direction DR1 in the second row R2 and the fourth row R4, and the second transmission area EA2 can be repeatedly arranged along the second direction DR2 in the second column C2 and the fourth column C4.

[0111] The first emission region EA1, the second emission region EA2, and the third emission region EA3 can each be formed by a dam structure BNS formed on the light-emitting element layer EML, which will be described in more detail below (for example, see...). Figure 6 Multiple openings OPE1, OPE2, and OPE3 in the pixel-defining layer define the region. For example, a first emission region EA1 may be defined by a first opening OPE1 in the pixel-defining layer, a second emission region EA2 may be defined by a second opening OPE2 in the pixel-defining layer, and a third emission region EA3 may be defined by a third opening OPE3 in the pixel-defining layer.

[0112] The areas of the emission regions EA1, EA2, and EA3 can vary according to the dimensions of the openings OPE1, OPE2, and OPE3 in the dam structure. The intensity of the light emitted from the corresponding emission regions EA1, EA2, and EA3 can vary according to the areas of the emission regions EA1, EA2, and EA3, and the areas of the emission regions EA1, EA2, and EA3 can be adjusted to control the color of the image displayed on the display device 10 or the electronic device 1. In embodiments, the areas or dimensions of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be the same as or substantially the same as each other. Figure 5 In the embodiments shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have the same or substantially the same area as each other, or the same or substantially the same diameter as each other.

[0113] However, this disclosure is not limited thereto. The areas of the emitting regions EA1, EA2, and EA3 can be adjusted differently as needed or desired, depending on the color of the image desired by the display device 10 and the electronic device 1. Furthermore, the areas of the emitting regions EA1, EA2, and EA3 may be related to the luminous efficiency and lifespan of the light-emitting element ED, and may have a trade-off with the reflection of external light. Taking these factors into consideration, the areas of the emitting regions EA1, EA2, and EA3 can be adjusted. For example, in the display device 10, the area of ​​the third emitting region EA3 may be larger than the areas of the first emitting region EA1 and the second emitting region EA2, and the area of ​​the first emitting region EA1 may be larger than the area of ​​the second emitting region EA2.

[0114] In having Figure 5 In the display device 10 shown with the arrangement of emission regions EA1, EA2, and EA3, a first emission region EA1, two second emission regions EA2, and a third emission region EA3 adjacent to each other can form a pixel group. A pixel group may include emission regions EA1, EA2, and EA3 that emit light of different colors to represent white grayscale levels. However, this disclosure is not limited to this, and the combination of emission regions EA1, EA2, and EA3 constituting a pixel group can be modified differently depending on the arrangement of emission regions EA1, EA2, and EA3, the color of the light emitted from emission regions EA1, EA2, and EA3, etc.

[0115] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on emission regions EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be configured to correspond respectively to emission regions EA1, EA2, and EA3. For example, color filters CF1, CF2, and CF3 may be disposed within emission regions EA1, EA2, and EA3, or within a light-blocking layer BM (e.g., see...). Figure 6 Multiple openings OPT1, OPT2, and OPT3 of the light-blocking layer are configured to correspond to openings OPE1, OPE2, and OPE3, respectively. The openings OPT1, OPT2, and OPT3 of the light-blocking layer can be formed to overlap with openings OPE1, OPE2, and OPE3, and can form a light emission region from which light emitted from emission regions EA1, EA2, and EA3 is emitted. Color filters CF1, CF2, and CF3 can each have an area larger than the areas of openings OPE1, OPE2, and OPE3, and color filters CF1, CF2, and CF3 can each completely cover the light emission region formed by the openings OPT1, OPT2, and OPT3 of the light-blocking layer BM.

[0116] Color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 configured to correspond to different emission regions EA1, EA2, and EA3, respectively. Color filters CF1, CF2, and CF3 may include colorants such as dyes or pigments that absorb light in bands other than a desired band (e.g., a specific or predetermined band), and may be configured to correspond to the color of light emitted from emission regions EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter configured to overlap with the first emission region EA1 and transmit only red first light. The second color filter CF2 may be a green color filter configured to overlap with the second emission region EA2 and transmit only green second light. The third color filter CF3 may be a blue color filter configured to overlap with the third emission region EA3 and transmit only blue third light.

[0117] Similar to the arrangement of emission regions EA1, EA2, and EA3, color filters CF1, CF2, and CF3 can be arranged in a diamond pattern (e.g., (Arrangement) settings. For example, the first color filter CF1 and the third color filter CF3 can be alternately arranged along the first direction DR1 and the second direction DR2. In the arrangement of color filters CF1, CF2, and CF3, the first color filter CF1 and the third color filter CF3 can be alternately arranged along the first direction DR1 in the first row R1 and the third row R3. In the first column C1 and the third column C3, the first color filter CF1 and the third color filter CF3 can be alternately arranged along the second direction DR2.

[0118] The second color filter CF2 and another adjacent second color filter CF2 can be arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2, the adjacent first color filter CF1, and the adjacent third color filter CF3 can be arranged along the fourth direction DR4 or the fifth direction DR5. Multiple second color filters CF2 can be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1, or the second color filter CF2 and the third color filter CF3, can be alternately arranged along the fourth direction DR4 or the fifth direction DR5. In the arrangement of color filters CF1, CF2, and CF3, the second color filter CF2 can be repeatedly arranged along the first direction DR1 in the second row R2 and the fourth row R4, and the second color filter CF2 can be repeatedly arranged along the second direction DR2 in the second column C2 and the fourth column C4.

[0119] Figure 6 This is a cross-sectional view showing a portion of the display device according to an embodiment. Figure 7 It is shown Figure 6 An enlarged view of the first launch area EA1. Figure 6It is the display device 10 (for example, see...). Figure 5 A partial cross-sectional view of the substrate SUB, the thin-film transistor layer (TFTL), the light-emitting element layer (EML), and the display layer (DU) (see, for example, see...). Figure 4 The cross-section of the thin film encapsulation layer TFEL, the touch sensing layer TSU, and the color filter layer CFL. Figure 7 The setting is shown Figure 6 The first light-emitting element ED1 in the first emission region EA1 and a part of the dike structure BNS adjacent to the first light-emitting element ED1.

[0120] Reference Figure 6 and Figure 7 as well as Figures 3 to 5 The display panel 100 of the display device 10 may include a display layer DU. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EML, and a thin film encapsulation layer TFEL. The display panel 100 may include a light blocking layer BM disposed on the thin film encapsulation layer TFEL, and color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the light blocking layer BM.

[0121] The substrate SUB can be a matrix substrate or a matrix component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but this disclosure is not limited thereto. As another example, the substrate SUB can include glass or metal materials.

[0122] The thin-film transistor layer (TFTL) may include a first buffer layer (BF1), a lower metal layer (BML), a second buffer layer (BF2), a thin-film transistor (TFT), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first connection electrode (CNE1), a first passivation layer (PAS1), a second connection electrode (CNE2), and a second passivation layer (PAS2).

[0123] A first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing or substantially preventing the penetration of oxygen and / or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers stacked alternately.

[0124] The lower metal layer BML can be disposed on the first buffer layer BF1. For example, the lower metal layer BML can be formed as a single layer or multiple layers of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and suitable alloys thereof (e.g., made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and suitable alloys thereof).

[0125] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing or substantially preventing the penetration of oxygen and / or moisture. For example, the second buffer layer BF2 may include multiple inorganic layers stacked alternately.

[0126] Thin-film transistors (TFTs) can be disposed on the second buffer layer BF2. The TFTs can form a pixel circuit corresponding to one of a plurality of pixels. For example, the TFT can be a switching transistor or a driving transistor of the pixel circuit. The TFT may include a channel region CH, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0127] The active layer ACT can be disposed on the second buffer layer BF2. The active layer ACT can overlap with the lower metal layer BML and the gate electrode GE in the thickness direction, and can be insulated from the gate electrode GE by the gate insulating layer GI. A portion of the active layer ACT can be made into a conductor to form the source electrode SE and the drain electrode DE.

[0128] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the active layer ACT, and the gate insulating layer GI is located between the gate electrode GE and the active layer ACT. The region of the active layer ACT that overlaps with the gate electrode GE can be the channel region CH.

[0129] A gate insulating layer GI can be disposed on the active layer ACT. For example, the gate insulating layer GI can cover the active layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the active layer ACT. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0130] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0131] The capacitor electrode CPE can be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE in the thickness direction. The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0132] The second interlayer insulating layer (ILD2) may cover the capacitor electrode (CPE) and the first interlayer insulating layer (ILD1). The second interlayer insulating layer (ILD2) may include a contact hole through which the first connection electrode (CNE1) passes. The contact hole of the second interlayer insulating layer (ILD2) may connect to the contact hole of the first interlayer insulating layer (ILD1) and the contact hole of the gate insulating layer (GI).

[0133] The first connection electrode CNE1 can be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the thin-film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 can be inserted into a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin-film transistor TFT.

[0134] The first passivation layer PAS1 can cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 can protect the thin-film transistor (TFT). The first passivation layer PAS1 can include a contact hole through which the second connection electrode CNE2 passes.

[0135] The second connection electrode CNE2 can be disposed on the first passivation layer PAS1. The second connection electrode CNE2 can electrically connect the first connection electrode CNE1 to the corresponding pixel electrode among the pixel electrodes AE1, AE2 and AE3 of the light-emitting element ED. The second connection electrode CNE2 can be inserted into the contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0136] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2 and AE3 of the light-emitting element ED pass.

[0137] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The EML may include light-emitting elements (ED) and multiple diaphragm structures (BNS). The light-emitting elements (ED) may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0138] The display device 10 may include a plurality of emission regions EA1, EA2, and EA3 disposed in the display area DA. The emission regions EA1, EA2, and EA3 may include a first emission region EA1, a second emission region EA2, and a third emission region EA3 for emitting light of different colors from each other. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may emit red light, green light, and blue light, respectively, and the color of the light emitted from each of the emission regions EA1, EA2, and EA3 may be different depending on the type of light-emitting element ED disposed at the light-emitting element layer EML (e.g., in the light-emitting element layer EML or on the light-emitting element layer EML). In an embodiment, the first emission region EA1 may emit red first light, the second emission region EA2 may emit green second light, and the third emission region EA3 may emit blue third light. However, this disclosure is not limited thereto.

[0139] The first emission region EA1, the second emission region EA2, and the third emission region EA3 can each be defined by a plurality of openings OPE1, OPE2, and OPE3 formed in the dam structure BNS of the light-emitting element layer EML. For example, the first emission region EA1 can be defined by the first opening OPE1 of the dam structure BNS, the second emission region EA2 can be defined by the second opening OPE2 of the dam structure BNS, and the third emission region EA3 can be defined by the third opening OPE3 of the dam structure BNS.

[0140] In embodiments, the areas or dimensions of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be the same or substantially the same as each other. For example, in the display device 10, the openings OPE1, OPE2, and OPE3 of the dam structure BNS may have the same or substantially the same diameter, and the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have the same or substantially the same area. However, this disclosure is not limited thereto. In the display device 10, the areas or dimensions of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other. For example, the area of ​​the second emission region EA2 may be larger than the areas of the first emission region EA1 and the third emission region EA3, and the area of ​​the third emission region EA3 may be larger than the area of ​​the first emission region EA1. The intensity of the light emitted from the corresponding emission regions EA1, EA2, and EA3 may vary depending on the area of ​​the emission regions EA1, EA2, and EA3, and the areas of the emission regions EA1, EA2, and EA3 may be adjusted to control the display in the display device 10 or the electronic device 1 (e.g., see...). Figure 1 The colors of the image in (). Although in Figure 6The embodiments shown depict emission regions EA1, EA2, and EA3 having the same or substantially the same area, but this disclosure is not limited thereto. The areas of emission regions EA1, EA2, and EA3 can be freely adjusted according to the color of the image desired by the display device 10 and the electronic device 1. Furthermore, the areas of emission regions EA1, EA2, and EA3 may be related to the luminous efficiency and lifetime of the light-emitting element ED, and may have a trade-off with the reflection of external light. Taking these factors into consideration, the areas of emission regions EA1, EA2, and EA3 can be adjusted.

[0141] In the display device 10, a first emission region EA1, a second emission region EA2, and a third emission region EA3 arranged adjacent to each other can form a pixel group. A pixel group may include emission regions EA1, EA2, and EA3 for emitting light of different colors to represent white grayscale levels. However, this disclosure is not limited to this, and the combination of emission regions EA1, EA2, and EA3 constituting a pixel group can be modified differently depending on the arrangement of emission regions EA1, EA2, and EA3, the color of the light emitted from emission regions EA1, EA2, and EA3, etc.

[0142] The display device 10 may include a plurality of light-emitting elements ED1, ED2, and ED3 disposed in different emission regions EA1, EA2, and EA3. The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1 disposed in the first emission region EA1, a second light-emitting element ED2 disposed in the second emission region EA2, and a third light-emitting element ED3 disposed in the third emission region EA3. The light-emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3. The light-emitting elements ED1, ED2, and ED3 disposed in the different emission regions EA1, EA2, and EA3 may emit light of different colors depending on the materials of the light-emitting layers EL1, EL2, and EL3. For example, the first light-emitting element ED1 disposed in the first emission region EA1 may emit red light of a first color, the second light-emitting element ED2 disposed in the second emission region EA2 may emit green light of a second color, and the third light-emitting element ED3 disposed in the third emission region EA3 may emit blue light of a third color. The first emission region EA1, the second emission region EA2, and the third emission region EA3 constituting a pixel may each include light-emitting elements ED1, ED2, and ED3 for emitting light of different colors to represent white grayscale levels.

[0143] Pixel electrodes AE1, AE2, and AE3 can be disposed on the second passivation layer PAS2. Pixel electrodes AE1, AE2, and AE3 can be configured to overlap with any one of the openings OPE1, OPE2, and OPE3 of the dam structure BNS. Pixel electrodes AE1, AE2, and AE3 can be electrically connected to the drain electrode DE of the thin-film transistor TFT via the first connection electrode CNE1 and the second connection electrode CNE2.

[0144] Pixel electrodes AE1, AE2, and AE3 can be disposed in multiple emission regions EA1, EA2, and EA3, respectively. Pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in a first emission region EA1, a second pixel electrode AE2 disposed in a second emission region EA2, and a third pixel electrode AE3 disposed in a third emission region EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be disposed spaced apart from each other on a second passivation layer PAS2. Pixel electrodes AE1, AE2, and AE3 can be disposed in different emission regions EA1, EA2, and EA3 to respectively constitute light-emitting elements ED1, ED2, and ED3 for emitting light of different colors from each other.

[0145] An inorganic insulating layer ISL can be disposed on the second passivation layer PAS2 and pixel electrodes AE1, AE2, and AE3. The inorganic insulating layer ISL can be disposed over the entire or substantially the entire second passivation layer PAS2, and can partially overlap with pixel electrodes AE1, AE2, and AE3 to expose a portion of the top surface of each of pixel electrodes AE1, AE2, and AE3. The inorganic insulating layer ISL can expose pixel electrodes AE1, AE2, and AE3 at the portions overlapping with openings OPE1, OPE2, and OPE3 of the dam structure BNS, and light-emitting layers EL1, EL2, and EL3 can be directly disposed on pixel electrodes AE1, AE2, and AE3, respectively. The inorganic insulating layer ISL can include inorganic insulating materials. For example, the inorganic insulating layer ISL can include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0146] According to an embodiment, an inorganic insulating layer ISL can be disposed on pixel electrodes AE1, AE2, and AE3, and can be spaced apart from the top surfaces of pixel electrodes AE1, AE2, and AE3. The inorganic insulating layer ISL can partially overlap with pixel electrodes AE1, AE2, and AE3 without directly contacting the top surfaces of pixel electrodes AE1, AE2, and AE3, and the light-emitting layers EL1, EL2, and EL3 of light-emitting elements ED1, ED2, and ED3 can be partially disposed between the inorganic insulating layer ISL and pixel electrodes AE1, AE2, and AE3. In the manufacturing process of the display device 10, a sacrificial layer can be disposed on pixel electrodes AE1, AE2, and AE3 before the inorganic insulating layer ISL is formed. The inorganic insulating layer ISL can be configured to cover a portion of the sacrificial layer, and can be spaced apart from the top surfaces of pixel electrodes AE1, AE2, and AE3 by removing the sacrificial layer. Then, in the deposition process of the light-emitting layers EL1, EL2, and EL3, the materials forming the light-emitting layers EL1, EL2, and EL3 can fill the space between the inorganic insulating layer ISL and the pixel electrodes AE1, AE2, and AE3, and the inorganic insulating layer ISL can be partially disposed on the light-emitting layers EL1, EL2, and EL3. However, the inorganic insulating layer ISL can be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3.

[0147] The display device 10 may include multiple dam structures BNS disposed on a thin-film transistor layer (TFTL) or a substrate (SUB) and comprising multiple openings OPE1, OPE2, and OPE3. The dam structures BNS may have a structure in which dam layers BN1 and BN2, comprising different materials, are sequentially stacked, and may include multiple openings OPE1, OPE2, and OPE3 forming emission regions EA1, EA2, and EA3, respectively. The light-emitting elements ED1, ED2, and ED3 of the display device 10 may be configured to overlap with the openings OPE1, OPE2, and OPE3 of the dam structures BNS.

[0148] The dike structure BNS may include a first dike layer BN1 disposed on the inorganic insulating layer ISL and a second dike layer BN2 disposed on the first dike layer BN1.

[0149] According to an embodiment, the first dam layer BN1 and the second dam layer BN2 may comprise different metallic materials, and the dam structure BNS may comprise a tip in which the second dam layer BN2 protrudes from the first dam layer BN1 toward the openings OPE1, OPE2, and OPE3. In the dam structure BNS, the lateral side of the first dam layer BN1 may have a shape that is recessed inward from the lateral side of the second dam layer BN2. In the dam structure BNS, the first dam layer BN1 may be thicker than the second dam layer BN2, and the second dam layer BN2 may be relatively thin, allowing the tip to be formed during the manufacturing process. Because the second dam layer BN2 has a shape that protrudes much more than the first dam layer BN1 toward the openings OPE1, OPE2, and OPE3, an undercut can be formed on the inner sidewalls of the openings OPE1, OPE2, and OPE3 of the dam structure BNS below the tip of the second dam layer BN2.

[0150] The sidewall shape of the dam structure BNS can be a structure formed due to the difference in etching rate during the etching process caused by the different materials of the first dam layer BN1 and the second dam layer BN2. According to an embodiment, the second dam layer BN2 may include a suitable material having an etching rate lower than that of the first dam layer BN1, and the first dam layer BN1 may be further etched in the process of forming the openings OPE1, OPE2, and OPE3 of the dam structure BNS to form an undercut below the tip tip of the second dam layer BN2. In an embodiment, the first dam layer BN1 may include a metallic material with high electrical conductivity, and the second dam layer BN2 may include a metallic material with low reflectivity. For example, the first dam layer BN1 may include aluminum (Al), and the second dam layer BN2 may include titanium (Ti). The dam structure BNS may have a suitable structure in which Al / Ti layers are stacked on an inorganic insulating layer ISL, and the tip tip may be formed in the Ti layer of the second dam layer BN2.

[0151] The dam structure BNS may include openings OPE1, OPE2, and OPE3 forming emission regions EA1, EA2, and EA3, respectively, and a light-blocking layer BM may be disposed on the dam structure BNS. The uppermost layer of the dam structure BNS may include a suitable material with low reflectivity to reduce the reflection of external light. Furthermore, in the dam structure BNS, the first dam layer BN1 may be electrically connected to the common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3. In the light-emitting elements ED1, ED2, and ED3 disposed in the different emission regions EA1, EA2, and EA3, the common electrodes CE1, CE2, and CE3 may not be directly connected to each other, but rather electrically connected to each other through the first dam layer BN1.

[0152] In the manufacturing process of the display device 10, a masking process can be used to form pixel-defining layers that form emitting regions EA1, EA2, and EA3 using organic materials, or to form light-emitting layers EL1, EL2, and EL3 that form light-emitting elements ED1, ED2, and ED3 in the corresponding emitting regions EA1, EA2, and EA3. To perform the masking process, the display device 10 can use a structure for mounting the mask, or it can use an unnecessarily large non-display area NDA to control variations according to the masking process. If such a masking process is minimized or not used, unnecessary components (e.g., structures for mounting the mask) can be omitted from the display device 10, and the area of ​​the non-display area NDA used to control variations can be minimized or reduced.

[0153] The display device 10 according to an embodiment includes a dam structure BNS for forming emission regions EA1, EA2, and EA3, and the dam structure BNS and emission regions EA1, EA2, and EA3 can be formed by deposition and etching processes instead of a mask process. Furthermore, the dam structure BNS includes a first dam layer BN1 and a second dam layer BN2 comprising different metallic materials, and the dam structure BNS has a structure including a tip on the inner sidewall of openings OPE1, OPE2, and OPE3, making it possible to form different layers separately in different emission regions EA1, EA2, and EA3 even by a deposition process. For example, even when the light-emitting layers EL1, EL2, and EL3 of light-emitting elements ED1, ED2, and ED3, and common electrodes CE1, CE2, and CE3 are formed by a deposition process without using a mask, the deposited material can be disconnected from openings OPE1, OPE2, and OPE3 by the tip of the second dam layer BN2 formed on the inner sidewall of openings OPE1, OPE2, and OPE3 without connection. By forming a material for forming specific layers on the entire surface of the display device 10 and then removing the layers formed in undesirable areas by etching, it is possible to form different layers individually in different emission regions EA1, EA2, and EA3. In the display device 10, different light-emitting elements ED1, ED2, and ED3 can be formed in different emission regions EA1, EA2, and EA3 by deposition and etching processes without using a mask process, and unnecessary components in the display device 10 can be omitted to minimize or reduce the area of ​​the non-display region NDA.

[0154] The first encapsulation layer TFE1 of the thin-film encapsulation layer TFEL can be disposed on the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3. The first encapsulation layer TFE1 may include a first inorganic layer TL1 disposed on the first light-emitting element ED1, a second inorganic layer TL2 disposed on the second light-emitting element ED2, and a third inorganic layer TL3 disposed on the third light-emitting element ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be formed on the entire or substantially the entire embankment structure BNS, and can be configured to cover (e.g., only cover) the light-emitting elements ED1, ED2, and ED3, the organic patterns ELP1, ELP2, and ELP3 described in more detail below, and the electrode patterns CEP1, CEP2, and CEP3 in the corresponding emission regions EA1, EA2, and EA3, without being disposed between the emission regions EA1, EA2, and EA3. The shapes of inorganic layers TL1, TL2 and TL3 can be formed by forming inorganic layers TL1, TL2 and TL3 to completely cover the dike structure BNS and then partially patterning inorganic layers TL1, TL2 and TL3.

[0155] The display device 10 may include a pattern representing the traces of a deposition process and the shape of a dam structure BNS. The pattern may be formed concurrently (e.g., simultaneously or substantially simultaneously) with the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3, and the common electrodes CE1, CE2, and CE3, and may remain on the dam structure BNS. The structures of the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the pattern will be described in more detail below.

[0156] Light-emitting layers EL1, EL2, and EL3 can be disposed on pixel electrodes AE1, AE2, and AE3, respectively. Light-emitting layers EL1, EL2, and EL3 can be organic light-emitting layers comprising organic materials (e.g., made of organic materials), and can be formed on pixel electrodes AE1, AE2, and AE3 respectively by a deposition process. In light-emitting layers EL1, EL2, and EL3, when a desired voltage (e.g., a predetermined voltage) is applied to the pixel electrodes AE1, AE2, and AE3 of light-emitting elements ED1, ED2, and ED3 by a thin-film transistor (TFT), and the common electrodes CE1, CE2, and CE3 of light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons can move to light-emitting layers EL1, EL2, and EL3 respectively through hole transport layers and electron transport layers, and holes and electrons can combine with each other in light-emitting layers EL1, EL2, and EL3 to emit light.

[0157] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 disposed in different emission regions EA1, EA2, and EA3. The first light-emitting layer EL1 may be disposed on a first pixel electrode AE1 in the first emission region EA1, the second light-emitting layer EL2 may be disposed on a second pixel electrode AE2 in the second emission region EA2, and the third light-emitting layer EL3 may be disposed on a third pixel electrode AE3 in the third emission region EA3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be light-emitting layers for a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3, respectively. The first light-emitting layer EL1 may be a light-emitting layer for emitting red light of a first color, the second light-emitting layer EL2 may be a light-emitting layer for emitting green light of a second color, and the third light-emitting layer EL3 may be a light-emitting layer for emitting blue light of a third color.

[0158] According to an embodiment, the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 can be partially disposed between the pixel electrodes AE1, AE2, and AE3 and the inorganic insulating layer ISL. The inorganic insulating layer ISL can be disposed on the pixel electrodes AE1, AE2, and AE3, but can be spaced apart from the top surfaces of the pixel electrodes AE1, AE2, and AE3. The deposition process of the light-emitting layers EL1, EL2, and EL3 can be performed such that the material of the light-emitting layers is deposited in an inclined direction rather than in a direction perpendicular to or substantially perpendicular to the top surface of the substrate SUB. Therefore, the light-emitting layers EL1, EL2, and EL3 can be disposed on the top surfaces of the pixel electrodes AE1, AE2, and AE3, respectively, and exposed through the openings OPE1, OPE2, and OPE3 of the dam structure BNS to fill the space between the pixel electrodes AE1, AE2, and AE3 and the inorganic insulating layer ISL.

[0159] In the manufacturing process of the display device 10, a sacrificial layer can be disposed between the inorganic insulating layer ISL and the pixel electrodes AE1, AE2, and AE3, and the light-emitting layers EL1, EL2, and EL3 can be disposed in the area where the sacrificial layer is partially removed. Therefore, the bottom surface of the inorganic insulating layer ISL can be spaced apart from the pixel electrodes AE1, AE2, and AE3. However, the sacrificial layer can be retained as a partial residual pattern RP in the area between the inorganic insulating layer ISL and the pixel electrodes AE1, AE2, and AE3. The area between the inorganic insulating layer ISL and the pixel electrodes AE1, AE2, and AE3 can be filled with the partial residual pattern RP and the light-emitting layers EL1, EL2, and EL3.

[0160] The display device 10 according to the embodiment may include a plurality of organic patterns ELP1, ELP2, and ELP3 disposed on the embankment structure BNS, comprising the same or substantially the same material as the light-emitting layers EL1, EL2, and EL3. Since the light-emitting layers EL1, EL2, and EL3 are formed by a process of depositing material onto the entire or substantially the entire surface of the display device 10, the material forming the light-emitting layers EL1, EL2, and EL3, in addition to the openings OPE1, OPE2, and OPE3 of the embankment structure BNS, can also be deposited on the embankment structure BNS.

[0161] For example, the display device 10 may include organic patterns ELP1, ELP2, and ELP3 disposed on the embankment structure BNS. The organic patterns ELP1, ELP2, and ELP3 may include a first organic pattern ELP1, a second organic pattern ELP2, and a third organic pattern ELP3 disposed on the second embankment layer BN2 of the embankment structure BNS.

[0162] The first organic pattern ELP1 may include the same material as the first light-emitting layer EL1 of the first light-emitting element ED1. The second organic pattern ELP2 may include the same material as the second light-emitting layer EL2 of the second light-emitting element ED2. The third organic pattern ELP3 may include the same material as the third light-emitting layer EL3 of the third light-emitting element ED3. Organic patterns ELP1, ELP2, and ELP3 may be formed in the same process as the process used to form light-emitting layers EL1, EL2, and EL3 (including materials identical to the materials of organic patterns ELP1, ELP2, and ELP3).

[0163] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 can be directly disposed on the second embankment layer BN2 of the embankment structure BNS. The organic patterns ELP1, ELP2, and ELP3 can be formed in the same process as the process for forming the light-emitting layers EL1, EL2, and EL3 (including the same materials as the organic patterns ELP1, ELP2, and ELP3), and can be disposed near (e.g., adjacent to) the emission regions EA1, EA2, and EA3 where the light-emitting layers EL1, EL2, and EL3 are respectively disposed. For example, the first organic pattern ELP1 can be disposed on the second embankment layer BN2, while surrounding the first opening OPE1 (e.g., around the periphery of the first opening OPE1) near (e.g., adjacent to) the first opening OPE1 or the first emission region EA1. The second organic pattern ELP2 may be disposed on the second embankment layer BN2 while being near (e.g., adjacent to) the second opening OPE2 or the second emission region EA2, surrounding (e.g., around the periphery of) the second opening OPE2. The third organic pattern ELP3 may be disposed on the second embankment layer BN2 while being near (e.g., adjacent to) the third opening OPE3 or the third emission region EA3, surrounding (e.g., around the periphery of) the third opening OPE3.

[0164] The organic patterns ELP1, ELP2, and ELP3 can be traces formed by the organic patterns ELP1, ELP2, and ELP3 being broken off from the light-emitting layers EL1, EL2, and EL3 due to the tip of the dam structure BNS. The light-emitting layers EL1, EL2, and EL3 can be formed in the openings OPE1, OPE2, and OPE3, respectively, and the organic patterns ELP1, ELP2, and ELP3, as well as the light-emitting layers EL1, EL2, and EL3, can be broken off by the tip formed on the sidewalls of the openings OPE1, OPE2, and OPE3. Because the light-emitting layers EL1, EL2, and EL3 are formed by a maskless deposition process, the material of the light-emitting layers EL1, EL2, and EL3 can be formed on the entire or substantially the entire dam structure BNS. Organic patterns ELP1, ELP2 and ELP3 can be formed by patterning organic patterns ELP1, ELP2 and ELP3 in the vicinity of emission regions EA1, EA2 and EA3 or openings OPE1, OPE2 and OPE3 (e.g., adjacent to emission regions EA1, EA2 and EA3 or openings OPE1, OPE2 and OPE3).

[0165] Common electrodes CE1, CE2, and CE3 can be disposed on the light-emitting layers EL1, EL2, and EL3, respectively. Common electrodes CE1, CE2, and CE3 may comprise transparent conductive materials, allowing light generated in the light-emitting layers EL1, EL2, and EL3 to be emitted. Common electrodes CE1, CE2, and CE3 can receive a common voltage or a low-potential voltage. When pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage, and common electrodes CE1, CE2, and CE3 receive a low-potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, enabling the light-emitting layers EL1, EL2, and EL3 to emit light.

[0166] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 disposed in different emission regions EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light-emitting layer EL1 in the first emission region EA1, the second common electrode CE2 may be disposed on the second light-emitting layer EL2 in the second emission region EA2, and the third common electrode CE3 may be disposed on the third light-emitting layer EL3 in the third emission region EA3.

[0167] According to an embodiment, the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 can be partially disposed on the side surface of the first dam layer BN1 of the dam structure BNS. Similar to the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3 can also be formed by a deposition process. The deposition process of the common electrodes CE1, CE2, and CE3 can be performed such that the electrode material is deposited in an inclined direction rather than perpendicular to or substantially perpendicular to the top surface of the substrate SUB. Therefore, the common electrodes CE1, CE2, and CE3 can be disposed on the side surface of the first dam layer BN1 below the tip TIP of the second dam layer BN2 of the dam structure BNS. The common electrodes CE1, CE2, and CE3 can be in direct contact with the side surface of the first dam layer BN1. The common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3 can be in direct contact with the first dam layer BN1 of the dam structure BNS, and the common electrodes CE1, CE2, and CE3 can be electrically connected to each other. Unlike pixel electrodes AE1, AE2, and AE3, common electrodes CE1, CE2, and CE3 can be implemented as electrodes that are electrically common to all pixels, rather than being divided for each of the multiple pixels.

[0168] According to an embodiment, the contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the first dam layer BN1 can be larger than the contact area between the light-emitting layers EL1, EL2, and EL3 and the side surface of the first dam layer BN1. The common electrodes CE1, CE2, and CE3, as well as the light-emitting layers EL1, EL2, and EL3, are formed such that the materials of the common electrodes CE1, CE2, and CE3, and the light-emitting layers EL1, EL2, and EL3 are deposited in an inclined direction rather than perpendicular to or substantially perpendicular to the top surface of the substrate SUB, and the area disposed on the side surface of the first dam layer BN1 can vary depending on the inclination angle. In an embodiment, the deposition process of the common electrodes CE1, CE2, and CE3 can be performed in a direction that is more inclined than the deposition process of the light-emitting layers EL1, EL2, and EL3. Compared to the area of ​​the light-emitting layers EL1, EL2, and EL3 on the sidewalls of openings OPE1, OPE2, and OPE3, the common electrodes CE1, CE2, and CE3 can be disposed with a large area on the sidewalls of openings OPE1, OPE2, and OPE3, or, compared to the positions of the light-emitting layers EL1, EL2, and EL3 on the sidewalls of openings OPE1, OPE2, and OPE3, they can be located at a high position on the sidewalls of openings OPE1, OPE2, and OPE3. Because the common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first dam layer BN1, the common electrodes CE1, CE2, and CE3 can contact the first dam layer BN1 with a large area (e.g., in direct contact with the first dam layer BN1).

[0169] The display device 10 according to an embodiment may include a plurality of electrode patterns CEP1, CEP2, and CEP3 comprising the same material as the common electrodes CE1, CE2, and CE3 and disposed on the embankment structure BNS. Because the common electrodes CE1, CE2, and CE3 are formed by a process of depositing material onto the entire or substantially the entire surface of the display device 10, the material forming the common electrodes CE1, CE2, and CE3, in addition to the openings OPE1, OPE2, and OPE3 of the embankment structure BNS, can also be deposited on the embankment structure BNS.

[0170] The display device 10 may include electrode patterns CEP1, CEP2, and CEP3 disposed above the embankment structure BNS. Electrode patterns CEP1, CEP2, and CEP3 may include a first electrode pattern CEP1, a second electrode pattern CEP2, and a third electrode pattern CEP3 disposed on the second embankment layer BN2 of the embankment structure BNS.

[0171] For example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 can be directly disposed on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship between the electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3 can be the same as or substantially the same as the arrangement relationship between the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3. The electrode patterns CEP1, CEP2, and CEP3 can be traces formed because the deposited material is disconnected from the common electrodes CE1, CE2, and CE3 due to the tip TIP of the dam structure BNS. In the display device 10, due to the tip TIP of the dam structure BNS, even in a deposition process without using a mask, the common electrodes CE1, CE2, and CE3 can be formed individually in different regions from each other.

[0172] A capping layer CPL may be disposed on the common electrodes CE1, CE2, and CE3. The capping layer CPL may include an inorganic insulating material to cover the patterns disposed on the embankment structure BNS and the light-emitting elements ED1, ED2, and ED3. The capping layer CPL can prevent or substantially prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air, and can prevent or substantially prevent the patterns disposed on the embankment structure BNS from being peeled off during the manufacturing process of the display device 10. In embodiments, the capping layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0173] The display device 10 may include a capping pattern CLP disposed on a dam structure BNS. The capping pattern CLP may be directly disposed on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 disposed on the second dam layer BN2 of the dam structure BNS. The arrangement relationship between the capping pattern CLP and the electrode patterns CEP1, CEP2, and CEP3 may be the same as or substantially the same as the arrangement relationship between the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 and the capping layer CPL. The capping pattern CLP may be a trace formed due to the material being deposited breaking off and not connecting with the capping layer CPL caused by the tip TIP of the dam structure BNS.

[0174] Multiple organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and capping pattern CLP can be disposed on the dam structure BNS, and can be configured to surround the periphery of the emission regions EA1, EA2, and EA3 or the openings OPE1, OPE2, and OPE3 respectively (e.g., surrounding the periphery of the emission regions EA1, EA2, and EA3 or the openings OPE1, OPE2, and OPE3). The stacked structure of the organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and capping pattern CLP disposed around the emission regions EA1, EA2, and EA3 can be partially etched during the manufacturing process of the display device 10, allowing the pattern shape to be changed. Therefore, a portion of the top surface of the second dam layer BN2 of the dam structure BNS may not be covered by the organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and capping pattern CLP.

[0175] The thin-film encapsulation layer TFEL can be disposed on the light-emitting elements ED1, ED2, and ED3 and the dam structure BNS, and can cover multiple light-emitting elements ED1, ED2, and ED3 and the dam structure BNS. The thin-film encapsulation layer TFEL may include at least one inorganic layer to prevent or substantially prevent oxygen and / or moisture from penetrating into the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust.

[0176] In an embodiment, the thin-film encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 stacked sequentially. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0177] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0178] The second encapsulation layer TFE2 may comprise a polymeric material. Examples of polymeric materials include acrylic resins, epoxy resins, polyimides, and polyethylene. For instance, the second encapsulation layer TFE2 may comprise an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer TFE2 may be formed by curing monomers or by applying a polymer.

[0179] The first encapsulation layer TFE1 can be disposed on the light-emitting elements ED1, ED2 and ED3, multiple patterns, and the embankment structure BNS. The first encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2 and a third inorganic layer TL3 respectively configured to correspond to different emission regions EA1, EA2 and EA3.

[0180] The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may comprise inorganic insulating materials to cover the light-emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can prevent or substantially prevent damage to the light-emitting elements ED1, ED2, and ED3 from external air, and can prevent or substantially prevent the pattern disposed on the embankment structure BNS from being peeled off during the manufacturing process of the display device 10. In an embodiment, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may comprise aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0181] The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be configured to cover organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and a capping pattern CLP. Because the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be formed using chemical vapor deposition (CVD), they can be formed to have a uniform or substantially uniform thickness along the stepped portions of the deposited layers. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be formed into a thin film even below the undercut of the tip TIP of the dike structure BNS.

[0182] The first inorganic layer TL1 can be disposed on the first light-emitting element ED1 and the first electrode pattern CEP1. The first inorganic layer TL1 can be configured to cover the first light-emitting element ED1 and the first opening OPE1 along the inner sidewall of the first light-emitting element ED1 and the first opening OPE1, and can also be configured to cover the first organic pattern ELP1, the first electrode pattern CEP1 and the capping pattern CLP. However, the first inorganic layer TL1 may not overlap with the second opening OPE2 and the third opening OPE3, and can be disposed on (e.g., only disposed on) the embankment structure BNS in the periphery of the first opening OPE1 and the first opening OPE1.

[0183] The second inorganic layer TL2 can be disposed on the second light-emitting element ED2 and the second electrode pattern CEP2. The second inorganic layer TL2 can be configured to cover the second light-emitting element ED2 and the second opening OPE2 along the inner sidewalls of the second light-emitting element ED2 and the second opening OPE2, and can also be configured to cover the second organic pattern ELP2, the second electrode pattern CEP2, and the capping pattern CLP. However, the second inorganic layer TL2 may not overlap with the first opening OPE1 and the third opening OPE3, and can be disposed on (e.g., only disposed on) the embankment structure BNS in the periphery of the second opening OPE2 and the second opening OPE2.

[0184] The third inorganic layer TL3 can be disposed on the third light-emitting element ED3 and the third electrode pattern CEP3. The third inorganic layer TL3 can be disposed along the inner sidewall of the third light-emitting element ED3 and the third opening OPE3 to cover the third light-emitting element ED3 and the third opening OPE3, and can also be disposed to cover the third organic pattern ELP3, the third electrode pattern CEP3, and the capping pattern CLP. However, the third inorganic layer TL3 may not overlap with the first opening OPE1 and the second opening OPE2, and can be disposed on (e.g., only disposed on) the embankment structure BNS in the periphery of the third opening OPE3 and the third opening OPE3.

[0185] The first inorganic layer TL1 can be formed after the formation of the first common electrode CE1. The second inorganic layer TL2 can be formed after the formation of the second common electrode CE2. The third inorganic layer TL3 can be formed after the formation of the third common electrode CE3. Therefore, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be configured to cover different electrode patterns CEP1, CEP2, and CEP3 and organic patterns ELP1, ELP2, and ELP3, respectively. In a plan view, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can have an area larger than the area of ​​the openings OPE1, OPE2, and OPE3 of the dam structure BNS, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be spaced apart from each other on the dam structure BNS. Therefore, a portion of the second dam layer BN2 of the dam structure BNS may not overlap with the inorganic layers TL1, TL2, and TL3, and a portion of the top surface of the second dam layer BN2 may be exposed without being covered by the inorganic layers TL1, TL2, and TL3. A portion of the second dam layer BN2 may be in direct contact with the second encapsulation layer TFE2 of the thin-film encapsulation layer TFEL, which will be described in more detail below.

[0186] The touch sensing layer (TSU) can be disposed on the encapsulation layer (TFEL). The touch sensing layer (TSU) may include a first touch insulating layer (SIL1), a second touch insulating layer (SIL2), a touch electrode (TEL), and a third touch insulating layer (SIL3).

[0187] The first touch insulating layer SIL1 may be disposed on the encapsulation layer TFEL. The first touch insulating layer SIL1 may have both insulating and optical functions. The first touch insulating layer SIL1 may include at least one inorganic layer. However, the first touch insulating layer SIL1 may be omitted as needed or desired.

[0188] The second touch insulating layer SIL2 may cover the first touch insulating layer SIL1. A further touch electrode layer may be disposed on the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may cover the touch electrode. The second touch insulating layer SIL2 may have insulating and optical functions. For example, the second touch insulating layer SIL2 may be an inorganic layer comprising (e.g., including) at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0189] A portion of the touch electrode TEL may be disposed on the second touch insulating layer SIL2. The touch electrode TEL may not overlap with the first emission region EA1, the second emission region EA2, and the third emission region EA3. The touch electrode TEL may be formed from a single layer comprising (e.g., containing) molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed as a stacked structure having aluminum and titanium (e.g., Ti / Al / Ti), a stacked structure of aluminum and ITO (e.g., ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of APC alloy and ITO (e.g., ITO / APC / ITO).

[0190] The third touch insulating layer SIL3 may cover the touch electrode TEL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have insulating and optical functions. The third touch insulating layer SIL3 may include any one or more of the materials mentioned above associated with the second touch insulating layer SIL2 (e.g., it may be made of any one or more of the materials mentioned above associated with the second touch insulating layer SIL2).

[0191] A light-blocking layer BM can be disposed on the touch-sensing layer TSU. The light-blocking layer BM may include a plurality of apertures OPT1, OPT2, and OPT3 configured to overlap with the emitting regions EA1, EA2, and EA3. For example, the first aperture OPT1 may be configured to overlap with the first emitting region EA1. The second aperture OPT2 may be configured to overlap with the second emitting region EA2, and the third aperture OPT3 may be configured to overlap with the third emitting region EA3. The area or size of the apertures OPT1, OPT2, and OPT3 may be larger than the area and size of the emitting regions EA1, EA2, and EA3 defined by the dam structure BNS, respectively. The apertures OPT1, OPT2, and OPT3 of the light-blocking layer BM are formed to be larger than the emitting regions EA1, EA2, and EA3, such that light emitted from the emitting regions EA1, EA2, and EA3 can be visually recognized by the user from the front surface and the side surface of the display device 10.

[0192] The light-blocking layer BM may include a light-absorbing material. For example, the light-blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but this disclosure is not limited thereto. The light-blocking layer BM can prevent or substantially prevent visible light penetration and color mixing between the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3, and therefore can cause an improvement in the color reproduction of the display device 10.

[0193] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on emission regions EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be configured to correspond respectively to emission regions EA1, EA2, and EA3. For example, color filters CF1, CF2, and CF3 may be disposed on a light-blocking layer BM comprising a plurality of openings OPT1, OPT2, and OPT3 configured to correspond respectively to emission regions EA1, EA2, and EA3. The openings in the light-blocking layer may be formed to overlap with the openings of emission regions EA1, EA2, and EA3 or the dam structure BNS, and may form a light emission region from which light emitted from emission regions EA1, EA2, and EA3 is emitted. Color filters CF1, CF2, and CF3 may have an area larger than the area of ​​the openings in the light-blocking layer BM, and color filters CF1, CF2, and CF3 may completely cover the light emission region formed by the openings.

[0194] Color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 configured to correspond to different emission regions EA1, EA2, and EA3, respectively. Color filters CF1, CF2, and CF3 may include colorants such as dyes or pigments that absorb light in bands other than specific wavelengths, and may be configured to correspond to the color of light emitted from emission regions EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter configured to overlap with the first emission region EA1 and transmit only red first light. The second color filter CF2 may be a green color filter configured to overlap with the second emission region EA2 and transmit only green second light. The third color filter CF3 may be a blue color filter configured to overlap with the third emission region EA3 and transmit only blue third light.

[0195] Multiple color filters CF1, CF2, and CF3 can be spaced apart from other adjacent color filters CF1, CF2, and CF3 on the light-blocking layer BM. Color filters CF1, CF2, and CF3 can each have an area larger than the area of ​​the openings OPT1, OPT2, and OPT3 of the light-blocking layer BM, while covering these openings OPT1, OPT2, and OPT3, and color filters CF1, CF2, and CF3 can have a small area sufficient to be spaced apart from other color filters CF1, CF2, and CF3 on the light-blocking layer BM. However, this disclosure is not limited thereto. Multiple color filters CF1, CF2, and CF3 can be configured to partially overlap with other adjacent color filters CF1, CF2, and CF3. Different color filters CF1, CF2, and CF3 are regions that do not overlap with the emission regions EA1, EA2, and EA3, and can overlap with each other on the light-blocking layer BM. In the display device 10, color filters CF1, CF2, and CF3 are configured to overlap with each other, such that the intensity of reflected light from external light can be reduced. Furthermore, the color of the reflected light from external light can be controlled by adjusting the settings, shape, and area of ​​color filters CF1, CF2, and CF3 in the plan view.

[0196] The color filters CF1, CF2, and CF3 of the color filter layer CFL can be disposed on the light blocking layer BM. Different color filters CF1, CF2, and CF3 can be configured to correspond to different emission regions EA1, EA2, and EA3, or to openings OPE1, OPE2, and OPE3, and to openings OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively. For example, the first color filter CF1 can be configured to correspond to the first emission region EA1, the second color filter CF2 can be configured to correspond to the second emission region EA2, and the third color filter CF3 can be configured to correspond to the third emission region EA3. The first color filter CF1 can be disposed in the first opening OPT1 of the light blocking layer BM, the second color filter CF2 can be disposed in the second opening OPT2 of the light blocking layer BM, and the third color filter CF3 can be disposed in the third opening OPT3 of the light blocking layer BM. Each of the color filters CF1, CF2 and CF3 can be configured to have an area larger than the area of ​​the openings OPT1, OPT2 and OPT3 of the light blocking layer BM in the plan view, and some can be set directly on the light blocking layer BM.

[0197] The outer coating OC can be applied to color filters CF1, CF2, and CF3 to planarize or substantially planarize the tops of color filters CF1, CF2, and CF3. The outer coating OC can be a colorless light-transmitting layer that does not have color in the visible light band. For example, the outer coating OC can include a colorless light-transmitting organic material such as acrylic resin.

[0198] Figure 8 This is a block diagram of the current detection device 555 of the display device according to an embodiment.

[0199] Reference Figure 8 According to an embodiment, the current detection device 555 may include a control unit (e.g., a controller) CON and a current detection unit (e.g., a current detector or a current detection circuit) CDT.

[0200] The current detection device 555 can be disposed in the non-display area NDA of the display device 10 (for example, see...). Figure 3 For example, the control unit CON and the current sensing unit CDT can be located on the substrate SUB (see, for example, see...). Figure 3 On the non-display area NDA.

[0201] Figure 9 This is a detailed block diagram of the current detection unit (CDT) according to an embodiment. For example, Figure 9 The current detection unit CDT can be as described above. Figure 8 An example of a current sensing unit (CDT) described.

[0202] like Figure 9As shown, the current detection unit CDT may include a first driver DU1 and a second driver DU2.

[0203] The first driver DU1 may include a first dummy transistor DT1 and a first dummy light-emitting element DED1.

[0204] The first dummy transistor DT1 can be connected between the first terminal T1 and the first anode electrode of the first dummy light-emitting element DED1. For example, the first dummy transistor DT1 can be connected between the first terminal T1 and the first node N1. According to an embodiment, the first dummy transistor DT1 may include a first gate electrode connected to the second terminal T2, a first drain electrode connected to the first terminal T1, and a first source electrode connected to the first node N1. For example, the first dummy transistor DT1 can be connected to the aforementioned display area DA (for example, see...). Figure 3 Thin-film transistor TFTs (e.g., see...) Figure 6 The same applies. According to an embodiment, the first dummy transistor DT1 and the thin-film transistor TFT can be formed concurrently with each other (e.g., simultaneously or substantially simultaneously) using the same or substantially the same process.

[0205] The first dummy light-emitting element DED1 can be connected between the first source electrode of the first dummy transistor DT1 and the fourth terminal T4. For example, the first dummy light-emitting element DED1 can be connected between the first node N1 and the third node N3. According to an embodiment, the first dummy light-emitting element DED1 may include a first anode electrode connected to the first node N1 and a first cathode electrode connected to the fourth terminal T4 via the third node N3. The first dummy light-emitting element DED1 can be related to the light-emitting elements ED1, ED2, and ED3 of the aforementioned display area DA (see, for example, see...). Figure 6The first dummy light-emitting element (DED1) can be identical to any of the red light-emitting elements disposed in the display area DA, and can provide red light. In other words, the first dummy light-emitting element (DED1) can be a red light-emitting element that provides red light. The first dummy light-emitting element (DED1) and the red light-emitting element of the display area can be formed concurrently with each other (e.g., simultaneously or substantially simultaneously) using the same or substantially the same process. According to an embodiment, the first dummy light-emitting element (DED1) may include a first light-emitting layer located between the first anode electrode and the first cathode electrode, and the first light-emitting layer of the first dummy light-emitting element (DED1) may be the same as the first light-emitting layer of the display area DA. For example, the first light-emitting layer of the first dummy light-emitting element (DED1) may include a hole transport layer, an organic light-emitting layer, and an electron transport layer, and the organic light-emitting layer of the first dummy light-emitting element (DED1) can provide red light. The first anode electrode of the first dummy light-emitting element (DED1) may correspond to the pixel electrode, and the first cathode electrode of the first dummy light-emitting element (DED1) may correspond to the common electrode.

[0206] The first node N1 can be connected to the third terminal T3.

[0207] The second driver DU2 may include a second dummy transistor DT2 and a second dummy light-emitting element DED2.

[0208] The second dummy transistor DT2 can be connected between the fifth terminal T5 and the second anode electrode of the second dummy light-emitting element DED2. For example, the second dummy transistor DT2 can be connected between the fifth terminal T5 and the second node N2. According to an embodiment, the second dummy transistor DT2 may include a second gate electrode connected to the sixth terminal T6, a second drain electrode connected to the fifth terminal T5, and a second source electrode connected to the second node N2. For example, the second dummy transistor DT2 may be the same as the thin-film transistor TFT of the aforementioned display area DA. According to an embodiment, the first dummy transistor DT1, the second dummy transistor DT2, and the thin-film transistor TFT can be formed concurrently with each other (e.g., simultaneously or substantially simultaneously) using the same or substantially the same process.

[0209] The second dummy light-emitting element DED2 can be connected between the second source electrode of the second dummy transistor DT2 and the fourth terminal T4. For example, the second dummy light-emitting element DED2 can be connected between the second node N2 and the third node N3. According to an embodiment, the second dummy light-emitting element DED2 may include a second anode electrode connected to the second node N2 and a second cathode electrode connected to the fourth terminal T4 via the third node N3. The second dummy light-emitting element DED2 can be the same as any of the light-emitting elements ED1, ED2, and ED3 of the display area DA described above. However, the second dummy light-emitting element DED2 can be different from the first dummy light-emitting element DED1 described above. In other words, the second dummy light-emitting element DED2 and the first dummy light-emitting element DED1 can provide light of different colors from each other. For example, the second dummy light-emitting element DED2 can be the same as the green light-emitting element disposed in the display area DA and can provide green light. In other words, the second dummy light-emitting element DED2 can be a green light-emitting element that provides green light. The second dummy light-emitting element DED2 and the green light-emitting element of the display area DA can be formed concurrently with each other (e.g., simultaneously or substantially simultaneously) using the same or substantially the same process. According to an embodiment, the second dummy light-emitting element DED2 may include a second light-emitting layer between the second anode electrode and the second cathode electrode, and the second light-emitting layer of the second dummy light-emitting element DED2 may be the same as the second light-emitting layer of the display area DA. For example, the second light-emitting layer of the second dummy light-emitting element DED2 may include a hole transport layer, an organic light-emitting layer, and an electron transport layer, and the organic light-emitting layer of the second dummy light-emitting element DED2 can provide green light. The second anode electrode of the second dummy light-emitting element DED2 may correspond to the pixel electrode, and the second cathode electrode of the second dummy light-emitting element DED2 may correspond to the common electrode.

[0210] The second node N2 can be connected to the seventh terminal T7.

[0211] The first cathode electrode of the first dummy light-emitting element DED1 and the second cathode electrode of the second dummy light-emitting element DED2 can be connected to the third node N3, and the third node N3 can be connected to the fourth terminal T4.

[0212] According to an embodiment, the first emitting layer of the first dummy light-emitting element DED1 can provide light other than the aforementioned red light. For example, the first emitting layer of the first dummy light-emitting element DED1 can be an emitting layer that provides green or blue light. Furthermore, the second emitting layer of the second dummy light-emitting element DED2 can provide light other than the aforementioned green light. For example, the second emitting layer of the second dummy light-emitting element DED2 can be an emitting layer that provides red or blue light. However, as described above, assuming that the first emitting layer of the first dummy light-emitting element DED1 and the second emitting layer of the second dummy light-emitting element DED2 provide light of different colors, then the first dummy light-emitting element DED1 and the second dummy light-emitting element DED2 can provide light of various colors.

[0213] Resistor Rd can be connected between the first anode electrode of the first dummy light-emitting element DED1 and the second anode electrode of the second dummy light-emitting element DED2. Resistor Rd can be represented by the aforementioned dam structure BNS (for example, see...). Figure 6 The resistance value of the disconnected light-emitting layer. For example, the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2 adjacent to the first light-emitting layer of the first dummy light-emitting element DED1 can be separated from each other by the dike structure BNS in the dike structure area (e.g., the area where the dike structure BNS is set), and the aforementioned resistor Rd can refer to the resistance value of the first light-emitting layer and the second light-emitting layer separated by the dike structure BNS in the dike structure area. In other words, the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2 adjacent to the first light-emitting layer of the first dummy light-emitting element DED1 can be partially connected to each other in the part other than the aforementioned dike structure area, and the aforementioned resistor Rd can refer to the resistance of the structure including the connection portion and the disconnection portion of the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2.

[0214] The first driver DU1 and the second driver DU2 can be connected to each other via the aforementioned resistor Rd. For example, the first driver DU1 and the second driver DU2 can be connected in parallel via the aforementioned resistor Rd.

[0215] Figure 10 This is a detailed block diagram of the current detection unit (CDT) according to an embodiment. For example, Figure 10 The current detection unit CDT can be as described above. Figure 8 An embodiment of the described current sensing unit (CDT) is described.

[0216] like Figure 10As shown, the current detection unit CDT may include a first-first driver DU1-1, a first-second driver DU1-2, a second-first driver DU2-1, and a second-second driver DU2-2. In other words, the current detection unit CDT may include multiple first drivers DU1 and multiple second drivers DU2. The multiple first drivers DU1 (e.g., first-first driver DU1-1 and first-second driver DU1-2) may be commonly connected to a first terminal T1, a second terminal T2, a third terminal T3, and a fourth terminal T4. The multiple second drivers DU2 (e.g., second-first driver DU2-1 and second-second driver DU2-2) may be commonly connected to a fifth terminal T5, a sixth terminal T6, a seventh terminal T7, and a fourth terminal T4.

[0217] The first driver DU1-1 and the first driver DU1-2 can each be referenced above. Figure 9 The first driver DU1 described is the same.

[0218] The first dummy transistor DT1 of the first driver DU1-1 and the first dummy transistor DT1 of the first driver DU1-2 can be connected to the second terminal T2 through their respective first gate electrodes, connected to the first terminal T1 through their respective first drain electrodes, and connected to the first node N1 and the third terminal T3 through their respective first source electrodes.

[0219] The first dummy light-emitting element DED1 of the first driver DU1-1 and the first dummy light-emitting element DED1 of the first driver DU1-2 can be connected to the first node N1 and the third terminal T3 through their respective first anode electrodes, and can be connected to the fourth terminal T4 through their respective first cathode electrodes.

[0220] The second-first driver DU2-1 and the second-second driver DU2-2 can each be referenced above. Figure 9 The second driver DU2 described is the same.

[0221] The second dummy transistor DT2 of the second-first driver DU2-1 and the second dummy transistor DT2 of the second-second driver DU2-2 can be connected to the sixth terminal T6 through their respective second gate electrodes, to the fifth terminal T5 through their respective second drain electrodes, and to the second node N2 and the seventh terminal T7 through their respective second source electrodes.

[0222] The second dummy light-emitting element DED2 of the second-first driver DU2-1 and the second dummy light-emitting element DED2 of the second-second driver DU2-2 can be connected to the second node N2 and the seventh terminal T7 through their respective second anode electrodes, and can be connected to the fourth terminal T4 through their respective second cathode electrodes.

[0223] Multiple first dummy light-emitting elements (DED1) of multiple first drivers DU1 (e.g., first-first driver DU1-1 and first-second driver DU1-2) can all provide light of the same color as each other. For example, the first dummy light-emitting element (DED1) of the first-first driver DU1-1 and the first dummy light-emitting element (DED1) of the first-second driver DU1-2 can each provide red light.

[0224] Multiple second dummy light-emitting elements (DED2) of multiple second drivers DU2 (e.g., second-first driver DU2-1 and second-second driver DU2-2) can all provide light of the same color. However, as mentioned above, the second dummy light-emitting elements (DED2) and the first dummy light-emitting elements (DED1) can provide light of different colors. For example, the second dummy light-emitting elements (DED2) of the second-first driver DU2-1 and the second dummy light-emitting elements (DED2) of the second-second driver DU2-2 can each provide green light.

[0225] A first resistor Rd1 can be connected between the first anode electrode of the first dummy light-emitting element DED1 provided in the first driver DU1-1 and the second anode electrode of the second dummy light-emitting element DED2 provided in the second driver DU2-1. The first resistor Rd1 can be represented by the above-described dam structure BNS (e.g., see...). Figure 6The resistor Rd1 refers to the resistance value of the disconnected light-emitting layer. For example, the first light-emitting layer of the first dummy light-emitting element DED1 provided in the first driver DU1-1 and the second light-emitting layer of the second dummy light-emitting element DED2 provided in the second driver DU2-1 adjacent to the first dummy light-emitting element DED1 in the first driver DU1-1 can be separated by the dike structure BNS in the dike structure area (e.g., the area where the dike structure BNS is set), and the aforementioned first resistor Rd1 can refer to the resistance value of the first light-emitting layer provided in the first driver DU1-1 and the resistance value of the second light-emitting layer provided in the second driver DU2-1, which are separated by the dike structure BNS in the dike structure area. In other words, the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2 adjacent to the first light-emitting layer of the first dummy light-emitting element DED1 can be partially connected in the part other than the aforementioned dike structure area, and the aforementioned first resistor Rd1 can refer to a resistor with a structure including the connection part and the disconnect part of the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2.

[0226] The second resistor Rd2 can be connected between the first anode electrode of the first dummy light-emitting element DED1 provided in the first-second driver DU1-2 and the second anode electrode of the second dummy light-emitting element DED2 provided in the second-second driver DU2-2. The second resistor Rd2 can be a resistor representing the resistance value of the light-emitting layer disconnected by the aforementioned dike structure BNS. For example, the first light-emitting layer of the first dummy light-emitting element DED1 provided in the first-second driver DU1-2 and the second light-emitting layer of the second dummy light-emitting element DED2 provided in the second-second driver DU2-2 adjacent to the first light-emitting layer of the first dummy light-emitting element DED1 can be separated by the dike structure BNS in the dike structure region (e.g., the region where the dike structure BNS is provided), and the aforementioned second resistor Rd2 can refer to the resistance value of the first light-emitting layer provided in the first-second driver DU1-2 and the resistance value of the second light-emitting layer provided in the second-second driver DU2-2, which are separated by the dike structure BNS in the dike structure region. In other words, the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2 adjacent to the first light-emitting layer of the first dummy light-emitting element DED1 can be partially connected in the part other than the aforementioned dike structure area, and the aforementioned second resistor Rd2 can refer to a resistor with a structure including the connection part and the disconnect part of the first light-emitting layer of the first dummy light-emitting element DED1 and the second light-emitting layer of the second dummy light-emitting element DED2.

[0227] The first driver DU1 (e.g., first-first driver DU1-1 and first-second driver DU1-2) and the second driver DU2 (e.g., second-first driver DU2-1 and second-second driver DU2-2) can be connected to each other via the aforementioned resistors (e.g., first resistor Rd1 and second resistor Rd2). For example, the first driver DU1 (e.g., first-first driver DU1-1 and first-second driver DU1-2) and the second driver DU2 (e.g., second-first driver DU2-1 and second-second driver DU2-2) can be connected in parallel with each other via the aforementioned resistors (e.g., first resistor Rd1 and second resistor Rd2).

[0228] According to an embodiment, the current detection unit CDT may include three or more first drivers DU1 and three or more second drivers DU2.

[0229] Figure 11 This is an array diagram of the current detection unit (CDT) of the display device according to an embodiment. For example, refer to... Figure 10 , Figure 11 It can be an array diagram of current sensing units (CDTs) including six first drivers (DU1) and six second drivers (DU2). Figure 12 yes Figure 11 A magnified view of part A. Figure 13 It is shown Figure 12 The view of the first pattern layer. Figure 14 It is shown Figure 12 The view of the first pattern layer and the second pattern layer. Figure 15 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, and the first type of contact hole. Figure 16 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, and the first type of contact hole. Figure 17 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, the first type of contact hole, and the second type of contact hole. Figure 18 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, the fourth pattern layer, the first type of contact hole, and the second type of contact hole. Figure 19 It is shown Figure 12 A view of the first pattern layer, the second pattern layer, the third pattern layer, the fourth pattern layer, the first type of contact hole, the second type of contact hole, and the emission area.

[0230] The first pattern layer can be set on the second buffer layer BF2 mentioned above. For example... Figures 11 to 13As shown, the first pattern layer may include at least one first active layer ACT1 and at least one second active layer ACT2. The first active layer ACT1 and the second active layer ACT2 may be alternately arranged. For example, the first active layer ACT1 and the second active layer ACT2 may be alternately arranged along a first direction DR1. For example, along the first direction DR1, odd-numbered active layers may be the first active layer ACT1, and even-numbered active layers may be the second active layer ACT2.

[0231] The first active layer ACT1 may include a first channel region CH1, a first drain electrode DE1, a first source electrode SE1, and a third transmission line LL3.

[0232] The second active layer ACT2 may include a second channel region CH2, a second drain electrode DE2, a second source electrode SE2, and a seventh transmission line LL7.

[0233] The first patterning layer may include the same material as the active layer ACT described above.

[0234] The first patterned layer may be formed at the same layer as the active layer ACT (e.g., in the middle or on top). The first patterned layer and the active layer ACT may be formed by the same or substantially the same process.

[0235] The second patterning layer can be disposed on the third-party DR3 on the first patterning layer. For example, the second patterning layer can be disposed on the gate insulating layer GI (see, for example, see...). Figure 6 (above) For example Figure 11 , Figure 12 and Figure 14 As shown, the second pattern layer may include a first gate electrode GE1, a second transmission line LL2, a sixth transmission line LL6, a first-to-first connection line CL1-1, and a fifth first connection line CL5-1.

[0236] The first gate electrode GE1 may overlap with the first active layer ACT1. The region of the first active layer ACT1 that overlaps with the first gate electrode GE1 may be the first channel region CH1 of the first dummy transistor DT1. For example, the first dummy transistor DT1 may include the first gate electrode GE1, the first source electrode SE1, the first drain electrode DE1, and the first channel region CH1. Multiple first gate electrodes GE1 disposed along the second direction DR2 may be connected to each other via the second transmission line LL2. For example, multiple first gate electrodes GE1 and the second transmission line LL2 may be integrally formed together.

[0237] The second gate electrode GE2 may overlap with the second active layer ACT2. The region of the second active layer ACT2 that overlaps with the second gate electrode GE2 may be the second channel region CH2 of the second dummy transistor DT2. For example, the second dummy transistor DT2 may include the second gate electrode GE2, the second source electrode SE2, the second drain electrode DE2, and the second channel region CH2. Multiple second gate electrodes GE2 disposed along the second direction DR2 may be interconnected via the sixth transmission line LL6. For example, multiple second gate electrodes GE2 and the sixth transmission line LL6 may be integrally formed together.

[0238] The first-to-first connecting line CL1-1 can be set adjacent to the second transmission line LL2.

[0239] The fifth first connection line CL5-1 can be set adjacent to the sixth transmission line LL6.

[0240] The second patterning layer may include (for example, may contain) the same material as the gate electrode GE described above.

[0241] The second patterned layer can be formed in the same layer as the gate electrode GE (e.g., in the middle or on top). The second patterned layer and the gate electrode GE can be formed using the same or substantially the same process.

[0242] like Figure 6 , Figure 11 , Figure 12 and Figure 15 As shown, the first type of contact hole may include a first contact hole CT1, a second contact hole CT2, a fourth contact hole CT4, a fifth contact hole CT5, a seventh contact hole CT7, an eighth contact hole CT8, a ninth contact hole CT9, a tenth contact hole CT10, an eleventh contact hole CT11, a twelfth contact hole CT12, a thirteenth contact hole CT13, and a fourteenth contact hole CT14.

[0243] The first contact hole CT1 can penetrate the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The first drain electrode DE1 can be exposed through the first contact hole CT1.

[0244] The second contact hole CT2 can penetrate the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The first source electrode SE1 can be exposed through the second contact hole CT2.

[0245] The fourth contact hole CT4 can penetrate the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The second drain electrode DE2 can be exposed through the fourth contact hole CT4.

[0246] The fifth contact hole CT5 can penetrate the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The second source electrode SE2 can be exposed through the fifth contact hole CT5.

[0247] The seventh contact hole CT7 can penetrate the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1. The first-to-first connecting line CL1-1 can be exposed through the seventh contact hole CT7.

[0248] The eighth contact hole CT8 can penetrate the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1. The fifth first connecting wire CL5-1 can be exposed through the eighth contact hole CT8.

[0249] The ninth contact hole CT9 can penetrate the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The third transmission line LL3 can be exposed through the ninth contact hole CT9.

[0250] The tenth contact hole CT10 can penetrate the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI. The seventh transmission line LL7 can be exposed through the tenth contact hole CT10.

[0251] The eleventh contact hole CT11 can penetrate the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1. The first-to-first connecting line CL1-1 can be exposed through the eleventh contact hole CT11.

[0252] The twelfth contact hole CT12 can penetrate the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1. The fifth first connecting line CL5-1 can be exposed through the twelfth contact hole CT12.

[0253] The thirteenth contact hole CT13 can penetrate the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1. The sixth transmission line LL6 can be exposed through the thirteenth contact hole CT13.

[0254] The fourteenth contact hole CT14 can penetrate the second interlayer insulation layer ILD2 and the first interlayer insulation layer ILD1. The second transmission line LL2 can be exposed through the fourteenth contact hole CT14.

[0255] The third patterning layer can be disposed on the second patterning layer on the third-direction DR3. For example, the third patterning layer can be disposed on the aforementioned second interlayer insulating layer ILD2. Figure 11 , Figure 12 and Figure 16As shown, the third pattern layer may include a first transmission line LL1, a fifth transmission line LL5, a first connecting electrode CNE1', a second connecting electrode CNE2', a third connecting line CL3, a seventh connecting line CL7, a first-second connecting line CL1-2, a fifth-second connecting line CL5-2, a sixth connecting line CL6, a fourth transmission line LL4, a second connecting line CL2, a first terminal T1, a second terminal T2, a third terminal T3, a fourth terminal T4, a fifth terminal T5, a sixth terminal T6, and a seventh terminal T7.

[0256] The first transmission line LL1 can be connected to the first drain electrode DE1 through the first contact hole CT1. Furthermore, the first transmission line LL1 can be connected to the first-first connection line CL1-1 through the seventh contact hole CT7.

[0257] The fifth transmission line LL5 can be connected to the second drain electrode DE2 through the fourth contact hole CT4. Furthermore, the fifth transmission line LL5 can be connected to the fifth first connection line CL5-1 through the eighth contact hole CT8.

[0258] The first connecting electrode CNE1' can be connected to the first source electrode SE1 through the second contact hole CT2.

[0259] The second connecting electrode CNE2' can be connected to the second source electrode SE2 through the fifth contact hole CT5.

[0260] The third connecting line CL3 can be connected to the third transmission line LL3 through the ninth contact hole CT9. The third connecting line CL3 can be connected to the third terminal T3. The third connecting line CL3 and the third terminal T3 can be integrally formed with each other. For example, the third connecting line CL3 can include the third terminal T3 at one end of the third connecting line CL3.

[0261] The seventh connecting line CL7 can be connected to the seventh transmission line LL7 through the tenth contact hole CT10. The seventh connecting line CL7 can be connected to the seventh terminal T7. The seventh connecting line CL7 and the seventh terminal T7 can be integrally formed with each other. For example, the seventh connecting line CL7 can include the seventh terminal T7 at one end of the seventh connecting line CL7.

[0262] The first-second connecting line CL1-2 can be connected to the first-first connecting line CL1-1 through the eleventh contact hole CT11. The first-second connecting line CL1-2 can be connected to the first terminal T1. The first-second connecting line CL1-2 and the first terminal T1 can be integrally formed with each other. For example, the first-second connecting line CL1-2 can include the first terminal T1 at one end of the first-second connecting line CL1-2.

[0263] The fifth second connecting line CL5-2 can be connected to the fifth first connecting line CL5-1 through the twelfth contact hole CT12. The fifth second connecting line CL5-2 can be connected to the fifth terminal T5. The fifth second connecting line CL5-2 and the fifth terminal T5 can be integrally formed with each other. For example, the fifth second connecting line CL5-2 can include the fifth terminal T5 at one end.

[0264] The sixth connecting line CL6 can be connected to the sixth transmission line LL6 through the thirteenth contact hole CT13. The sixth connecting line CL6 can be connected to the sixth terminal T6. The sixth connecting line CL6 and the sixth terminal T6 can be integrally formed with each other. For example, the sixth connecting line CL6 can include the sixth terminal T6 at one end of the sixth connecting line CL6.

[0265] In some embodiments, the fourth transmission line LL4 can be connected to the first cathode electrode of the first dummy light-emitting element DED1 and the second cathode electrode of the second dummy light-emitting element DED2. The first cathode electrode and the second cathode electrode can be integrally formed with each other. In other words, the first cathode electrode and the second cathode electrode integrally formed with each other can be a common electrode. The fourth transmission line LL4 can be connected to the fourth terminal T4. The fourth transmission line LL4 and the fourth terminal T4 can be integrally formed with each other. For example, the fourth transmission line LL4 may include the fourth terminal T4 at one end of the fourth transmission line LL4.

[0266] The second connecting line CL2 can be connected to the second transmission line LL2 through the fourteenth contact hole CT14. According to an embodiment, one end of the second transmission lines LL2 can be connected to each other. One end of the second transmission line LL2 can be connected to the second connecting line CL2. The second connecting line CL2 can be connected to the second terminal T2. The second connecting line CL2 and the second terminal T2 can be integrally formed with each other. For example, the second connecting line CL2 may include the second terminal T2 at one end.

[0267] The third patterning layer may include the same material as the first connecting electrode CNE1 described above.

[0268] The third patterned layer can be formed in the same layer as the first connecting electrode CNE1 (e.g., in the middle or on top). The third patterned layer and the first connecting electrode CNE1 can be formed by the same or substantially the same process.

[0269] like Figure 6 , Figure 11 , Figure 12 and Figure 17 As shown, the second type of contact hole may include a third contact hole CT3 and a sixth contact hole CT6.

[0270] The third contact hole CT3 can penetrate the second passivation layer PAS2 and the first passivation layer PAS1. The first connecting electrode CNE1' can be exposed through the third contact hole CT3.

[0271] The sixth contact hole CT6 can penetrate the second passivation layer PAS2 and the first passivation layer PAS1. The second connecting electrode CNE2' can be exposed through the sixth contact hole CT6.

[0272] The fourth patterning layer can be disposed on the third patterning layer on the third-direction DR3. For example, the fourth patterning layer can be disposed on the second passivation layer PAS2 mentioned above. Figure 11 , Figure 12 and Figure 18 As shown, the fourth patterned layer may include a first anode electrode AE1' and a second anode electrode AE2'.

[0273] The first anode electrode AE1' can be connected to the first connecting electrode CNE1' through the third contact hole CT3.

[0274] The second anode electrode AE2' can be connected to the second connecting electrode CNE2' through the sixth contact hole CT6.

[0275] The fourth pattern layer may include the same material as the first pixel electrode AE1 described above.

[0276] The fourth pattern layer can be formed in the same layer as the first pixel electrode AE1 (e.g., in the middle or on top). The fourth pattern layer and the first pixel electrode AE1 can be formed using the same or substantially the same process.

[0277] According to an embodiment, the first auxiliary connection electrode may be further disposed between the first connection electrode CNE1' and the first anode electrode AE1'. Similar to the second connection electrode CNE2 described above, the first auxiliary connection electrode may be disposed on the first passivation layer PAS1. One side of the first auxiliary connection electrode can be connected to the first connection electrode CNE1' through a contact hole penetrating the first passivation layer PAS1, and the other side of the first auxiliary connection electrode can be connected to the first anode electrode AE1' through a contact hole penetrating the second passivation layer PAS2.

[0278] According to an embodiment, a second auxiliary connection electrode may be further disposed between the second connection electrode CNE2' and the second anode electrode AE2'. Similar to the second connection electrode CNE2 described above, the second auxiliary connection electrode may be disposed on the first passivation layer PAS1. One side of the second auxiliary connection electrode can be connected to the second connection electrode CNE2' through a contact hole penetrating the first passivation layer PAS1, and the other side of the second auxiliary connection electrode can be connected to the second anode electrode AE2' through a contact hole penetrating the second passivation layer PAS2.

[0279] like Figure 6 , Figure 9 and Figure 19 As shown, the dam structure BNS' can be disposed on the first anode electrode AE1' and the second anode electrode AE2'. The dam structure BNS' can be disposed between dummy light-emitting elements that provide light of different colors to each other. For example, the dam structure BNS' can be disposed between the first anode electrode AE1' of the first dummy light-emitting element DED1 and the second anode electrode AE2' of the second dummy light-emitting element DED2. The dam structure BNS' can be formed into a strip shape extending along the first direction DR1. Multiple dam structures BNS' can be arranged along the second direction DR2.

[0280] The dike structure BNS' may include a first dike layer BN1 and a second dike layer BN2.

[0281] The dike structure BNS' may include (for example, may contain) the same material as the dike structure BNS described above.

[0282] The dike structure BNS' can be formed in the same layer as the aforementioned dike structure BNS (e.g., in the middle or on top).

[0283] According to an embodiment, the aforementioned thin-film encapsulation layer TFEL and light-blocking layer BM can be disposed on the dam structure BNS'. In this case, in the current detection device 555 (for example, see...), Figure 8 On the current sensing device 555, the light-blocking layer BM does not have openings OPT1, OPT2, and OPT3. For example, the light-blocking layer BM can be disposed on the current sensing device 555, such that the light-blocking layer BM covers... Figure 8 The diagram shows all the patterns of the current sensing device 555. In other words, the light blocking layer BM can be disposed on the dummy transistors and dummy light-emitting elements of the current sensing device 555, such that the light blocking layer BM covers all the dummy transistors and dummy light-emitting elements.

[0284] According to an embodiment, Figure 6 The second connection electrode CNE2 can be omitted as needed or desired. In such a case, the first pixel electrode AE1 can be directly connected to the first connection electrode CNE1 through contact holes penetrating the second passivation layer PAS2 and the first passivation layer PAS1. Similarly, the second pixel electrode AE2 and the third pixel electrode AE3 can also be directly connected to the first connection electrode CNE1 through contact holes penetrating the second passivation layer PAS2 and the first passivation layer PAS1, without the need for the second connection electrode CNE2.

[0285] The current detection device 555 according to the embodiment can indirectly measure the lateral leakage current between adjacent pixels of different colors. For example, as Figure 8The current sensing device 555 shown can measure the lateral leakage current flowing from the first driver DU1 to the second driver DU2 through the resistor Rd when the first dummy transistor DT1 is turned on and the second dummy transistor DT2 is turned off. In the example, the current sensing device 555 can operate the first dummy transistor DT1 to be turned on and the second dummy transistor DT2 to be turned off by applying an effective level first dummy gate voltage to the second terminal T2, a first drive voltage to the first terminal T1, a common voltage to the fourth terminal T4, and an ineffective level second dummy gate voltage to the sixth terminal T6 through the control unit CON. In this case, the drive current flowing through the turned-on first dummy transistor DT1 can be applied to the first dummy light-emitting element DED1. Therefore, the first dummy light-emitting element DED1 can emit light. If a lateral leakage current occurs between adjacent pixels that provide different colors from each other, a lateral leakage current can also occur between the adjacent first driver DU1 and second driver DU2. For example, when a lateral leakage current occurs between adjacent pixels, the driving current applied to the first dummy light-emitting element DED1 can be applied to the second dummy light-emitting element DED2 through resistor Rd. Therefore, the second dummy light-emitting element DED2 can emit light through the lateral leakage current. In this case, the control unit CON of the current detection device 555 can quantitatively measure the value of the lateral leakage current by receiving (e.g., by sensing) the voltage of the second node N2 through the seventh terminal T7. Even if each of the first dummy light-emitting element DED1 and the second dummy light-emitting element DED2 emits light, as described above, the current detection device 555 including the first dummy light-emitting element DED1 and the second dummy light-emitting element DED2 can be disposed in the non-display area NDA and can be shielded by the light blocking layer BM, so that the light from the first dummy light-emitting element DED1 and the second dummy light-emitting element DED2 is not emitted to the display panel 100 (e.g., see...). Figure 3 The outside of ).

[0286] In another embodiment, the current detection device 555 can operate by applying a first dummy gate voltage of effective level to the second terminal T2, a first drive voltage to the first terminal T1, a common voltage to the fourth terminal T4, and a second dummy gate voltage of effective level to the sixth terminal T6 via the control unit CON, thereby turning on each of the first dummy transistor DT1 and the second dummy transistor DT2. In this case, the drive current flowing through the turned-on first dummy transistor DT1 can be applied to the first dummy light-emitting element DED1. In this case, the control unit CON of the current detection device 555 can quantitatively measure the value of the lateral leakage current by receiving (e.g., by sensing) the voltage of the second node N2 via the turned-on second dummy transistor DT2 and the fifth terminal T5. For example, the lateral leakage current based on the voltage of the second node N2 can correspond to the lateral leakage current between adjacent pixels of different colors.

[0287] In another embodiment, the current detection device 555 can apply a second driving voltage to the second terminal T2 via the control unit CON. The aforementioned first driving voltage can be a driving voltage for driving the red light-emitting element, and the second driving voltage can be a driving voltage for driving the green light-emitting element. The first driving voltage and the second driving voltage can have different magnitudes.

[0288] The first dummy gate voltage can have an active level or an inactive level as described above, and the active level can be a voltage greater than the threshold voltage of the first dummy transistor DT1, while the inactive level can be a voltage less than the threshold voltage of the first dummy transistor DT1. For example, as Figure 9 As shown, when the first dummy transistor DT1 is an N-type transistor, the effective level of the first dummy gate voltage can be a positive voltage, and the ineffective level of the first dummy gate voltage can be a negative voltage.

[0289] As described above, the second dummy gate voltage can have an active level or an inactive level. An active level can be a voltage greater than the threshold voltage of the second dummy transistor DT2, and an inactive level can be a voltage less than the threshold voltage of the second dummy transistor DT2. For example, as... Figure 9 As shown, when the second dummy transistor DT2 is an N-type transistor, the effective level of the second dummy gate voltage can be a positive voltage, and the ineffective level of the second dummy gate voltage can be a negative voltage.

[0290] The electronic or electrical devices and / or any other related devices or components (e.g., control units, etc.) described herein according to embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Additionally, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices can be processes or threads running on one or more processors within one or more computing devices, executing computer program instructions, and interacting with other system components to perform the various functionalities described herein. The computer program instructions are stored in memory such as random access memory (RAM), which can be implemented in the computing device using standard memory devices. The computer program instructions can also be stored in other non-transitory computer-readable media such as optical disc read-only memory (CD-ROM) or flash memory drives. Furthermore, those skilled in the art will recognize that, without departing from the spirit and scope of the exemplary embodiments of this disclosure, the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices.

[0291] The foregoing is a description of some embodiments of this disclosure and should not be construed as limiting any of the embodiments thereof. Although some embodiments have been described, it will be readily apparent to those skilled in the art that various modifications may be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it should be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: The display panel includes a display area and a non-display area; Multiple light-emitting elements are present in the display area; and The current detection device is located in the non-display area. in: The current detection device includes a controller and a current detection circuit configured to be controlled by the controller; The current detection circuit includes a first driver and a second driver; The first driver includes a first dummy light-emitting element corresponding to a first light-emitting element among the plurality of light-emitting elements configured to provide light of a first color; and The second driver includes a second dummy light-emitting element corresponding to a second light-emitting element among the plurality of light-emitting elements configured to provide light of a second color.

2. The display device according to claim 1, characterized in that, The first driver further includes a first dummy transistor connected between the first terminal and the first dummy light-emitting element.

3. The display device according to claim 2, characterized in that, The current detection device also includes a second terminal connected to the first gate electrode of the first dummy transistor.

4. The display device according to claim 3, characterized in that, The current detection device also includes a third terminal connected to the first anode electrode of the first dummy light-emitting element.

5. The display device according to claim 4, characterized in that, The current detection device also includes a fourth terminal connected to the first cathode electrode of the first dummy light-emitting element.

6. The display device according to claim 5, characterized in that, The second driver also includes a second dummy transistor connected between the fifth terminal and the second dummy light-emitting element.

7. The display device according to claim 6, characterized in that, The current detection device also includes a sixth terminal connected to the second gate electrode of the second dummy transistor.

8. The display device according to claim 7, characterized in that, The current detection device also includes a seventh terminal connected to the second anode electrode of the second dummy light-emitting element.

9. The display device according to claim 8, characterized in that, The second cathode electrode of the second dummy light-emitting element is connected to the fourth terminal.

10. The display device according to claim 9, characterized in that, The display device further includes a resistor connected between the first anode electrode of the first dummy light-emitting element and the second anode electrode of the second dummy light-emitting element.

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