Display device

Abstract

The utility model provides a display device, which is characterized in that through a driving unit provided with a plurality of first pins of a first type and a plurality of second pins of a second type, when the number of the plurality of first pins is equal to the total column number of a plurality of pixel circuit units, at least one second pin can be electrically coupled with at least one fan-out line; therefore, when the number of the plurality of data lines of the display panel is greater than or equal to the total column number of the plurality of pixel circuit units, signals can be transmitted to the excessive data lines through the at least one second pin.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display device is widely used due to its self-luminous, fast response, high contrast, wide viewing angle and flexible substrate.

[0003] The OLED display device includes a plurality of sub-pixels, each of which includes a pixel circuit unit and a light emitting structure, and the light emitting structure is driven by the pixel circuit unit to emit light, thereby realizing display. UTILITY MODEL CONTENT

[0004] The purpose of the present application is to provide a display device.

[0005] In order to achieve the above purpose, the present application provides a display device, comprising a display panel and a driving unit, the driving unit is electrically connected with the display panel;

[0006] The display panel has a display area and a fan-out area on one side of the display area, and comprises:

[0007] A substrate;

[0008] A plurality of pixel circuit units are located on one side of the substrate and arranged in an array;

[0009] A plurality of light emitting structures are located on the side of the plurality of pixel circuit units away from the substrate and arranged in an array, and are electrically coupled with the plurality of pixel circuit units; the total column number N of the plurality of light emitting structures is greater than or equal to the total column number M of the plurality of pixel circuit units, N is an integer greater than or equal to 2, and M is an integer greater than or equal to 2;

[0010] A plurality of data lines are located on one side of the substrate and in the display area, the number K of the plurality of data lines is greater than or equal to the total column number M of the plurality of pixel circuit units, K is an integer greater than or equal to 3, and the plurality of data lines are electrically coupled with the plurality of pixel circuit units;

[0011] A plurality of fan-out lines are located on one side of the substrate and in the fan-out area, and are electrically coupled with the plurality of data lines one by one;

[0012] The driving unit comprises:

[0013] A plurality of first pins of a first type and a plurality of second pins of a second type, the plurality of first pins are electrically coupled with at least part of the plurality of fan-out lines one by one;

[0014] The plurality of second pins are configured to be electrically coupled with at least one of the fan-out lines when the number C of the plurality of first pins is equal to M.

[0015] As can be seen from the above, the display device provided by the present application has the plurality of first pins of the first type and the plurality of second pins of the second type, and at least one of the second pins can be electrically coupled with at least one of the fan-out lines when the number of the plurality of first pins is equal to the total number of columns of the plurality of pixel circuit units, so that the at least one of the second pins can transmit signals for the extra data lines when the number of the plurality of data lines of the display panel is greater than or equal to the total number of columns of the plurality of pixel circuit units. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present application or related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0017] Figure 1A A schematic diagram of an exemplary display device 100 according to an embodiment of the present application is shown.

[0018] Figure 1B A schematic diagram of an exemplary display panel 102 according to an embodiment of the present application is shown.

[0019] Figure 1C A schematic diagram of another exemplary display panel 102 according to an embodiment of the present application is shown.

[0020] Figure 2A A schematic diagram of an exemplary display panel 200 according to an embodiment of the present application is shown.

[0021] Figure 2B A timing diagram of the operation of an exemplary display panel 200 according to an embodiment of the present application is shown.

[0022] Figure 3A A schematic diagram of an exemplary display panel 300 according to an embodiment of the present application is shown.

[0023] Figure 3B A timing diagram of the operation of an exemplary display panel 300 according to an embodiment of the present application is shown.

[0024] Figure 4A A schematic diagram of an exemplary display panel 400 according to an embodiment of the present application is shown.

[0025] Figure 4BA schematic diagram of an exemplary display panel 410 according to embodiments of the present application is shown.

[0026] Figure 4C A schematic diagram of an exemplary display panel 420 according to embodiments of the present application is shown.

[0027] Figure 4D A schematic diagram of an exemplary display panel 430 according to embodiments of the present application is shown.

[0028] Figure 5 A schematic diagram of an exemplary driving unit 500 according to embodiments of the present application is shown.

[0029] Figure 6A A schematic diagram of an exemplary display device 600 according to embodiments of the present application is shown.

[0030] Figure 6B A schematic diagram of an exemplary display device 650 according to embodiments of the present application is shown.

[0031] Figure 6C A schematic diagram of an exemplary FIP according to embodiments of the present application is shown.

[0032] Figure 6D A schematic diagram of an exemplary display device 660 according to embodiments of the present application is shown.

[0033] Figure 6E A schematic diagram of an exemplary display device 670 according to embodiments of the present application is shown.

[0034] Figure 6F A schematic diagram of an exemplary display device 680 according to embodiments of the present application is shown.

[0035] Figure 6G A schematic diagram of an exemplary display device 690 according to embodiments of the present application is shown.

[0036] Figure 6H A schematic diagram of an exemplary display device 700 according to embodiments of the present application is shown. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to specific embodiments and drawings.

[0038] Unless otherwise defined, technical terms and scientific terms used in the present application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Unless otherwise defined, technical terms and scientific terms used in the present application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to identify different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the term encompass the elements or objects listed after the term and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and similar terms do not mean physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", and the like only represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0039] Figure 1A A schematic diagram of an exemplary display device 100 according to embodiments of the present application is shown.

[0040] The display device 100 is a product with image display function, for example, it can be a display, a television, a billboard, a digital photo frame, a laser printer with display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large area wall, a household appliance, an information query device (such as a business query device of an electronic government, a bank, a hospital, a power department, a monitor, etc.).

[0041] As shown in Figure 1A The display device 100 can include a display panel 102. In some embodiments, the display panel 102 can be an organic light emitting diode (OLED) display or a quantum dot light emitting diode (QLED) display.

[0042] Figure 1B A schematic diagram of an exemplary display panel 102 according to embodiments of the present application is shown.

[0043] As shown in Figure 1BAs shown, the display panel 102 has a display area AA and a fanout area BB located on one side of the display area AA. The display area AA is used to display image information. In some embodiments, the display panel 102 may include a substrate 104 and a plurality of sub-pixels 1022 arranged in an array on one side of the substrate 104. Each sub-pixel 1022 may include a light-emitting structure and a pixel circuit unit, the pixel circuit unit being electrically coupled to the light-emitting structure for driving the light-emitting structure to emit light.

[0044] It can be understood that subpixel 1022 is the smallest unit for displaying images on display panel 102. Each subpixel 1022 can display a single color, such as red, green, or blue. Display panel 102 may include multiple red subpixels, multiple green subpixels, and multiple blue subpixels. By adjusting the brightness (grayscale) of subpixels 1022 of different colors, different intensities of red, green, and blue light can be obtained. Furthermore, by superimposing at least two of the different intensities of red, green, and blue light, even more colors of light can be displayed, thus achieving full-color display on display panel 102.

[0045] Figure 1C A schematic diagram of yet another exemplary display panel 102 according to an embodiment of this application is shown.

[0046] like Figure 1C As shown, in some embodiments, the display panel 102 may further include multiple data lines 1024 located in the display area AA and multiple fan-out lines 1026 located in the fan-out area BB. The multiple data lines 1024 are electrically coupled to multiple pixel circuit units to transmit data signals to the pixel circuit units, enabling the display of different grayscale levels. The multiple fan-out lines 1026 are electrically coupled to the multiple data lines 1024 in a one-to-one correspondence.

[0047] like Figure 1C As shown, multiple data lines 1024 are arranged at intervals along a first direction X, and all data lines 1024 extend along a second direction Y. The second direction Y intersects the first direction X, and both the first direction X and the second direction Y can be parallel to the substrate 104. The first direction X and the second direction Y are perpendicular or approximately perpendicular. For example, as shown... Figure 1C As shown, the first direction X is horizontal, and the second direction Y is vertical. Multiple data lines 1024 are spaced at the same or approximately the same distance along the first direction X.

[0048] Back Figure 1BThe plurality of sub-pixels 1022 are arranged in a plurality of columns along the first direction X and a plurality of rows along the second direction Y. As described above, each of the sub-pixels 1022 can include a light-emitting structure and a pixel circuit unit. Thus, the pixel circuit units in the plurality of sub-pixels 1022 can be arranged in a plurality of rows and a plurality of columns along the first direction X and the second direction Y. Figure 1C As shown in FIG. 10, the plurality of data lines 1024 extend along the second direction Y. In this way, one data line 1024 can be electrically coupled to the pixel circuit units in a column of the sub-pixels 1022 arranged along the second direction Y.

[0049] As shown in FIG. 11, the fan-out region BB is adjacent to one side edge of the display region AA along the second direction Y. Thus, the plurality of data lines 1024 are arranged to extend along the second direction Y so that the plurality of data lines 1024 can be electrically coupled to the plurality of fan-out lines 1026 in the fan-out region BB one by one. Figure 1C As shown in FIG. 12, the plurality of fan-out lines 1026 in the fan-out region BB gradually approach and converge, and extend to the side of the fan-out region BB away from the display region AA. This facilitates the electrical coupling between the plurality of fan-out lines 1026 and the driving unit 106 (Integrated Circuit, IC) outside the display panel 102, so that the driving unit 106 is electrically connected to the display panel 102. It can be understood that the driving unit 106 can input signals to each pixel circuit unit through the plurality of fan-out lines 1026 and the plurality of data lines 1024.

[0050] Figure 1C The side of the plurality of fan-out lines 1026 away from the display region AA extends to the side edge of the fan-out region BB away from the display region AA, so that the plurality of fan-out lines 1026 can be electrically coupled to the driving unit 106.

[0051] However, the above implementation increases the occupied space of the plurality of fan-out lines 1026 along the second direction Y, thereby increasing the width of the fan-out region BB along the second direction Y, i.e., increasing the width of the side bezel (e.g., the lower bezel) of the display panel 102, which is not conducive to the realization of narrow bezels of the display panel 102 and affects the visual effect of the display panel 102.

[0052] However, the above implementation increases the occupied space of the plurality of fan-out lines 1026 along the second direction Y, thereby increasing the width of the fan-out region BB along the second direction Y, i.e., increasing the width of the side bezel (e.g., the lower bezel) of the display panel 102, which is not conducive to the realization of narrow bezels of the display panel 102 and affects the visual effect of the display panel 102.

[0053] ​To realize full color, a display device includes sub-pixels that emit light of different colors, e.g., red, green, and blue pixels. In a conventional display device, a plurality of sub-pixels can be arranged in the form of RGB pixels of red, green, and blue. To increase the resolution of the display screen, in some embodiments, the plurality of sub-pixels can be arranged in the form of RGBG pixels of green and red or blue. Since the luminance of green pixels is higher and the sensitivity of the human eye to green is higher, the RGBG pixel array can be used so that the density of green pixels is greater. In the display device of the RGBG pixel array, by having two pixels of green and red or blue for each pixel group (or, each pixel unit, each unit pixel), the unit pixel size can be reduced, and thus the resolution of the display device can be increased.

[0054] Figure 2A A schematic diagram of an exemplary display panel 200 according to embodiments of the present application is shown.

[0055] As shown in Figure 2A , the display panel 200 can include a substrate 202 and a plurality of sub-pixels, each of which can include a light emitting structure 204 and a pixel circuit unit. The plurality of pixel circuit units are arranged in an array on one side of the substrate 202, and the plurality of light emitting structures 204 are arranged in an array on the side of the plurality of pixel units away from the substrate 202, and the plurality of light emitting structures 204 and the plurality of pixel circuit units can be electrically coupled one-to-one. The orthogonal projection of the light emitting structure 204 on the substrate 202 is within the orthogonal projection of the pixel circuit unit on the substrate 202.

[0056] The display panel 200 can further include data lines connected to the pixel circuit units, e.g., data lines Y1, Y2, Y3, and Y4. In some embodiments, the odd columns of light emitting structures 204 can be alternately configured with a first pixel color and a second pixel color, and the even columns of light emitting structures 204 can all be a third pixel color, where the first pixel color can be red, the second pixel color can be blue, and the third pixel color can be green. The pixel circuit units corresponding to the light emitting structures 204 of the first pixel color and the pixel circuit units corresponding to the light emitting structures 204 of the second pixel color in the odd columns are electrically coupled to one data line (e.g., data lines Y1 and Y3), and the pixel circuit units corresponding to the light emitting structures 204 of the third pixel color in the even columns are electrically coupled to another data line (e.g., data lines Y2 and Y4).

[0057] Figure 2B A timing diagram of the operation of an exemplary display panel 200 according to embodiments of the present application is shown.

[0058] In combination Figure 2A and Figure 2BIn some embodiments, the pixel colors of the light emitting structures 204 of the n-1th row of the display panel 200 along the first direction X are in sequence the first pixel color, the third pixel color, the second pixel color, and the third pixel color; the pixel colors of the light emitting structures 204 of the n th row along the first direction X are in sequence the second pixel color, the third pixel color, the first pixel color, and the third pixel color; and the pixel colors of the light emitting structures 204 of the n+1th row along the first direction X are in sequence the first pixel color, the third pixel color, the second pixel color, and the third pixel color. In this way, when the display panel 200 is in operation, the data line Y1 needs to transmit the data voltage (R) of the first pixel color in one row and the data voltage (B) of the second pixel color in one row, the data line Y3 needs to transmit the data voltage (B) of the second pixel color in one row and the data voltage (R) of the first pixel color in one row, and the data lines Y2 and Y4 each transmit the data voltage (G) of the third pixel color in one row.

[0059] However, in the display device with the RGBG pixel array, the alternately providing the data voltage of different pixel colors for one data line can cause large power consumption. As the OLED display panel is more and more deeply involved in the market, the competition trend is also more and more obvious. The standby time of the display device is also more and more pursuing the lowest power consumption as possible.

[0060] In order to reduce the power consumption of the display panel 200 with the RGBG pixel array, in some embodiments, the pixels of different pixel colors can be driven by respective data lines.

[0061] Figure 3A A schematic diagram of an exemplary display panel 300 according to an embodiment of the present application is shown.

[0062] As Figure 3A shown, the display panel 300 can include a substrate 302 and a plurality of sub-pixels, each of which can include a light emitting structure 304 and a pixel circuit unit. The plurality of pixel circuit units are arranged in an array on one side of the substrate 302, and the plurality of light emitting structures 304 are arranged in an array on the side of the plurality of pixel circuit units away from the substrate 302, and the plurality of light emitting structures 304 and the plurality of pixel circuit units can be electrically coupled one by one. The orthographic projection of the light emitting structure 304 on the substrate 302 is located within the orthographic projection of the pixel circuit unit on the substrate 302.

[0063] The display panel 300 can further include data lines connected to the pixel circuit units, for example, data lines Y5, Y6, Y7 and Y8. The light emitting structures 304 in the odd columns can be alternately arranged in the first pixel color and the second pixel color, and the light emitting structures 304 in the even columns can all be in the third pixel color. In some embodiments, the pixel circuit units corresponding to the light emitting structures 304 in the first pixel color in the odd columns and the odd rows (for example, the first column, the n-1th row and the n+1th row in the direction from the data line Y5 to the data line Y8) are electrically coupled to one data line (for example, the data line Y5), the pixel circuit units corresponding to the light emitting structures 304 in the second pixel color in the odd columns and the even rows (for example, the first column, the n th row in the direction from the data line Y5 to the data line Y8) are electrically coupled to another data line (for example, the data line Y7), and the pixel circuit units corresponding to the light emitting structures 304 in the third pixel color in the even columns are electrically coupled to one data line (for example, the data lines Y6 and Y8).

[0064] Figure 3B A timing diagram showing the operation of the exemplary display panel 300 according to an embodiment of the present application is shown.

[0065] In combination Figure 3A and Figure 3B In some embodiments, the pixel colors of the light emitting structures 304 in the n-1th row of the display panel 300 are in the first direction X in the order of the first pixel color, the third pixel color, the second pixel color, and the third pixel color; the pixel colors of the light emitting structures 304 in the n th row are in the first direction X in the order of the second pixel color, the third pixel color, the first pixel color, and the third pixel color; and the pixel colors of the light emitting structures 304 in the n+1th row are in the first direction X in the order of the first pixel color, the third pixel color, the second pixel color, and the third pixel color. Through the above connection mode of the pixel circuit units of the display panel 300 and the data lines Y5, Y6, Y7 and Y8, when the display panel 300 is in operation, the data line Y5 transmits the data voltage (R) of the first pixel color every row, the data line Y7 transmits the data voltage (B) of the second pixel color every row, and the data lines Y6 and Y8 transmit the data voltage (G) of the third pixel color every row. In this way, each data line transmits the data voltage of one pixel color, without alternating transmission between different pixel colors, thereby reducing the power consumption of the display panel.

[0066] It can be understood Figure 3A and Figure 3B It can be understood

[0067] Figure 4AA schematic diagram of an example display panel 400 according to embodiments of the present application is shown.

[0068] As shown in Figure 4A the display panel 400 can have a display area AA, and the display panel 400 includes a substrate 402 and a plurality of sub-pixels, each of which can include a light-emitting structure 404 and a pixel circuit unit 406. The plurality of pixel circuit units 406 are arranged in an array on one side of the substrate 402, and the plurality of light-emitting structures 404 are arranged in an array on the side of the plurality of pixel circuit units 406 away from the substrate 402. In the display panel 400, the total number of columns N of the plurality of light-emitting structures 404 is equal to the total number of columns M of the plurality of pixel circuit units 406, N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, and the plurality of pixel units 406 and the plurality of light-emitting structures 404 are electrically coupled one-to-one.

[0069] As shown in Figure 4A the plurality of sub-pixels in the display panel 400 can be arranged in the form of RGBG pixels. In some embodiments, for any two adjacent columns of light-emitting structures 404, the light-emitting structures 404 in one column are arranged alternately in a first pixel color (e.g., the pixel color of the light-emitting structure 404a) and a second pixel color (e.g., the pixel color of the light-emitting structure 404b), and the plurality of light-emitting structures 404 in the other column all have a third pixel color (e.g., the pixel color of the light-emitting structure 404c), and the pixel colors of the two adjacent light-emitting structures 404 in the same row are different.

[0070] As shown in Figure 4A in some embodiments, the orthogonal projection of any k1th column of light-emitting structures 404 on the substrate 402 is within the orthogonal projection of the k1th column of pixel circuit units 406 on the substrate 402, for the first column of light-emitting structures 404 to the Nth column of light-emitting structures 404. The k1th column of light-emitting structures 404 is electrically coupled one-to-one with the k1th column of pixel circuit units 406, k1 is an integer greater than or equal to 1 and less than or equal to N.

[0071] As shown in Figure 4AAs shown, the display panel 400 further includes a plurality of data lines 408 located on one side of the substrate 402 and in the display area AA. In order to reduce the power consumption of the display panel 200, in some embodiments, the light emitting structures 404a of the first pixel color and the light emitting structures 404b of the second pixel color in the even rows in the display panel 400 are offset by one data line in the direction D (the direction from the first column of light emitting structures 404 to the Nth column of light emitting structures 404), that is, taking the light emitting structures 404a and 404b as an example, the light emitting structure 404b is electrically coupled to the data line B1, the light emitting structure 404a is electrically coupled to the data line Rn, and so on. In this way, after the light emitting structures 404 of the N-1th column of even rows are offset in the direction D, one data line (for example, the data line R') needs to be added to electrically couple the light emitting structures 404 of the N-1th column of even rows.

[0072] In this way, in the display panel 400, the number K of the plurality of data lines 408 is greater than the total number M of columns of the plurality of pixel circuit units 406, K is an integer greater than or equal to 3, and the plurality of data lines 408 are electrically coupled to the plurality of pixel circuit units 406. In some embodiments, the light emitting structures 404 of the Nth column have the third pixel color, the pixel circuit units 406 corresponding to the light emitting structures 404 of the j1th column of one pixel color are electrically coupled to the j1th data line (for example, the data line R1, B1, Rn, Bn), the pixel circuit units 406 corresponding to the light emitting structures 404 of the j1th column of another pixel color are electrically coupled to the j1+2th data line (for example, the data line B1, Rn, Bn, R'), and the pixel circuit units 406 corresponding to the light emitting structures 404 of the j2th column of the third pixel color are electrically coupled to the j2th data line (for example, the data line G1, G2, G2n-1, G2n). Wherein j1 is an odd number greater than or equal to 1 and less than N, and j2 is an even number greater than or equal to 2 and less than or equal to N. The added Kth data line (for example, the data line R') can have the first pixel color or the second pixel color, depending on the arrangement order of the pixel colors of the odd column light emitting structures 404 in the second direction Y.

[0073] In this way, in the display panel 400, each of the data lines R1, G1, B1, G2, Rn, G2n-1, Bn, G2n and R' is used to drive the pixel circuit units 406 of the light emitting structures 404 of the same pixel color, which improves the problem that the data lines in the display panel 200 alternately provide data voltages of different pixel colors, resulting in greater power consumption.

[0074] Figure 4B A schematic diagram of an exemplary display panel 410 according to embodiments of the present application is shown.

[0075] As Figure 4BAs shown, the display panel 410 may have a display area AA, and the display panel 410 includes a substrate 412 and a plurality of sub-pixels. Each sub-pixel may include a light-emitting structure 414 and a pixel circuit unit 416. The plurality of pixel circuit units 416 are located on one side of the substrate 412 and are arranged in an array, and the plurality of light-emitting structures 414 are located on the side of the plurality of pixel circuit units 416 opposite to the substrate 412 and are arranged in an array. In the display panel 410, the total number N of the plurality of light-emitting structures 414 is equal to the total number M of the plurality of pixel circuit units 416, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 2. The plurality of pixel units 416 and the plurality of light-emitting structures 414 are electrically coupled in a one-to-one correspondence.

[0076] like Figure 4B As shown, the multiple sub-pixels in the display panel 410 can be arranged in the form of RGBG pixels. In some embodiments, for any two adjacent columns of light-emitting structures 414, one column of light-emitting structures 414 is alternately set according to a first pixel color (e.g., the pixel color of light-emitting structure 414a) and a second pixel color (e.g., the pixel color of light-emitting structure 414b), and the multiple light-emitting structures 414 in the other column all have a third pixel color (e.g., the pixel color of light-emitting structure 414c). The pixel colors of two adjacent light-emitting structures 414 in the same row are different.

[0077] Considering that having all light-emitting structures 404 in the Nth column of the display panel 400 in the third pixel color can easily lead to overly obvious third pixel color at the edges of the display panel 400, thus causing color shift in the display panel 400, in some embodiments, the light-emitting structures 414 in the Nth column of the display panel 410 are alternately set according to the first pixel color and the second pixel color. In this way, the light-emitting structures 414 in the Nth column of the display panel 410 can form pixel units with the light-emitting structures 414 in the (N-1)th column, improving the color shift problem caused by the single pixel color of the light-emitting structures 404 in the Nth column of the display panel 400.

[0078] like Figure 4B As shown, in some embodiments, in the display panel 410, the orthographic projection of any k1-th column light-emitting structure 414 from the first column to the Nth column of light-emitting structures 414 onto the substrate 412 lies within the orthographic projection of the pixel circuit unit 416 of the k1-th column onto the substrate 412. Any k1-th column light-emitting structure 414 and the k1-th column pixel circuit unit 416 are electrically coupled in a one-to-one correspondence, where k1 is an integer greater than or equal to 1 and less than or equal to N.

[0079] like Figure 4BAs shown, the display panel 410 further includes a plurality of data lines 418 located on one side of the substrate 412 and in the display area AA. The addition of the Nth column of light emitting structures 414 in the display panel 410 requires a corresponding addition of a column of pixel circuit units 416, and a corresponding addition of a data line 418 for driving the pixel circuit units 416 of the Nth column of light emitting structures 414.

[0080] In this way, in the display panel 410, the number K of the plurality of data lines 418 is greater than the total number M of columns of the plurality of pixel circuit units 416, K is an integer greater than or equal to 3, and the plurality of data lines 418 are electrically coupled to the plurality of pixel circuit units 416. In some embodiments, the Nth column of light emitting structures 414 are arranged alternately according to the first pixel color and the second pixel color. The pixel circuit units 416 corresponding to the light emitting structures 414 of one pixel color in the j3th column are electrically coupled to the j3th data line (e.g., data line R1, B1, Rn, Bn), the pixel circuit units 416 corresponding to the light emitting structures 414 of another pixel color in the j3th column are electrically coupled to the j3+2th data line (e.g., data line B1, Rn, Bn, R’), the pixel circuit units 416 corresponding to the light emitting structures 414 of a third pixel color in the j4th column are electrically coupled to the j4th data line (e.g., data line G1, G2, G2n-1, G2n), the pixel circuit units 416 corresponding to the light emitting structures 414 of one pixel color in the Nth column are electrically coupled to the Nth data line (e.g., data line R’), and the pixel circuit units 416 corresponding to the light emitting structures 414 of another pixel color in the Nth column are electrically coupled to the N+1th data line (e.g., data line B’). Here, j3 is an odd number greater than or equal to 1 and less than N, and j4 is an even number greater than or equal to 2 and less than N. The Nth data line (e.g., data line R’) and the N+1th data line (e.g., data line B’) added have the first pixel color or the second pixel color, respectively, depending on the arrangement order of the pixel colors of the odd-numbered columns of light emitting structures 414 along the second direction Y.

[0081] Figure 4C A schematic diagram of an exemplary display panel 420 according to embodiments of the present application is shown.

[0082] As Figure 4CAs shown, the display panel 420 may have a display area AA, and the display panel 420 includes a substrate 422 and a plurality of sub-pixels. Each sub-pixel may include a light-emitting structure 424 and a pixel circuit unit 426. The plurality of pixel circuit units 426 are located on one side of the substrate 422 and are arranged in an array, and the plurality of light-emitting structures 424 are located on the side of the plurality of pixel circuit units 426 opposite to the substrate 422 and are arranged in an array. In the display panel 420, the total number N of the plurality of light-emitting structures 424 is greater than the total number M of the plurality of pixel circuit units 426, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 2. The plurality of pixel units 426 and the plurality of light-emitting structures 424 are electrically coupled.

[0083] like Figure 4C As shown, multiple sub-pixels in the display panel 420 can be arranged in the form of RGBG pixels. In some embodiments, for any two adjacent columns of light-emitting structures 424, one column of light-emitting structures 424 is alternately set with a first pixel color (e.g., the pixel color of light-emitting structure 424a) and a second pixel color (e.g., the pixel color of light-emitting structure 424b), and multiple light-emitting structures 424 in the other column all have a third pixel color (e.g., the pixel color of light-emitting structure 424c). The pixel colors of two adjacent light-emitting structures 424 in the same row are different.

[0084] like Figure 4C As shown, in some embodiments, in the display panel 420, the orthographic projection of any k2-th column light-emitting structure 424 from the first column to the (N-1)th column light-emitting structure 424 onto the substrate 422 lies within the orthographic projection of the pixel circuit unit 426 of the k2-th column onto the substrate 422. Any k2-th column light-emitting structure 424 and the k2-th column pixel circuit unit 426 are electrically coupled in a one-to-one correspondence, where k2 is an integer greater than or equal to 1 and less than or equal to N-1. A light-emitting structure 424 of one color in the first column is electrically coupled to the pixel circuit unit 426 corresponding to a light-emitting structure 424 of the same pixel color in the third column, and a light-emitting structure 424 of another pixel color in the Nth column is electrically coupled to the pixel circuit unit 426 corresponding to a light-emitting structure 424 of the same pixel color in the (N-2)th column.

[0085] like Figure 4C As shown, the display panel 420 also includes multiple data lines 428, which are located on one side of the substrate 422 and in the display area AA. In some embodiments, the light-emitting structure 424 added to the Nth column in the display panel 420 does not have a corresponding additional column of pixel circuit units 426.

[0086] In this way, in the display panel 420, the number K of the plurality of data lines 428 is equal to the total number M of the plurality of pixel circuit units 426, K is an integer greater than or equal to 3, and the plurality of data lines 428 are electrically coupled to the plurality of pixel circuit units 426. In some embodiments, the light emitting structures 424 in the Nth column are arranged alternately according to the first pixel color and the second pixel color. The pixel circuit units corresponding to the light emitting structures 424 of another pixel color in the first column are electrically coupled to the first data line (for example, the data line R1), and the pixel circuit units corresponding to the light emitting structures 424 of one pixel color in the Nth column are electrically coupled to the N-2th data line (for example, the data line Bn). The pixel circuit units corresponding to the light emitting structures 424 of one pixel color in the j5th column are electrically coupled to the j5th data line (for example, the data line B1, Rn, Bn), the pixel circuit units corresponding to the light emitting structures 424 of another pixel color in the j5th column are electrically coupled to the j5-2th data line (for example, the data line R1, B1, Rn), and the pixel circuit units corresponding to the light emitting structures 424 of the third pixel color in the j6th column are electrically coupled to the j6th data line (for example, the data line G1, G2, G2n-1, G2n). Here, j5 is an odd number greater than or equal to 3 and less than N, and j6 is an even number greater than or equal to 2 and less than N.

[0087] In this way, in the display panel 420, although one column of light emitting structures 424 is added, one column of pixel circuit units 426 does not need to be added accordingly. By offsetting the data lines 428 in the direction D, the light emitting structures of the first pixel color and the second pixel color in the even rows are offset in the direction opposite to the direction D, the light emitting structures of one pixel color in the first column can share an anode with the light emitting structures of the same pixel color in the third column, and the light emitting structures of another pixel color in the Nth column can share an anode with the light emitting structures of the same pixel color in the N-2th column, so that the added light emitting structures 424 can be electrically coupled to the pixel circuit units 426 without adding corresponding pixel circuit units 426. In this way, each data line 428 is still used to drive the pixel circuit units 426 of the light emitting structures 424 of the same pixel color, which improves the problem that the display panel 200 has relatively large power consumption due to the data lines alternately providing data voltages of different pixel colors. At the same time, the added column of light emitting structures 424 improves the color deviation problem of the display panel 400.

[0088] Figure 4D A schematic diagram of an exemplary display panel 430 according to an embodiment of the present application is shown.

[0089] As Figure 4DAs shown, the display panel 430 may have a display area AA, and the display panel 430 includes a substrate 432 and a plurality of sub-pixels. Each sub-pixel may include a light-emitting structure 434 and a pixel circuit unit 436. The plurality of pixel circuit units 436 are located on one side of the substrate 432 and are arranged in an array, and the plurality of light-emitting structures 434 are located on the side of the plurality of pixel circuit units 436 away from the substrate 432 and are arranged in an array. In the display panel 430, the total number N of the plurality of light-emitting structures 434 is equal to the total number M of the plurality of pixel circuit units 436, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 2. The plurality of pixel units 436 and the plurality of light-emitting structures 434 are electrically coupled in a one-to-one correspondence.

[0090] like Figure 4D As shown, multiple sub-pixels in the display panel 430 can be arranged in the form of RGBG pixels. In some embodiments, for any two adjacent columns of light-emitting structures 434, one column of light-emitting structures 434 is alternately set with a first pixel color (e.g., the pixel color of light-emitting structure 434a) and a second pixel color (e.g., the pixel color of light-emitting structure 434b), and multiple light-emitting structures 434 in the other column all have a third pixel color (e.g., the pixel color of light-emitting structure 434c). The pixel colors of two adjacent light-emitting structures 434 in the same row are different.

[0091] like Figure 4D As shown, in some embodiments, the orthographic projection of any k1-th column light-emitting structure 434 from the first column to the Nth column light-emitting structure 434 onto the substrate 432 lies within the orthographic projection of the pixel circuit unit 436 of the k1-th column onto the substrate 432. Any k1-th column light-emitting structure 434 and the k1-th column pixel circuit unit 436 are electrically coupled in a one-to-one correspondence, where k1 is an integer greater than or equal to 1 and less than or equal to N.

[0092] like Figure 4D As shown, the display panel 430 also includes multiple data lines 438, which are located on one side of the substrate 432 and in the display area AA. In order to reduce the power consumption of the display panel 200, in some embodiments, the light-emitting structures 434 in the odd-numbered rows of the display panel 430 are offset by one data line in the direction opposite to direction D, and two additional data lines (e.g., data lines R' and G') are added.

[0093] In this way, in the display panel 430, the number K of the plurality of data lines 438 is greater than the total number M of the plurality of pixel circuit units 436, K is an integer greater than or equal to 3, and the plurality of data lines 438 are electrically coupled to the plurality of pixel circuit units 436. In some embodiments, the light emitting structure 434 in the Nth column has the third pixel color, the light emitting structure 434 of one pixel color in the j7th column corresponds to the pixel circuit unit 436 electrically coupled to the j7th data line (for example, the data line R', B1, R1, Bn), the light emitting structure 434 of another pixel color in the j7th column corresponds to the pixel circuit unit 436 electrically coupled to the j7+2th data line (for example, the data line B1, R1, Bn, Rn), and the light emitting structure 434 of the third pixel color in the j8th column corresponds to the pixel circuit unit 436 alternately electrically coupled to the j8th data line (for example, the data line G', G1, G2, G2n-1) and the j8+2th data line (for example, the data line G1, G2, G2n-1, G2n). Wherein, j7 is an odd number greater than or equal to 1 and less than N, and j8 is an even number greater than or equal to 2 and less than or equal to N. The first added data line (for example, the data line R') can have the first pixel color or the second pixel color, depending on the arrangement order of the pixel color of the odd column light emitting structure 434 along the second direction Y. The second added data line (for example, the data line G') has the third pixel color.

[0094] In this way, in the display panel 430, each data line 438 is used to drive the pixel circuit unit 436 of the light emitting structure 434 of the same pixel color, which improves the problem that the data lines in the display panel 200 alternately provide data voltages of different pixel colors to generate greater power consumption. The display panels 400-430 in the above embodiments can be ADP (Advanced Diamond Pixel) display panels.

[0095] As described above, the plurality of fan-out lines 1026 of the display panel 102 occupies space along the second direction Y, thereby causing the width of the fan-out area BB along the second direction Y to increase, that is, causing the width of the side frame (for example, the lower frame) of the display panel 102 to increase, which is not conducive to the display panel 102 to achieve a narrow frame and affects the visual effect of the display panel 102.

[0096] Fanout in Panel (FIP) or Fanout in AA (FIAA) allows the fanout area traces to be placed in the AA area, thus achieving an extremely narrow bottom bezel. Therefore, FIP or FIAA is a crucial function, and incorporating FIP or FIAA functionality into the aforementioned display panels 400-430 can provide a low-power display device with an extremely narrow bottom bezel. However, as mentioned above, some display panels 400-430 require additional data lines, and correspondingly, additional fanout lines electrically coupled to these data lines are also needed. Currently, the number of pins in the driver unit electrically coupled to the fanout lines is fixed; that is, the current driver unit does not have extra pins to electrically couple with the added fanout lines. Therefore, there is currently no available driver unit for achieving a low-power display device with an extremely narrow bottom bezel.

[0097] In view of this, this application provides a display device in which, through a driving unit having a plurality of first pins of a first type and a plurality of second pins of a second type, when the number of the plurality of first pins is equal to the total number of columns of the plurality of pixel circuit units, at least one second pin can be electrically coupled to at least one fan-out line, so that when the number of the plurality of data lines on the display panel is greater than or equal to the total number of columns of the plurality of pixel circuit units, signals can be transmitted for the extra data lines through the at least one second pin.

[0098] Figure 5 A schematic diagram of an exemplary driving unit 500 according to an embodiment of this application is shown.

[0099] like Figure 5 As shown, in some embodiments, the driving unit 500 may include a plurality of first pins 502 of a first type and a plurality of second pins 504 of a second type. The plurality of second pins 504 are located on at least one side of the plurality of first pins 502. For example, the number of the plurality of second pins 504 may be four, and the four second pins 504 are evenly distributed on both sides of the plurality of first pins 502. The plurality of second pins 504 of the second type are configured such that, when the number C of the plurality of first pins 502 is equal to the total number M of the plurality of pixel circuit units, at least one second pin 504 is electrically coupled to at least one fan-out line, where C is an integer greater than or equal to 2. That is, the plurality of second pins 504 can be used to electrically couple to fan-out lines corresponding to data lines added in the display panels 400-430 to achieve a low-power display device with an extremely narrow bottom bezel.

[0100] Figure 6A A schematic diagram of an exemplary display device 600 according to an embodiment of this application is shown.

[0101] like Figure 6AAs shown, the display device 600 can include a display panel 602 and a driving unit 500 electrically connected with the display panel 602. The display panel 602 can have a display area AA and a fan-out area BB located at one side of the display area AA. In order to reduce the side frame (e.g., the lower frame) width of the display panel 102, the display panel 602 can include a substrate 606, a plurality of data lines 608 located at one side of the substrate 606 and in the display area AA, and a plurality of fan-out lines 610 located at one side of the substrate 606 and in the fan-out area BB and electrically coupled with the plurality of data lines 608 one by one. The plurality of data lines 608 are arranged at intervals along a first direction X and each of the plurality of data lines 608 extends along a second direction Y intersecting the first direction X.

[0102] As shown, in some embodiments, the display area AA can include a middle display area 612 and two side display areas 614, the middle display area 612 being located between the two side display areas 614. The driving unit 500 can include a middle input area 6042 and two side input areas 6044, the middle input area 6042 being located between the two side input areas 6044. Figure 6A

[0103] The side display area 614 can include a plurality of first data lines 6142 and A second data lines 6144, A being a positive integer greater than 1. In a direction of the side display area 614 pointing to the middle display area 612, the first data line 6144 to the A-th data line 6144 are arranged in sequence.

[0104] The side input area 6044 can include at least part of the plurality of first pins 502 and the plurality of second pins 504, at least part of the plurality of first pins 502 can include a plurality of first input ends 5022 and A second input ends 5024, A being a positive integer greater than 1. The plurality of second pins 504 can include B second input ends 5042, B being a positive integer greater than 1.

[0105] ​When the display panel 400-430 increases the data lines, in some embodiments, the display device can include a display panel and a driving unit electrically connected with the display panel; wherein the display panel has a display area and a fan-out area located at one side of the display area, and includes: a substrate, a plurality of pixel circuit units arranged in an array on one side of the substrate, a plurality of light-emitting structures arranged in an array on the side of the plurality of pixel circuit units away from the substrate, and the plurality of light-emitting structures being electrically coupled with the plurality of pixel circuit units. The total column number N of the plurality of light-emitting structures is greater than or equal to the total column number M of the plurality of pixel circuit units, N is an integer greater than or equal to 2, and M is an integer greater than or equal to 2. The display panel further includes a plurality of data lines located on one side of the substrate and in the display area, the number K of the plurality of data lines is greater than or equal to the total column number M of the plurality of pixel circuit units, K is an integer greater than or equal to 3, and the plurality of data lines are electrically coupled with the plurality of pixel circuit units. A plurality of fan-out lines are located on one side of the substrate and in the fan-out area, and are electrically coupled with the plurality of data lines in a one-to-one correspondence. The driving unit includes a plurality of first pins of a first type and a plurality of second pins of a second type, and the plurality of first pins are electrically coupled with at least part of the plurality of fan-out lines in a one-to-one correspondence, wherein the plurality of second pins are configured to, when the number C of the plurality of first pins is equal to M, electrically couple at least one second pin with at least one fan-out line.

[0106] Taking the display panel 400 as an example, Figure 6B A schematic diagram of an exemplary display device 650 according to embodiments of the present application is shown.

[0107] As Figure 6B shown, since the number of the plurality of first pins 502 is equal to the total column number of the plurality of pixel circuit units, that is, the number of the data lines R1-G2n is equal to the number of the plurality of first pins 502 and is electrically coupled with the plurality of first pins 502 in a one-to-one correspondence. As not considering the reverse arrangement, in some embodiments, the increased data line R' of the display panel 400 needs to be electrically coupled with one pin of the plurality of second pins 504 through the fan-out line, so as to provide the data voltage for the increased data line through the second pin.

[0108] In order to realize a display device with low power consumption and extremely narrow bottom frame, whether the increased data line participates in the insertion arrangement of FIP is very important.

[0109] Figure 6C A schematic diagram of an exemplary insertion arrangement of FIP according to embodiments of the present application is shown.

[0110] As Figure 6C shown, taking the horizontal resolution of the display panel as 1280 as an example, then the number of channels of the driving unit required to be used by the corresponding data line is 2560. Taking the number c of channels required to be locally inserted as 300, the insertion area insertion data as 4, and the insertion area normal data as 2 as an example.Figure 6C The first row in the first row represents the data line, and the second row represents the input end.

[0111] Figure 6C The first row in the first row includes a first data line 6142 and a second data line 6144, and the first data line 6142 can be a normal data line, and the second data line 6144 can be an insertion sequence data line. Figure 6C The second row in the second row includes a first input end 5022 and a second input end 5024, and the first input end 5022 can be a normal input end, and the second input end 5024 can be an insertion sequence input end.

[0112] Figure 6C The number marked on the data line in the first row represents the number of the data line, and the number marked on the input end represents the number of the input end. It can be seen that along the side display area 614, the direction of the middle display area 612 is pointed to, and the plurality of data lines are arranged in order according to the number.

[0113] And in the local insertion sequence input end, in some embodiments, A second input ends 5024 or A+B second input ends 5024 are divided into a plurality of second input end groups, and each second input end group includes at least one second input end 5024. A plurality of first input ends 5022 are divided into a plurality of first input end groups, and each first input end group includes at least one first input end 5022. The second input end group and the first input end group are alternately arranged, and the second input end group is close to the boundary of the side input area 6044 away from the middle input area 6042. The first input end group and the second input end group are alternately arranged, that is, along the side input area 6044, the direction of the middle input area 6042 is pointed to, 4 second input ends 5024 are arranged in reverse order (that is, arranged in the order of the 300th input end, the 299th input end, the 298th input end, and the 297th input end), then 2 first input ends 5022 are arranged in order (that is, arranged in the order of the 301st input end and the 302nd input end), then 4 second input ends 5024 are arranged in reverse order (that is, arranged in the order of the 296th input end, the 295th input end, the 294th input end, and the 293rd input end), then 2 first input ends 5022 are arranged in order (that is, arranged in the order of the 303rd input end and the 304th input end), and so on. Among them, 2 first input ends 5022 can form a first input end group, and 4 second input ends 5024 can form a second input end group, and in some embodiments, each first input end group includes the same number of first input ends, and each second input end group includes the same number of second input ends.

[0114] The plurality of data lines and the plurality of input ends are connected according to the number by fan-out lines. For example, as shown in Figure 6CAs shown, after the input terminals are partially inserted in order, the 300th data line is electrically coupled to the 300th input terminal through the fan-out line 618, and the 301st data line is electrically coupled to the 301st input terminal through the fan-out line 620. In combination with Figure 6A and Figure 6C The connection line 622 can include a first portion 6222 and a second portion 6224. For the second data line 6144 located at the edge of the side display area 614, the second data line 6144 can be electrically coupled to the first portion 6222 of the connection line 622, and then electrically coupled to the corresponding second fan-out line 6104 through the second portion 6224 of the connection line 622. The second portion 6224 is arranged alternately with the orthogonal projection of the first data line 6144 on the substrate 606, so that the second data line 6144 located at the edge of the side display area 614 is electrically coupled to the inserted input terminal.

[0115] In some embodiments, the side display area 614 can further include a plurality of connection lines 622. A plurality of second data lines 6144 are electrically coupled to a plurality of second fan-out lines 6104 one by one through the corresponding plurality of connection lines 622. The lengths of the connection lines 622 to which the first second data line 6144 to the A+Bth second data line 6144 are coupled decrease in turn. Through the above arrangement, the second data line 6144 extending to the corner boundary of the display panel 602 can be guided to a position close to the middle display area 612 and then electrically coupled to the corresponding second input terminal 5024. In this way, the FIP technology can be well implemented, and a display device with low power consumption and an extremely narrow bottom frame can be provided.

[0116] It should be noted that, Figure 6A Only the arrangement of the side display area on one side is taken as an example for description. The arrangement of the side display area on the other side not shown is the same as that described in the above embodiments, which will not be described herein again.

[0117] The two pins added to the left and right of the driving unit 500 can be independently controlled. Assuming that the resolution of the driving unit 500 to which the pins are added becomes 1444x3200, when the driving unit 500 is used on a common panel (a panel without added data lines), it can only support a panel with a maximum resolution of 1440x3200. In this way, the driving unit does not need to be modified, and the development cost of the driving unit is reduced.

[0118] The additional pins on the left and right sides of the driver unit 500 are only needed when the display panel's resolution reaches the maximum resolution of the driver unit 500. If the display panel's resolution is less than the driver unit 500's maximum resolution—for example, if the driver unit 500 supports a horizontal resolution of 1440, but the connected display panel only supports a horizontal resolution of 1280—then the driver unit 500 will have extra pins. In this case, the number C of multiple first pins can be greater than M. Therefore, the data lines added to the display panels 400-430 do not need to be connected to the additional second pins on the left and right sides of the driver unit 500; they can be connected to the remaining first pins. This avoids excessively long traces connected to the second pins, which could lead to abnormal trace impedance.

[0119] In some embodiments, the display area includes a central display area and two side display areas, with the central display area located between the two side display areas. The driving unit includes a central input area and two side input areas, with the central input area located between the two side input areas. The side input areas include at least a plurality of first pins and a plurality of second pins. The at least a plurality of first pins include a plurality of first input terminals and A second input terminals, where A is a positive integer greater than 1. The plurality of second pins include B second input terminals, where B is a positive integer greater than 1. The side display areas include a plurality of first data lines and A second data lines. The plurality of fan-out lines include a plurality of first fan-out lines and a plurality of second fan-out lines. The plurality of first data lines are electrically coupled to the plurality of first fan-out lines in a one-to-one correspondence. The plurality of first fan-out lines are electrically coupled to the plurality of first input terminals in a one-to-one correspondence. The A second data lines are electrically coupled to the plurality of second fan-out lines in a one-to-one correspondence. The plurality of second fan-out lines are electrically coupled to A second input terminals or A+B second input terminals in a one-to-one correspondence.

[0120] As mentioned above, whether the added data lines in the ADP display panel participate in the interpolation sorting is crucial. This participation depends on whether the added data lines transmit actual data signals. If there are actual data signals, they participate in the interpolation sorting; otherwise, they do not. Taking display panel 400 as an example... Figure 6B As shown, the data line R' added to the display panel 400 needs to utilize one of the second pins 504 added to the right side of the driving unit 500, and the transmitted data is the data of the (N-1)th column pixel. Therefore, since data line R' has actual data, it needs to participate in reverse sorting. The reverse sorting method is as described in the above embodiment, and will not be repeated here. Since the pins corresponding to data line R1 and data line R' respectively drive the pixel circuit units corresponding to the light-emitting structures of odd-numbered rows and even-numbered rows, in some embodiments, the buffer in the driving unit 500 can be a row buffer. The row buffer can store data on a row-by-row basis to save data storage space in the driving unit.

[0121] As shown in Figure 6B In some embodiments, the side display area further includes B second data lines, B second input ends are configured to be arranged in sequence from the first second input end to the A+B second input end in a direction from the middle input area to the side input area when the total number N of the total columns of the plurality of light emitting structures is equal to the total number M of the total columns of the plurality of pixel circuit units and the number K of the plurality of data lines is greater than the total number M of the total columns of the plurality of pixel circuit units. Since the data line R' needs to participate in reverse arrangement, the total number of the second data lines is A+B. The first second data line to the A+B second data line are arranged in sequence. The A+B second input ends are electrically coupled to the A+B second data lines one by one through the corresponding plurality of second fan-out lines.

[0122] As shown in Figure 6B In some embodiments, the N+1th data line (data line R') has the first pixel color or the second pixel color, and the plurality of second pins 504 are configured to electrically couple the fan-out line corresponding to the N+1th data line to the second pin when the number C of the plurality of first pins 502 is equal to M.

[0123] Figure 6D A schematic diagram of an exemplary display device 660 according to embodiments of the present application is shown. Figure 6D The display device 660 shown can be a derivative of the display device 650.

[0124] As shown in Figure 6D The display device 660 can include a display panel 440, which in some embodiments can have a display area AA, and the display panel 440 includes a substrate 442 and a plurality of sub-pixels, each of which can include a light emitting structure 444 and a pixel circuit unit 446. The plurality of pixel circuit units 446 are arranged in an array on one side of the substrate 442, and the plurality of light emitting structures 444 are arranged in an array on the side of the plurality of pixel circuit units 446 away from the substrate 442. In the display panel 440, the total number N of the plurality of light emitting structures 444 is equal to the total number M of the plurality of pixel circuit units 446, N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, and the plurality of pixel units 446 and the plurality of light emitting structures 444 are electrically coupled one by one.

[0125] In the display panel 440, the pixel circuit units 446 corresponding to the light emitting structures 444 in the first column even rows are electrically coupled with the added data line B', and the pixel circuit units 446 corresponding to the light emitting structures 444 in the first column odd rows are electrically coupled with the data line R1. The pixel circuit units 446 corresponding to the light emitting structures 444 in the even columns are electrically coupled with the data lines G1, G2, G2n-1 and G2n. Except for the first column, the pixel circuit units 446 corresponding to the light emitting structures 444 in the odd columns odd rows are electrically coupled with the data lines B1, Rn, Bn, and the pixel circuit units 446 corresponding to the light emitting structures 444 in the odd columns even rows are electrically coupled with the data lines R1, B1, Rn. Since the pixel arrangement order is RGBG or BGRG, the added data line B' in the display panel 440 cannot be connected to the second pin 504 adjacent to the data line R1, and needs to be electrically coupled with the second pin 5046.

[0126] The added data line B' in the display panel 440 has actual data transmission, and therefore, the input end corresponding to the data line B' needs to participate in the reverse sorting. The reverse sorting method is described above, and will not be described here again.

[0127] Figure 6E A schematic diagram of an example display device 670 according to embodiments of the present application is shown.

[0128] As Figure 6E shown, two data lines, i.e., the data lines R' and B', are added in the display panel 410, and therefore, two second pins 504 are added on the right side of the driving unit 500. If the reverse sorting is not considered, the added data lines R' and B' are respectively electrically coupled with the plurality of second pins 504. In some embodiments, the Nth data line and the N+1th data line respectively have a first pixel color and a second pixel color, and the plurality of second pins are configured such that when the number C of the plurality of first pins is equal to M, the fan-out line corresponding to the Nth data line and the fan-out line corresponding to the N+1th data line are electrically coupled with the plurality of second pins.

[0129] As considering reverse order sorting, assuming the resolution of the display panel 410 is 1441, the driving unit 500 needs to increase the pin. But in the use of the display panel 410, the resolution of the picture to be displayed is 1440. At this time, the data line B' can have no actual data and does not participate in the reverse order arrangement. In some embodiments, in the display device 670, the data line R' has actual data in the even row, so the data line R' needs to participate in the reverse order arrangement, and the data line B' has no actual data in both the odd row and the even row, so the data line B' does not participate in the reverse order arrangement. In order to solve the color deviation problem of the display panel, the pixel in the last column of the display panel 410 still needs to be displayed. In some embodiments, in the display device 670, the display data of the Nth column of light emitting structure 414 is obtained by copying the display data of the N-4th column of light emitting structure 414, as shown by the arrow 672 in FIG. 6. The display brightness of the Nth column of light emitting structure 414 can be adjusted by multiplying the display data of the N-4th column of light emitting structure 414 by a coefficient, which can adjust the color deviation of the edge of the display panel and will not make the brightness of the Nth column of light emitting structure 414 too bright, so as to make the display effect more abrupt. Figure 6E

[0130] Assuming that the data lines R' and B' both have actual data transmission, the data lines R' and B' need to participate in the reverse order arrangement. In some embodiments, the side display area 614 further includes B second data lines 6144, and the B second input terminals 5024 are configured to: when the total column number N of the plurality of light emitting structures 414 is equal to the total column number M of the plurality of pixel circuit units 416 and the number K of the plurality of data lines 418 is greater than the total column number M of the plurality of pixel circuit units 416, the first second input terminal 5024 to the A+Bth second input terminal 5024 are arranged in sequence along the direction of the middle input area 6042 pointing to the side input area 6044. The first second data line 6144 to the A+Bth second data line 6144 are arranged in sequence. The A+B second input terminals 5024 are electrically coupled to the A+B second data lines 6144 in one-to-one correspondence through the corresponding plurality of second fan-out lines 6104. In this way, after the reverse order arrangement, the data lines R' and B' located at the edge position can be connected to the input terminal close to the middle display area 612 of the display panel 410 through the connection line. In this way, the gathering of the plurality of fan-out lines at the position close to the rounded corner boundary of the fan-out area can be reduced, the width of the lower frame of the display panel is effectively narrowed, and the FIP technology is well implemented, thereby providing a display device with low power consumption and extremely narrow lower frame.

[0131] Figure 6F A schematic diagram of an exemplary display device 680 according to embodiments of the present application is shown.

[0132] As Figure 6F ​As shown, the display device 680 may include a display panel 420. The display panel 420 does not have additional data lines, therefore the display device 680 does not require the additional pins added in the driving unit 500. Without considering reverse arrangement, in some embodiments, in the display device 680, multiple first pins 502 are electrically coupled one-to-one with multiple fan-out lines 610 corresponding to multiple data lines 428. Considering reverse arrangement, the data lines 428 located at the edge of the display panel 420 are connected to a position near the central display area 612 via connecting lines 622. This reduces the convergence of multiple fan-out lines near the rounded corner boundary of the fan-out area, effectively narrowing the width of the bottom bezel of the display panel, thus effectively implementing FIP technology and providing a low-power display device with an extremely narrow bottom bezel.

[0133] Figure 6G A schematic diagram of an exemplary display device 690 according to an embodiment of this application is shown.

[0134] like Figure 6G As shown, the display device 690 may include a display panel 430, which has two additional data lines (e.g., data lines R' and G') added in the direction opposite to direction D. Therefore, the display device needs to use the additional pins in the driving unit 500. Without considering reverse arrangement, in some embodiments, the first data line (e.g., data line R') has a first pixel color or a second pixel color, and the second data line (e.g., data line G') has a third pixel color. A plurality of second pins 504 are configured such that, when the number C of the plurality of first pins 502 is equal to M, the fan-out line 610 corresponding to the first data line and the fan-out line 610 corresponding to the second data line are electrically coupled to the plurality of second pins 504. If the arrangement is reversed, the data line 428 located at the edge of the display panel 430 is connected to the position near the central display area 612 via the connecting line 622. This reduces the convergence of multiple fan-out lines near the rounded corner boundary of the fan-out area, effectively narrowing the width of the bottom bezel of the display panel. This effectively realizes the FIP technology and provides a display device with low power consumption and an extremely narrow bottom bezel.

[0135] Figure 6H A schematic diagram of an exemplary display device 700 according to an embodiment of this application is shown. Figure 6H The display device 700 shown can be a derivative of the display device 690.

[0136] like Figure 6HAs shown, the display device 700 can include a display panel 450, which in some embodiments can have a display area AA, and the display panel 450 includes a substrate 452 and a plurality of sub-pixels, each of which can include a light-emitting structure 454 and a pixel circuit unit 456. The plurality of pixel circuit units 456 are arranged in an array on one side of the substrate 452, and the plurality of light-emitting structures 454 are arranged in an array on the side of the plurality of pixel circuit units 456 away from the substrate 452. In the display panel 450, the total number of columns N of the plurality of light-emitting structures 454 is equal to the total number of columns M of the plurality of pixel circuit units 456, N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, and the plurality of pixel units 456 and the plurality of light-emitting structures 454 are electrically coupled in a one-to-one correspondence.

[0137] In some embodiments, the light-emitting structures 454 in the odd rows in the display panel 450 are offset by one data line in a direction opposite to the direction D, and two data lines (for example, data lines R1 and G1) are added, which are electrically coupled to the plurality of first pins 502 through the fan-out lines 610 without considering the reverse arrangement, so that the data lines Rn+1 and Gn+1 are electrically coupled to the plurality of second pins 504 through the fan-out lines 610, respectively. If the reverse arrangement is considered, the data lines Rn+1 and Gn+1 located at the edge of the display panel are connected to the input end close to the display area 612 in the middle of the display panel through the connection lines 622. In this way, the gathering of the plurality of fan-out lines at the position close to the rounded corner boundary in the fan-out area can be reduced, the width of the lower frame of the display panel can be effectively narrowed, and the FIP technology can be well implemented, thereby providing a display device with low power consumption and extremely narrow lower frame.

[0138] The display device provided in the present application can be electrically coupled to at least one second pin through at least one fan-out line when the number of the plurality of first pins is equal to the total number of columns of the plurality of pixel circuit units, so that the at least one second pin can transmit signals to the excess data lines when the number of the plurality of data lines of the display panel is greater than or equal to the total number of columns of the plurality of pixel circuit units.

[0139] It should be understood by those of ordinary skill in the art that the above discussion of any of the embodiments is merely exemplary and is not intended to suggest the scope of the present application (including claims) is limited to these examples; under the concept of the present application, the above embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0140] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will be omitted as not to unnecessarily obscure the embodiments of the application being presented. Moreover, the devices can be shown in block diagram form in order to avoid unnecessary obscurity of the present embodiments, and this also acknowledges the fact that the details in regard to the implementation of such block diagram devices are highly dependent on the platform within which the present embodiments are to be implemented (i.e., such details should be well within the purview of one of ordinary skill in the art). Where specific details are set forth in order to describe an illustrative embodiment of the application, it will be apparent to one of ordinary skill in the art that the embodiment of the application can be practiced without these specific details. In other instances, detailed descriptions of well-known methods, devices, and materials can be omitted so as not to obscure the description of the present embodiments of the application. It is intended that the specific embodiments disclosed herein are presented by way of example only and that the present application is not limited by the embodiments presented herein.

[0141] Although the present application has been described in connection with certain specific embodiments thereof, many modifications, changes, variations and substitutions will be apparent to those of ordinary skill in the art. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0142] It is therefore intended that the present application cover all such modifications, changes, variations and substitutions that fall within the broad scope of the appended claims. Accordingly, any one or more of the features, functions, structures, or other aspects of the embodiments described herein can be combined in any suitable manner to form additional embodiments, which are also within the scope of the present application. Thus, various additional embodiments of the present application are also contemplated. Therefore, the foregoing description is not intended to be limiting. Hence, any non-included alternatives, modifications, or variations should be understood as within the scope of the present application.

Claims

1. A display device, comprising a display panel and a driving unit, wherein the driving unit is electrically connected to the display panel; in, The display panel has a display area and a fan-out area located on one side of the display area, and includes: Substrate; Multiple pixel circuit units are located on one side of the substrate and arranged in an array; Multiple light-emitting structures are located on the side of the multiple pixel circuit units away from the substrate and arranged in an array, and are electrically coupled to the multiple pixel circuit units; the total number of columns N of the multiple light-emitting structures is greater than or equal to the total number of columns M of the multiple pixel circuit units, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 2. Multiple data lines are located on one side of the substrate and in the display area. The number of data lines K is greater than or equal to the total number of columns M of the multiple pixel circuit units, and K is an integer greater than or equal to 3. The multiple data lines are electrically coupled to the multiple pixel circuit units. Multiple fan-out lines are located on one side of the substrate and in the fan-out area, and are electrically coupled to the multiple data lines one by one. The driving unit includes: A plurality of first pins of the first type and a plurality of second pins of the second type, wherein the plurality of first pins are electrically coupled to at least a portion of the plurality of fan-out lines in a one-to-one correspondence; The plurality of second pins are configured such that, when the number C of the plurality of first pins is equal to M, at least one second pin is electrically coupled to at least one fan-out line, where C is an integer greater than or equal to 2.

2. The display device as claimed in claim 1, wherein, The display area includes a central display area and two side display areas, with the central display area located between the two side display areas; the driving unit includes a central input area and two side input areas, with the central input area located between the two side input areas; The side input area includes: at least a portion of the plurality of first pins and the plurality of second pins, wherein at least a portion of the plurality of first pins includes a plurality of first input terminals and A second input terminals, where A is a positive integer greater than 1; the plurality of second pins includes B second input terminals, where B is a positive integer greater than 1; The side display area includes: multiple first data lines and A second data lines; The multiple fan-out lines include multiple first fan-out lines and multiple second fan-out lines. The multiple first data lines are electrically coupled to the multiple first fan-out lines in a one-to-one correspondence. The multiple first fan-out lines are electrically coupled to the multiple first input terminals in a one-to-one correspondence. The A second data lines are electrically coupled to the multiple second fan-out lines in a one-to-one correspondence. The multiple second fan-out lines are electrically coupled to the A second input terminals or A+B second input terminals in a one-to-one correspondence.

3. The display device as claimed in claim 2, wherein, The side display area also includes B second data lines. The B second input terminals are configured such that, when the total number N of the plurality of light-emitting structures is equal to the total number M of the plurality of pixel circuit units and the number K of the plurality of data lines is greater than the total number M of the plurality of pixel circuit units, the first second input terminal to the A+B second input terminals are arranged sequentially along the direction from the central input area to the side input area; the first second data line to the A+B second data lines are arranged sequentially; and the A+B second input terminals are electrically coupled to the A+B second data lines one-to-one through the corresponding plurality of second fan-out lines.

4. The display device as claimed in claim 2, wherein, The B second input terminals are configured such that, when the total number N of the plurality of light-emitting structures is greater than the total number M of the plurality of pixel circuit units and the number K of the plurality of data lines is greater than or equal to the total number M of the plurality of pixel circuit units, the first second input terminal to the Ath second input terminal are arranged sequentially along the direction from the central input area to the side input area; the first second data line to the Ath second data line are arranged sequentially; and the A second input terminals are electrically coupled to the Ath second data line in a one-to-one correspondence through the corresponding plurality of second fan-out lines.

5. The display device as claimed in claim 3, wherein, A second input terminal or A+B second input terminals are divided into multiple groups of second input terminals, each group of second input terminals includes at least one second input terminal; multiple first input terminals are divided into multiple groups of first input terminals, each group of first input terminals includes at least one first input terminal; the second input terminal groups and the first input terminal groups are alternately arranged, with the second input terminal groups located near the boundary of the side input area and away from the boundary of the central input area.

6. The display device as claimed in claim 3, wherein, The side display area also includes multiple connecting lines. The A second data line is electrically coupled to the multiple second fan-out lines in a one-to-one correspondence through the corresponding multiple connecting lines. The lengths of the connecting lines coupled to the first second data line to the A second data line or the A+B second data lines decrease sequentially.

7. The display device as claimed in claim 6, wherein, The connecting line includes a first part and a second part that are coupled to each other. The first part is electrically coupled to the corresponding second data line, and the second part is electrically coupled to the corresponding second fan-out line. The orthographic projection of the second part on the substrate is alternately arranged with the orthographic projection of the first data line on the substrate.

8. The display device as claimed in claim 5, wherein, Each of the first input terminal groups includes the same number of first input terminals; each of the second input terminal groups includes the same number of second input terminals.

9. The display device as claimed in claim 1, wherein, For any two adjacent columns of the light-emitting structures, the light-emitting structures in one column are set alternately according to the first pixel color and the second pixel color, and the multiple light-emitting structures in the other column all have a third pixel color, and the pixel colors of two adjacent light-emitting structures in the same row are different.

10. The display device as claimed in claim 9, wherein, For any k1th column of the light-emitting structure from the first column to the Nth column, the orth projection of the light-emitting structure on the substrate lies within the orth projection of the pixel circuit unit in the k1th column on the substrate. The light-emitting structure in any k1-th column is electrically coupled to the pixel circuit unit in the k1-th column in a one-to-one correspondence, where k1 is an integer greater than or equal to 1 and less than or equal to N.

11. The display device as claimed in claim 10, wherein, The light-emitting structure in the Nth column has a third pixel color; The pixel circuit unit corresponding to the light-emitting structure of one pixel color in column j1 is electrically coupled to the data line j1; the pixel circuit unit corresponding to the light-emitting structure of another pixel color in column j1 is electrically coupled to the data line j1+2; and the pixel circuit unit corresponding to the light-emitting structure of the third pixel color in column j2 is electrically coupled to the data line j2. Where j1 is an odd number greater than or equal to 1 and less than N, and j2 is an even number greater than or equal to 2 and less than or equal to N; The N+1th data line has a first pixel color or a second pixel color, and the plurality of second pins are configured such that when the number C of the plurality of first pins is equal to M, the fan-out line corresponding to the N+1th data line is electrically coupled to the second pin.

12. The display device as claimed in claim 10, wherein, The light-emitting structure in the Nth column is set alternately according to the first pixel color and the second pixel color; The pixel circuit unit corresponding to the light-emitting structure of one pixel color in column j3 is electrically coupled to the data line j3; the pixel circuit unit corresponding to the light-emitting structure of another pixel color in column j3 is electrically coupled to the data line j3+2; the pixel circuit unit corresponding to the light-emitting structure of the third pixel color in column j4 is electrically coupled to the data line j4; the pixel circuit unit corresponding to the light-emitting structure of one pixel color in column N is electrically coupled to the data line N; and the pixel circuit unit corresponding to the light-emitting structure of another pixel color in column N is electrically coupled to the data line N+1. Where j3 is an odd number greater than or equal to 1 and less than N, and j4 is an even number greater than or equal to 2 and less than N; The Nth data line and the N+1th data line have a first pixel color and a second pixel color, respectively. The plurality of second pins are configured such that when the number C of the plurality of first pins is equal to M, the fan-out line corresponding to the Nth data line and the fan-out line corresponding to the N+1th data line are electrically coupled to the plurality of second pins.

13. The display device as claimed in claim 9, wherein, For any k2-th column of the light-emitting structure from the first column to the (N-1)-th column, the orth projection of the light-emitting structure on the substrate lies within the orth projection of the pixel circuit unit in the k2-th column on the substrate. The light-emitting structure in any k2-th column is electrically coupled to the pixel circuit unit in the k2-th column in a one-to-one correspondence, where k2 is an integer greater than or equal to 1 and less than or equal to N-1; The light-emitting structure of one pixel color in the first column is electrically coupled to the pixel circuit unit corresponding to the light-emitting structure of the same pixel color in the third column, and the light-emitting structure of another pixel color in the Nth column is electrically coupled to the pixel circuit unit corresponding to the light-emitting structure of the same pixel color in the (N-2)th column.

14. The display device as claimed in claim 13, wherein, The light-emitting structure in the Nth column is set alternately according to the first pixel color and the second pixel color; The pixel circuit unit corresponding to the light-emitting structure of another pixel color in the first column is electrically coupled to the first data line, and the pixel circuit unit corresponding to the light-emitting structure of another pixel color in the Nth column is electrically coupled to the (N-2)th data line. The pixel circuit unit corresponding to the light-emitting structure of one pixel color in column j5 is electrically coupled to the data line j5; the pixel circuit unit corresponding to the light-emitting structure of another pixel color in column j5 is electrically coupled to the data line j5-2; and the pixel circuit unit corresponding to the light-emitting structure of the third pixel color in column j6 is electrically coupled to the data line j6. Where j5 is an odd number greater than or equal to 3 and less than N, and j6 is an even number greater than or equal to 2 and less than N; The plurality of first pins are electrically coupled one-to-one with the plurality of fan-out lines corresponding to the plurality of data lines.

15. The display device as claimed in claim 10, wherein, The light-emitting structure in the Nth column has a third pixel color; The pixel circuit unit corresponding to the light-emitting structure of one pixel color in column j7 is electrically coupled to the data line j7; the pixel circuit unit corresponding to the light-emitting structure of another pixel color in column j7 is electrically coupled to the data line j7+2; and the pixel circuit unit corresponding to the light-emitting structure of the third pixel color in column j8 is alternately electrically coupled to the data line j8 and the data line j8+2. Where j7 is an odd number greater than or equal to 1 and less than N, and j8 is an even number greater than or equal to 2 and less than or equal to N; The first data line has a first pixel color or a second pixel color, the second data line has a third pixel color, and the plurality of second pins are configured such that when the number C of the plurality of first pins is equal to M, the fan-out line corresponding to the first data line and the fan-out line corresponding to the second data line are electrically coupled to the plurality of second pins.

16. The display device as claimed in claim 12, wherein, The display data of the Nth column of the light-emitting structure is obtained by copying the display data of the (N-4)th column of the light-emitting structure.

17. The display device as claimed in claim 1, wherein, The drive unit also includes a buffer, which is a row buffer.

Images