Chip testing device and chip testing equipment
By introducing an auxiliary control board into the chip testing device, the problem of limited chip density on plate-shaped structures is solved, achieving more efficient chip testing and cost reduction.
Patent Information
- Application Number
- CN202520045128.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-09
AI Technical Summary
In existing chip testing equipment, the density of chips fixed on plate-shaped structures is limited, resulting in reduced chip testing efficiency.
An auxiliary control board is installed on the main control board. The auxiliary control board provides control signals to the main control board and outputs the signals to the chip under test, thereby increasing the density of the assembly area on the main control board and improving the chip testing efficiency.
By increasing the assembly density of chip testing equipment, more chips can be tested in the same batch, reducing testing costs.
Smart Images
Figure CN223841961U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, specifically to a chip testing device and chip testing equipment. Background Technology
[0002] Typically, chips need to be fixed to a supporting structure before testing, such as a plate-shaped structure. To facilitate chip testing, this plate-shaped structure also needs to hold other control components, such as circuit units. This reduces the area available for chip mounting on the plate-shaped structure, decreasing the chip density. When the chip density on the plate-shaped structure is affected, chip testing efficiency is reduced. Utility Model Content
[0003] This application provides a chip testing apparatus and chip testing equipment, the main purpose of which is to improve chip testing efficiency.
[0004] According to a first aspect of this application, a chip testing apparatus is provided, comprising:
[0005] The main control board has one end face designated as the assembly surface, and the assembly surface is divided into multiple spaced assembly areas, which are used to assemble the chip under test.
[0006] An auxiliary control board, erected on the mounting surface, is configured to provide control signals to the main control board and output the control signals to the chip under test (DUT) via the main control board, causing the DUT to emit light.
[0007] The platform has a loading surface for supporting the main control board, which is located between the platform and the auxiliary control board.
[0008] In one embodiment, the emitted light from the chip under test is perpendicular to the mounting surface, and the normal vector of the auxiliary control board is perpendicular to and / or inclined to the normal vector of the main control board.
[0009] In one embodiment, the assembly surface is divided into multiple arrayed assembly areas, and an empty area is formed between adjacent assembly areas: the auxiliary control board is erected in the empty area, and / or erected on the outer periphery of the assembly surface.
[0010] In one embodiment, the auxiliary control board is erected on the outer periphery of the assembly surface, and the auxiliary control board is a tubular or hollow columnar structure formed by circumferential enclosure.
[0011] In one embodiment, the assembly surface is divided into multiple assembly areas arranged in multiple rows and columns, and the auxiliary control board is erected in the empty area between adjacent rows or columns of the assembly areas.
[0012] In one embodiment, the chip testing device includes a plurality of auxiliary control boards, wherein the plurality of auxiliary control boards are parallel to each other, and / or the plurality of auxiliary control boards are divided into two groups, wherein the auxiliary control boards in different groups are perpendicular to each other.
[0013] In one embodiment, the normal vector of the auxiliary control board is perpendicular to the normal vector of the main control board.
[0014] In one embodiment, the system further includes multiple circuit units, each of which is at least partially or entirely mounted on the auxiliary control board, and the circuit units cooperate with each other to output the control signal.
[0015] In one embodiment, when at least some of the circuit units are mounted on the auxiliary control board, the remaining circuit units are mounted in the assembly area: and / or, at least one circuit unit mounted on the auxiliary control board has a surface area greater than any circuit unit mounted in the assembly area.
[0016] According to a second aspect of this application, a chip testing device is provided, comprising a tester and the aforementioned chip testing apparatus, wherein the tester and the chip testing apparatus are electrically connected, and the tester is used to provide control signals to the auxiliary control board.
[0017] According to the chip testing apparatus in the above embodiments, an auxiliary control board is erected on the main control board. The auxiliary control board is configured to provide control signals to the main control board and output the control signals to the chip under test (DUT) through the main control board. The auxiliary control board can undertake at least part of the structure on the main control board, such as the structure controlling at least part of the DUT on the main control board. This allows for a larger area on the main control board to be divided into more assembly areas, thereby assembling more DUTs and increasing the density of DUT assembly on the main control board. This enables more chips to be tested in the same batch, improving testing efficiency and reducing chip testing costs. Furthermore, the auxiliary control board is located on the assembly surface of the main control board where the DUT is assembled; that is, the auxiliary control board and the DUT are located on the same end face of the main control board, facilitating the auxiliary control board to send control signals to the DUT on the main control board. Attached Figure Description
[0018] Figure 1 This is a three-dimensional structural diagram of a chip testing device in one embodiment of this application;
[0019] Figure 2 This is an exploded view of the chip testing device in one embodiment of this application:
[0020] Figure 3 This is a three-dimensional structural diagram of a chip testing device in one embodiment of this application;
[0021] Figure 4 This is a three-dimensional structural diagram of a chip testing device in one embodiment of this application;
[0022] Figure 5 This is a three-dimensional structural diagram of a chip testing device in one embodiment of this application;
[0023] Figure 6 This is a schematic diagram of the exploded structure of a chip testing device in one embodiment of this application;
[0024] Figure 7 This is a schematic diagram of the circuit control module of the chip testing equipment in one embodiment of this application.
[0025] Explanation of reference numerals in the attached drawings: 10. Main control board; 11. Assembly surface; 12. Assembly area; 13. Empty area; 20. Auxiliary control board; 21. Installation area; 201. Circular tube segment; 202. Conical tube segment; 30. Stage; 31. Carrying surface; 40. Chip under test; 50. Circuit unit; 51. Drive circuit unit; 52. Auxiliary circuit unit; 521. Power supply module; 522. Signal modulation module; 60. First connector; 70. Second connector. Detailed Implementation
[0026] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.
[0027] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.
[0028] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).
[0029] like Figures 1-7 As shown, one embodiment of this application provides a chip testing device, including: a main control board 10, an auxiliary control board 20, and a stage 30.
[0030] The main control board 10 has one end face designated as the assembly surface 11. The assembly surface 11 is divided into multiple spaced assembly areas 12, which are used to assemble the chip under test 40.
[0031] The auxiliary control board 20 is erected on the assembly surface 11. For example, the auxiliary control board 20 is erected and fixed to the assembly surface 11 by welding, connectors, or other means. The auxiliary control board 20 is configured to provide control signals to the main control board 10 and output the control signals to the chip under test 40 through the main control board 10. The chip under test 40 will light up after receiving the control signals from the main control board 10.
[0032] The stage 30 has a loading surface 31, which is used to support the main control board 10. The main control board 10 is located between the stage 30 and the auxiliary control board 20.
[0033] In the chip testing apparatus described in the above embodiments, an auxiliary control board 20 is erected on the main control board 10. The auxiliary control board 20 is configured to provide control signals to the main control board 10 and output the control signals to the chip under test (DUT) 40 through the main control board 10. The auxiliary control board 20 can support at least part of the structure on the main control board 10, such as the structure on the main control board 10 that controls at least part of the DUT 40. In this way, the main control board 10 can have a larger area to divide into more assembly areas 12, thereby assembling more DUT chips 40 and increasing the density of DUT chips 40 assembled on the main control board 10. This allows more chips to be tested in the same batch when testing the DUT chips 40, which improves the testing efficiency of the DUT chips 40 and reduces the chip testing cost. Furthermore, the auxiliary control board 20 is located on the mounting surface 11 of the main control board 10 where the chip under test 40 is mounted, that is, the auxiliary control board 20 and the chip under test 40 are located on the same end face of the main control board 10, which facilitates the auxiliary control board 20 to send control signals to the chip under test 40 on the main control board 10.
[0034] The emitted light from the chip under test (DUT) 40 is perpendicular to the mounting surface 21. The DUT 40 can be, for example, an LED under test, a diode under test, a VCSEL under test, or a VCSEL package module under test. The normal vector of the auxiliary control board 20 is perpendicular to or inclined to the normal vector of the main control board 10.
[0035] When the normal vector of the auxiliary control board 20 is perpendicular to the normal vector of the main control board 10, the emitted light generated by the chip under test 40 will not be blocked by the auxiliary control board 20, which helps to ensure the effectiveness of testing multiple chips under test 40 on the main control board 10. Alternatively, the mounting surface 11 on the main control board 10 can be fully utilized to divide more mounting areas 12 for mounting chips under test 40, increasing the density of mounting chips under test 40 on the main control board 10, thereby improving the testing efficiency of chips under test 40 and reducing the testing cost of chips under test 40.
[0036] When the normal vector of the auxiliary control board 20 is tilted to the normal vector of the main control board 10, if the projection of the auxiliary control board 20 along the axis of the main control board 10 will block part of the assembly surface 11, then it is necessary to avoid the blocked part of the assembly surface 11 to divide the assembly area 12. In this way, although the testing efficiency of the chip under test 40 can be improved by using the auxiliary control board 20, the maximization of testing efficiency will still be affected to some extent because the normal vector of the auxiliary control board 20 is perpendicular to the normal vector of the main control board 10.
[0037] Specifically, in this embodiment, the normal vector of the auxiliary control board 20 is perpendicular to the normal vector of the main control board 10, so as to maximize the use of the mounting surface 11 on the main control board 10 to mount more chips under test 40.
[0038] like Figures 1-5 As shown, the assembly surface 11 is divided into multiple arrayed assembly areas 12, with empty areas 13 formed between adjacent assembly areas 12. The auxiliary control board 20 is erected in the empty area 13, and / or erected on the outer periphery of the assembly surface 11.
[0039] like Figure 3 and Figure 6 As shown, in some embodiments, the auxiliary control board 20 is erected on the outer periphery of the assembly surface 11 to avoid the auxiliary control board 20 blocking the output light path of the chip 40 under test on the main control board 10.
[0040] It is understandable that, in order to make full use of the area of the assembly surface 11 on the main control panel 10, the multiple assembly areas 12 are generally distributed relatively centrally within the assembly surface 11, and the assembly surface 11 outside the assembly areas 12 corresponds to the outer periphery of the assembly surface 11.
[0041] The auxiliary control board 20 is a tubular or hollow columnar structure formed by enclosing it circumferentially. In this way, the auxiliary control board 20 is a relatively circumferentially closed structure. The multiple chips under test 40 on the main control board 10 are placed in the space enclosed by the auxiliary control board 20. The auxiliary control board 20 can act as a barrier or cover to prevent external light paths or light sources from entering the space enclosed by the auxiliary control board 20, effectively protecting the test environment or test results of the chips under test 40.
[0042] More specifically, for example, the auxiliary control panel 20 is a cylindrical tubular structure formed by enclosing it circumferentially, or, as... Figure 6 As shown, the auxiliary control plate 20 is a tubular structure with curved sidewalls formed by enclosing it circumferentially. For example, the auxiliary control plate 20 can also be a hollow quadrangular prism structure formed by enclosing it circumferentially. Another example is... Figure 3 As shown, the auxiliary control board 20 includes an axially connected circular tube segment 201 and a tapered tube segment 202. The two ends of the circular tube segment 201 are connected to the main control board 10 and the tapered tube segment 202, respectively. The normal vector of the auxiliary control board 20 at the circular tube segment 201 is perpendicular to the normal vector of the main control board 10, while the normal vector of the auxiliary control board 20 at the tapered tube segment 202 is inclined to the normal vector of the main control board 10. From the side closer to the main control board 10 to the side farther away, the radial dimension of the tapered tube segment 202 continuously increases. The tapered tube segment 202 can provide a larger area to support some structures on the main control board 10, such as control structures on the main control board 10 other than the chip under test 40, thereby increasing the density of the chip under test 40 mounted on the main control board 10.
[0043] In other embodiments, the auxiliary control board 20 may also be a non-closed structure. For example, according to the need of the assembly area, a plurality of auxiliary control boards 20 are provided on the outer peripheral side of the local assembly surface 11.
[0044] As Figures 4-5 shown, in some embodiments of the present application, a plurality of assembly areas 12 arranged in multiple rows and multiple columns are defined on the assembly surface 11. The auxiliary control board 20 is erected at the vacant area 13 between adjacent rows or adjacent columns of the assembly areas 12. At this time, correspondingly, the length of the auxiliary control board 20 is consistent with or corresponds to the total length formed by a plurality of assembly areas 12 on adjacent rows or adjacent columns, so as to increase the effective area of the auxiliary control board 20.
[0045] The chip testing device includes a plurality of auxiliary control boards 20. Among them, the plurality of auxiliary control boards 20 are all parallel to each other, and / or the plurality of auxiliary control boards 20 are divided into two groups, and the auxiliary control boards 20 in different groups are perpendicular to each other.
[0046] Specifically, for example, as Figure 4 shown, two parallel auxiliary control boards 20 are provided. The two auxiliary control boards 20 are relatively centered and distributed within the area surrounded by the plurality of assembly areas 12, so as to facilitate the electrical connection between the relevant control structures on the auxiliary control board 20 and the chips 40 to be tested on the plurality of assembly areas 12 on both sides. The height of the plurality of parallel auxiliary control boards 20 along the axial direction of the main control board 10 can be selected according to needs. When there are more relevant control structures assembled on the auxiliary control board 20, the assembly area of the auxiliary control board 20 can be increased by increasing the height.
[0047] Specifically, it can also be, for example Figure 5 shown, two auxiliary control boards 20 are provided. The two auxiliary control boards 20 are divided into two groups. The two or two groups of auxiliary control boards 20 are perpendicularly connected to form a T-shaped structure. Or, three auxiliary control boards 20 can be provided. One group includes two parallel auxiliary control boards 20, and the other group includes one auxiliary control board 20. The two groups of auxiliary control boards 20 are perpendicular to each other, and can form a cross-shaped or earth-shaped structure. Or, two groups of multiple perpendicular auxiliary control boards 20 can be provided to form structures such as a grid-shaped, king-shaped, square-shaped, or product-shaped structure. Here, it is not enumerated, and specific selection is made according to actual needs flexibly.
[0048] The auxiliary control boards 20 in different groups can be connected by welding. When the auxiliary control boards 20 in different groups are perpendicular to each other, the connection strength or connection stability between different auxiliary control boards 20 can also be increased.
[0049] In other embodiments, the assembly surface 11 may be divided into multiple arrayed assembly areas 12, with empty areas 13 formed between adjacent assembly areas 12. Multiple auxiliary control boards 20 are provided, with at least one auxiliary control board 20 erected in the empty area 13 and at least one auxiliary control board 20 erected on the outer periphery of the assembly surface 11. The auxiliary control boards 20 in the empty area 13 and the auxiliary control boards 20 on the outer periphery of the assembly surface 11 may be spaced apart or connected.
[0050] In the embodiments of this application, the chip testing equipment further includes a plurality of circuit units 50, each circuit unit 50 being at least partially or entirely mounted on the auxiliary control board 20, and each circuit unit 50 cooperating with each other to output control signals.
[0051] When at least some of the circuit units 50 are mounted on the auxiliary control board 20, the remaining circuit units 50 are mounted in the assembly area 12, and / or, at least one circuit unit 50 mounted on the auxiliary control board 20 has a surface area greater than any circuit unit 50 mounted in the assembly area 12.
[0052] Specifically, such as Figure 7 As shown, the control structure corresponding to the chip under test 40 is also known as the circuit unit 50. The circuit unit 50 includes a driving circuit unit 51 and an auxiliary circuit unit 52 that are electrically connected. The driving circuit unit 51 is electrically connected to the chip under test 40. The auxiliary circuit unit 52 includes a power supply module 521 and a signal modulation module 522. The power supply module 521 provides an electrical signal to the driving circuit unit 51, and the signal modulation module 522 provides a modulated driving signal to the driving circuit unit 51. The driving circuit unit 51 converts the signal sent by the auxiliary circuit unit 52 into a high-current short-pulse signal to drive the chip under test 40 to emit light.
[0053] The stage 30 is designed to provide a high and low temperature testing environment. This allows the chip testing device to perform high-current, short-pulse high and low temperature testing on the chip under test 40. High-current, short-pulse high and low temperature testing of VCSELs is a crucial indicator for characterizing high-current VCSELs and is in high demand in fields such as security, logistics, automotive, LiDAR, and 3D sensing. Currently, high-current VCSELs still face significant challenges in short-pulse high and low temperature testing, primarily due to the difficulty in achieving low-cost testing simultaneously under high current, short pulse, and high and low temperature conditions. When the chip under test 40 is a VCSEL or a VCSEL package module, the chip testing device designed in this application can effectively reduce the cost of high-current, short-pulse high and low temperature testing of VCSELs.
[0054] The chip testing device also includes a first connector 60 and a second connector 70. The first connector 60 is electrically connected to the drive circuit unit 51 and the auxiliary circuit unit 52, respectively. The auxiliary control board 20 is equipped with a communication interface. The auxiliary circuit unit 52 is electrically connected to the second connector 70 through the communication interface. The second connector 70 is also used for electrical connection with an external tester. Electrical signals, drive signals, and test signals from the tester can be sent to the auxiliary circuit unit 52 through the second connector 70. After processing, the auxiliary circuit unit 52 transmits the signals back to the drive circuit unit 51 through the first connector 60. The test signal, for example, is a test signal with a current greater than 10A and a pulse width in the nanosecond range. The electrical signals, drive signals, and test signals mentioned above correspond to the control signals mentioned earlier. Depending on the test conditions, the control signals may include other signals or omit some signals.
[0055] Specifically, the circuit unit 50 and the chip under test 40 are configured in a one-to-one correspondence. The auxiliary control board 20 is divided into multiple mounting areas 21. The drive circuit unit 51 and auxiliary circuit unit 52 in the circuit unit 50 are both mounted in the mounting areas 21. The mounting areas 21 are configured in a one-to-one correspondence with the circuit unit 50 or in a one-to-many configuration. When both the drive circuit unit 51 and auxiliary circuit unit 52 in the circuit unit 50 are mounted in the mounting areas 21, the assembly area 12 only needs to assemble the chip under test 40, effectively reducing the area of the assembly area 12 on the main control board 10. This allows the main control board 10 to be divided into more assembly areas 12, thereby assembling more chips under test 40. In other embodiments, the circuit units 50 on the auxiliary control board 20 can be flexibly increased, decreased, or rearranged according to actual conditions. For example, all the auxiliary circuit units 52 in the circuit unit 50 can be mounted in the mounting area 21 of the auxiliary control board 20, and all the drive circuit units 51 in the circuit unit 50 can be assembled in the assembly area 12 of the main control board 10.
[0056] The chip testing device described in the above embodiments, through the auxiliary control board 20, effectively increases the density of the chips under test 40 that can be mounted on the main control board 10, facilitating automated testing of multiple chips under test 40 at once, improving testing efficiency, and reducing testing costs. The chip testing device is simple in structure, easy to implement, highly feasible, and quick to deploy, possessing good testing versatility, stability, and mass production capability.
[0057] Another embodiment of this application provides a chip testing device, including a tester and the aforementioned chip testing apparatus. The tester and the chip testing apparatus are electrically connected. The tester is used to provide control signals to an auxiliary control board 20, such as sending electrical signals, test signals, and drive signals for testing to the auxiliary control board 20. The chip testing device includes the chip testing apparatus described in the above embodiment, and therefore also possesses the advantages of the aforementioned chip testing apparatus, which will not be elaborated further here.
[0058] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.
Claims
1. A chip testing device, characterized in that, include: The main control board has one end face designated as the assembly surface, and the assembly surface is divided into multiple spaced assembly areas, which are used to assemble the chip under test. An auxiliary control board is erected on the assembly surface. The auxiliary control board is configured to provide control signals to the main control board and output the control signals to the chip under test through the main control board so that the chip under test emits light. as well as The platform has a loading surface for supporting the main control board, which is located between the platform and the auxiliary control board.
2. The chip testing apparatus as described in claim 1, characterized in that, The emitted light from the chip under test is perpendicular to the assembly surface, and the normal vector of the auxiliary control board is perpendicular to and / or inclined to the normal vector of the main control board.
3. The chip testing apparatus as described in claim 2, characterized in that, The assembly surface is divided into multiple arrayed assembly areas, with empty areas formed between adjacent assembly areas; the auxiliary control board is erected in the empty area and / or erected on the outer periphery of the assembly surface.
4. The chip testing apparatus as described in claim 3, characterized in that, The auxiliary control board is erected on the outer periphery of the assembly surface, and the auxiliary control board is a tubular or hollow columnar structure formed by enclosing it circumferentially.
5. The chip testing apparatus as described in claim 3, characterized in that, The assembly surface is divided into multiple assembly areas arranged in multiple rows and columns, and the auxiliary control board is erected in the empty area between adjacent rows or columns of the assembly areas.
6. The chip testing apparatus as described in claim 5, characterized in that, The chip testing device includes multiple auxiliary control boards, wherein the multiple auxiliary control boards are parallel to each other, and / or the multiple auxiliary control boards are divided into two groups, and the auxiliary control boards in different groups are perpendicular to each other.
7. The chip testing apparatus as described in any one of claims 3 to 6, characterized in that, The normal vector of the auxiliary control board is perpendicular to the normal vector of the main control board.
8. The chip testing apparatus as described in claim 1, characterized in that, It also includes multiple circuit units, each of which is at least partially or entirely mounted on the auxiliary control board, and each of the circuit units cooperates with each other to output the control signal.
9. The chip testing apparatus as described in claim 8, characterized in that, When at least some of the circuit units are mounted on the auxiliary control board, the remaining circuit units are mounted in the assembly area; and / or, at least one circuit unit mounted on the auxiliary control board has a surface area greater than any circuit unit mounted in the assembly area.
10. A chip testing device, characterized in that, The device includes a tester and a chip testing apparatus as described in any one of claims 1 to 9, wherein the tester and the chip testing apparatus are electrically connected, and the tester is used to provide control signals to the auxiliary control board.