ADC test system
By designing the digital signal and interface driver adapter board as a separate circuit board and connecting it with the ADC core board and FPGA development board, the problems of low module reuse and complex design in traditional ADC test systems are solved, achieving higher reuse rate and reduced cost.
Patent Information
- Application Number
- CN202423265054.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2034-12-30
AI Technical Summary
Traditional ADC test systems have low module reuse rates and complex designs, leading to increased costs.
The digital signal and interface driver adapter board is separated from the ADC core board. It is connected to the ADC core board through the adapter board's FPC interface unit and to the FPGA development board through the adapter board's FMC interface unit, thus enabling the reuse of the module.
This improves the reusability of the ADC core board and reduces design complexity and cost.
Smart Images
Figure CN223842067U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of analog-to-digital converter technology, and in particular to an ADC testing system. Background Technology
[0002] An analog-to-digital converter (ADC) converts analog electrical signals output from a sensor into discrete digital signals.
[0003] Before an ADC chip product is put into use, its performance needs to be evaluated and calibrated. This requires an ADC performance testing and evaluation platform to comprehensively evaluate various aspects of the ADC's performance. ADC performance includes static and dynamic performance. Static performance includes offset, gain error, differential nonlinearity (DNL), and integral nonlinearity (INL); dynamic performance includes signal-to-noise ratio (SNR), total harmonic distortion (THD), spurious-free dynamic range (SFDR), and signal-to-noise distortion ratio (SINAD).
[0004] Traditional ADC testing systems, such as Figure 1 As shown, the system includes an ADC core board, an FPGA development board, and a PC host computer. A high-precision signal source generates an analog signal, which is input to the ADC core board. The ADC core board converts the analog signal into a digital signal, which is then driven by a driver and output directly to the FPGA development board via the FMC interface. The FPGA development board then encapsulates the data and transmits it transparently to the PC host computer for data processing and analysis.
[0005] However, traditional ADC testing systems have the following shortcomings: on the one hand, the ADC core board of the system is designed to be very complex, such as complex digital signal driver circuits; on the other hand, there are relatively few common modules for testing different ADC chips, which greatly increases the cost. Utility Model Content
[0006] The technical problem this invention aims to solve is how to address the low module reuse rate and complexity of traditional ADC testing systems.
[0007] To address the aforementioned technical problems, this utility model provides an ADC testing system, comprising a signal source, an ADC core board, a digital signal and interface driver adapter board, an FPGA development board, and a PC host computer, wherein:
[0008] The signal input terminal of the ADC core board is connected to the signal output terminal of the signal source to convert the analog signal output by the signal source into a digital signal.
[0009] The input terminal of the digital signal and interface driver adapter board is connected to the output terminal of the ADC core board for impedance transformation of the digital signal.
[0010] The input terminal of the FPGA development board is connected to the output terminal of the digital signal and interface driver adapter board; the output terminal of the FPGA development board is connected to the PC host computer for communication.
[0011] Furthermore, the digital signal and interface driver adapter board includes an adapter board FPC interface unit, a digital signal driving unit, and an adapter board FMC interface unit, wherein:
[0012] The input terminal of the digital signal and interface driver adapter board is connected to the output terminal of the ADC core board via the FPC interface unit of the adapter board through a flexible flat cable.
[0013] The output of the digital signal and interface driver adapter board is connected to the input of the FPGA development board via the FMC interface unit of the adapter board.
[0014] Furthermore, the ADC core board includes an ADC chip, a power management unit, a reference voltage unit, and a clock management unit, wherein:
[0015] The power management unit includes a buck converter, which is used to convert an externally input 12V voltage into a 5V voltage to power the ADC chip.
[0016] The reference voltage unit includes a reference voltage generation circuit and a reference voltage driving circuit, which are used to provide a stable reference voltage for the core board (10);
[0017] The clock management unit is used to perform impedance transformation on the externally input clock signal to provide a frequency-stable sampling clock for the ADC chip;
[0018] The ADC chip includes an FPC flexible flat cable interface, which is connected to the digital signal and interface driver adapter board via a flexible flat cable.
[0019] Furthermore, the FPGA development board includes an FPGA power management unit, a development board FMC interface unit, an FPGA unit, an RJ45 interface unit, and a USB unit, wherein:
[0020] The FPGA power management unit is used to convert the externally input DC power into 3.3V and 1.8V power voltages to power the FPGA chip, and output 12V DC power to the FMC interface unit of the development board.
[0021] The development board FMC interface unit is connected to the adapter board FMC interface unit, and is used to supply 12V DC power to the digital signal and interface driver adapter board, while transmitting the digital signals of the digital signal and interface driver adapter board to the FPGA unit, and sending the digital signals and sampling clock signals output by the FPGA unit to the digital signal and interface driver adapter board through the development board FMC interface unit.
[0022] The FPGA unit is used to package the received digital signals and send them to the PC host computer through the RJ45 interface unit.
[0023] Furthermore, the output terminal of the PC host computer outputs discrete time-domain digital signals.
[0024] Compared with the prior art, the present invention has the following beneficial effects:
[0025] This invention designs a digital signal and interface driver adapter board with high utilization and cost as a separate circuit board, and connects the circuits through its adapter board FPC interface unit using a flexible flat cable, and directly connects through its adapter board FMC interface unit. When evaluating different ADC performance, the digital signal and interface driver adapter board can be reused, and only the ADC core board needs to be redesigned. This solves the defects of low reuse rate and complex design of traditional ADC core boards that integrate digital signal and interface driver adapter boards. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of a traditional ADC testing system;
[0027] Figure 2 This is a schematic diagram of the ADC testing system disclosed in an embodiment of the present invention;
[0028] Figure 3 This is a schematic block diagram of the ADC core board in the ADC testing system disclosed in this utility model embodiment;
[0029] Figure 4 This is a schematic block diagram of the digital signal and interface driver adapter board in the ADC testing system disclosed in this utility model embodiment;
[0030] Figure 5 This is a schematic block diagram of the FPGA development board in the ADC testing system disclosed in this embodiment of the utility model;
[0031] Figure 6 This is a schematic diagram of data processing on the PC host computer in the ADC testing system disclosed in this embodiment of the utility model.
[0032] In the picture:
[0033] 00. Signal source;
[0034] 10. ADC core board; 20. Digital signal and interface driver adapter board; 30. FPGA development board; 40. PC host computer. Detailed Implementation
[0035] To make the technical solutions and effects of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.
[0036] In traditional ADC testing systems, on the one hand, due to the influence of designers' fixed mindset, the digital signal and interface driver adapter board and the ADC core board are designed as a single circuit board integrated together, which makes the existing ADC core board very complex; and the ADC core board needs to be redesigned when testing different ADC chips, which leads to a very low reuse rate of the ADC core board; on the other hand, separating the digital signal and interface driver adapter board requires overcoming a series of technical obstacles, such as signal integrity and electromagnetic compatibility (EMC).
[0037] The present invention aims to provide an ADC testing system that separates the digital signal and interface driver adapter board from the ADC core board, thereby solving the problems of complex ADC core board design and low reusability in traditional ADC testing systems.
[0038] Please see Figure 2 The ADC testing system provided by this utility model mainly includes: a signal source 00, an ADC core board 10, a digital signal and interface driver adapter board 20, an FPGA development board 30, and a PC host computer 40.
[0039] Signal source 00 is used to generate a sine wave signal to evaluate the performance of the ADC.
[0040] The ADC core board 10 is used to convert the analog signal generated by the signal source 00 into a digital signal.
[0041] The digital signal and interface driver adapter board 20 is connected to the ADC core board 10 and is used for impedance transformation of digital signals.
[0042] The FPGA development board 30 is connected to the digital signal and interface driver adapter board 20.
[0043] The FPGA development board 30 packages and forwards the received digital signals to the PC host computer 40, which then processes and analyzes the ADC output data.
[0044] In a further embodiment:
[0045] The signal input terminal of the ADC core board 10 is connected to the signal output terminal of the signal source 00 to convert the analog signal output by the signal source 00 into a digital signal.
[0046] The input terminal of the digital signal and interface driver adapter board 20 is connected to the output terminal of the ADC core board 10 for impedance transformation of digital signals.
[0047] The input terminal of the FPGA development board 30 is connected to the output terminal of the digital signal and interface driver adapter board 20; the output terminal of the FPGA development board 30 is connected to the PC host computer 40 for communication.
[0048] The following is a main description of each module in the ADC test system provided in this example:
[0049] First, the ADC core board 10 in this embodiment will be described.
[0050] Please see Figure 3 The ADC core board 10 includes an ADC chip, a power management unit, a reference voltage unit, and a clock management unit.
[0051] The power management unit includes a buck converter, which converts an externally input 12V voltage into a 5V voltage to power the ADC chip.
[0052] Among them, the buck converter can be a synchronous buck chip such as AH8642 or MP2225. This synchronous buck chip usually adopts pulse width modulation (PWM) control mode, and realizes voltage conversion by adjusting the switching state of MOSFET. It is a conventional technical means in this field and will not be described in detail here.
[0053] The reference voltage unit includes a reference voltage generation circuit and a reference voltage driving circuit, which are used to provide a stable reference voltage for the core board 10.
[0054] The clock management unit is used to perform impedance transformation on the externally input clock signal to provide a frequency-stable sampling clock for the ADC chip.
[0055] The clock management unit includes a phase-locked loop, a mixed-mode clock manager, a clock driver, a clock buffer, and filters.
[0056] The ADC chip includes an FPC flexible flat cable interface, which is connected to the digital signal and interface driver adapter board 20 via a flexible flat cable.
[0057] The design principle of the ADC core board 10 is as follows: The power management unit converts the externally input 12V voltage into a 5V voltage to power the ADC chip, and a linear power supply design is adopted for lower noise. The reference voltage unit includes a reference voltage generation and reference voltage driving circuit to provide a stable and low-noise reference voltage for the ADC. The clock management unit performs impedance transformation on the externally input clock signal to enhance the driving capability and provide a frequency-stable sampling clock for the ADC chip. The ADC chip converts the sinusoidal analog voltage signal from the high-precision signal source into a digital signal, sends it to the FPC flexible flat cable interface, and then connects to the digital signal and interface driver adapter board 20 via a flexible flat cable.
[0058] Next, the digital signal and interface driver adapter board 20 in this embodiment will be described.
[0059] Please see Figure 4 The digital signal and interface driver adapter board 20 includes an adapter board FPC interface unit, a digital signal driver unit, and an adapter board FMC interface unit.
[0060] The input terminal of the digital signal and interface driver adapter board 20 is connected to the output terminal of the ADC core board 10 via a flexible flat cable through the adapter board FPC interface unit.
[0061] The output of the digital signal and interface driver adapter board 20 is connected to the input of the FPGA development board 30 via the adapter board's FMC interface unit.
[0062] The design principle of the digital signal and interface driver adapter board 20 is as follows: The adapter board FPC interface unit is connected to the ADC core board 10 via a flexible flat cable, providing the ADC core board 10 with a 12V power supply and clock signal, as well as outputting digital signals to control the operating mode of the ADC core board 10 and receiving the input after the ADC chip converts the input analog signal into a digital signal. The digital signal driver unit contains a digital signal impedance transformation circuit, which amplifies the driving capability of the signal output from the ADC chip or the FPGA output with weak driving capability, enabling it to drive larger loads, such as larger capacitors and smaller resistors, and also making the rising and falling edges of the digital signal steeper. The adapter board FMC interface unit sends the digital signal with strong driving capability output from the digital signal driver unit to the FPGA development board 30, and also sends the digital signal with weak driving capability input from the FPGA development board 30 to the digital signal driver unit for driving capability amplification, including the clock signal input from the FPGA development board 30. The 12V power supply input from the FPGA development board 30 powers the driver chip on the digital signal and interface driver adapter board 20, and also connects the 12V power supply to the FPC interface unit of the adapter board through the adapter board FPC interface unit, and transmits the 12V power supply to the ADC core board 10 through the flexible flat cable.
[0063] When evaluating the performance of different ADCs, the digital signal and interface driver adapter board 20 can be reused. Only the ADC core board 10 in this embodiment needs to be redesigned, which reduces the design complexity of the ADC core board 10 and makes the digital signal and interface driver adapter board 20 in this embodiment have a high reuse rate.
[0064] Next, the FPGA development board 30 in this embodiment will be described.
[0065] The FPGA development board 30 includes an FPGA power management unit, a development board FMC interface unit, an FPGA unit, an RJ45 interface unit, and a USB unit.
[0066] The FPGA power management unit is used to convert the external DC power input into 3.3V and 1.8V power supply voltages to power the FPGA chip, and output 12V DC power to the FMC interface unit of the development board.
[0067] The development board FMC interface unit is connected to the adapter board FMC interface unit to supply 12V DC power to the digital signal and interface driver adapter board 20, while transmitting the digital signals of the digital signal and interface driver adapter board 20 to the FPGA unit, and sending the digital signals and sampling clock signals output by the FPGA unit to the digital signal and interface driver adapter board 20 through the development board FMC interface unit.
[0068] The FPGA unit is used to package and process the received digital signals and send them to the PC host computer 40 through the RJ45 interface unit.
[0069] The design principle of FPGA development board 30 is as follows: The FPGA power management unit converts the externally input DC power supply into 3.3V and 1.8V power voltages to power the FPGA chip. It also outputs 12V DC power to the development board's FMC interface unit. The development board's FMC interface unit is connected to the adapter board FMC interface unit of the digital signal and interface driver adapter board 20, supplying 12V power to the adapter board 20 and transmitting the digital signals from the adapter board 20 to the FPGA system. Simultaneously, it sends the FPGA's output digital signals and sampling clock signals to the adapter board 20 via the development board's FMC interface unit. The FPGA system packages the received digital signals and sends them to the PC host computer 40 via the Ethernet protocol RJ45 interface unit. Simultaneously, FPGA program download and system status monitoring are achieved through a serial port connected to the USB unit, converting the signals into USB signals for communication with the PC host computer 40.
[0070] Finally, the PC host computer 40 in this embodiment will be described.
[0071] The PC host computer 40 outputs discrete time-domain digital signals at its output terminals.
[0072] Please see Figure 6 The PC host computer 40 analyzes the signal received from the FPGA development board 30 and outputs a discrete time-domain digital signal; then, it performs a fast Fourier transform on the discrete signal to evaluate dynamic performance such as signal-to-noise ratio and total harmonic distortion; and it performs statistical analysis on the discrete signal to evaluate static performance such as differential nonlinearity, integral nonlinearity, and misalignment.
[0073] It should be noted that the PC host computer 40 processes and analyzes the ADC output data to evaluate the static and dynamic performance of the ADC. This is a conventional technical method in this field and will not be elaborated here.
[0074] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. An ADC testing system, characterized in that, It includes a signal source (00), an ADC core board (10), a digital signal and interface driver adapter board (20), an FPGA development board (30), and a PC host computer (40), wherein: The signal input terminal of the ADC core board (10) is connected to the signal output terminal of the signal source (00) to convert the analog signal output by the signal source (00) into a digital signal. The input terminal of the digital signal and interface driver adapter board (20) is connected to the output terminal of the ADC core board (10) for impedance transformation of the digital signal; The input terminal of the FPGA development board (30) is connected to the output terminal of the digital signal and interface driver adapter board (20); the output terminal of the FPGA development board (30) is connected to the PC host computer (40) for communication.
2. The ADC testing system according to claim 1, characterized in that, The digital signal and interface driver adapter board (20) includes an adapter board FPC interface unit, a digital signal driver unit, and an adapter board FMC interface unit, wherein: The input terminal of the digital signal and interface driver adapter board (20) is connected to the output terminal of the ADC core board (10) via the adapter board FPC interface unit through a flexible flat cable; The output of the digital signal and interface driver adapter board (20) is connected to the input of the FPGA development board (30) via the FMC interface unit of the adapter board.
3. The ADC testing system according to claim 1, characterized in that, The ADC core board (10) includes an ADC chip, a power management unit, a reference voltage unit, and a clock management unit, wherein: The power management unit includes a buck converter, which is used to convert an externally input 12V voltage into a 5V voltage to power the ADC chip. The reference voltage unit includes a reference voltage generation circuit and a reference voltage driving circuit, which are used to provide a stable reference voltage for the core board (10); The clock management unit is used to perform impedance transformation on the externally input clock signal to provide a frequency-stable sampling clock for the ADC chip; The ADC chip includes an FPC flexible flat cable interface, which is connected to the digital signal and interface driver adapter board (20) via a flexible flat cable.
4. The ADC testing system according to claim 2, characterized in that, The FPGA development board (30) includes an FPGA power management unit, a development board FMC interface unit, an FPGA unit, an RJ45 interface unit, and a USB unit, wherein: The FPGA power management unit is used to convert the externally input DC power into 3.3V and 1.8V power voltages to power the FPGA chip, and output 12V DC power to the FMC interface unit of the development board. The development board FMC interface unit is connected to the adapter board FMC interface unit to deliver 12V DC power to the digital signal and interface driver adapter board (20), and simultaneously transmit the digital signals of the digital signal and interface driver adapter board (20) to the FPGA unit, and send the digital signals and sampling clock signals output by the FPGA unit to the digital signal and interface driver adapter board (20) through the development board FMC interface unit. The FPGA unit is used to package the received digital signals and send them to the PC host computer (40) through the RJ45 interface unit.
5. The ADC testing system according to claim 1, characterized in that, The output terminal of the PC host computer (40) outputs discrete time-domain digital signals.