Simple semiconductor ATE packaging test mechanism

Abstract

The utility model provides a simple semiconductor ATE packaging test mechanism, which comprises a test seat assembly, the test seat assembly comprises a lower needle die, a lower cover configured at the upper end of the lower needle die and a floating plate adapted in a connecting and guiding port at the middle part of the lower cover, and the middle part of the lower needle die is uniformly exposed and provided with a plurality of lower needle pins. The floating plate is provided with a substrate packaging layer and a packaging expansion layer arranged on the upper end face of the substrate packaging layer, a packaging groove is formed in the middle of the substrate packaging layer, pin holes matched with the lower pin pins are evenly formed in the packaging groove, positioning arcs are arranged at the four corners of the packaging groove, and the packaging expansion layer is arranged on the upper end face of the substrate packaging layer. The front and rear ends are symmetrically provided with first adaptive grooves, and the left and right ends of the packaging expansion layer are provided with second adaptive grooves. The utility model relates to the technical field of semiconductor testing.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor testing technology, and in particular to a simple semiconductor ATE packaging testing mechanism. Background Technology

[0002] In the semiconductor industry, ensuring chip quality is a crucial step, a process that relies on ATE (Automatic Test Equipment) packaging and testing modules. Existing ATE modules typically require professional operation and maintenance, increasing initial investment costs and complicating daily operations. Furthermore, these traditional testing modules are often inflexible in design, struggling to adapt to the testing needs of various package types, especially when frequent chip replacements are required. This deficiency is particularly pronounced when probes wear or are damaged, making replacement both complex and time-consuming, further increasing downtime and maintenance costs.

[0003] Therefore, it is imperative to redesign a simple semiconductor ATE packaging and testing mechanism. Utility Model Content

[0004] To address the shortcomings of the existing technology, this utility model provides a simplified semiconductor ATE packaging and testing mechanism, aiming to solve the problems of complex operation, high maintenance costs, and difficulty in adapting to the testing needs of various packaged chip types in the existing ATE packaging and testing modules.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows: a simple semiconductor ATE packaging and testing mechanism, including a test socket assembly. The test socket assembly includes a lower pin mold, a lower cover disposed on the upper end of the lower pin mold, and a floating plate adapted to the interface in the middle of the lower cover. A plurality of lower pin pins are uniformly exposed in the middle of the lower pin mold. The floating plate is provided with a substrate encapsulation layer and an encapsulation extension layer disposed on the upper surface of the substrate encapsulation layer. An encapsulation groove is provided in the middle of the substrate encapsulation layer. Pin holes adapted to the plurality of lower pin pins are uniformly disposed in the encapsulation groove. Positioning arcs are provided at the four corners of the encapsulation groove. First adapter grooves are symmetrically provided at the front and rear ends. Second adapter grooves are provided at the left and right ends of the encapsulation extension layer.

[0006] Based on the above, the advantages of a simplified semiconductor ATE packaging and testing mechanism are that it solves the problems of complex operation, high maintenance costs, and difficulty in adapting to the testing needs of various packaged chip types in existing ATE packaging and testing modules; mainly reflected in:

[0007] 1. This utility model adopts a floating plate and lower pin mold design, which makes the replacement of the lower pin pin simple and quick. When the probe is worn or damaged, the user can quickly replace it by removing the lower pin mold, reducing downtime and maintenance costs, and reducing the need for professional personnel.

[0008] 2. This utility model also provides a packaging slot, a first adapter slot and a second adapter slot in the substrate packaging layer and the packaging extension layer, so that the floating board can support the testing of various chip packaging forms including BGA, QFN, LGA, QFP and SOP. This improves the flexibility and applicability of the testing mechanism and meets the chip testing needs of different packaging types.

[0009] 3. This utility model also features an upper cover hinged to a lower cover and a chip packaged on a floating plate pressed together by a chip pressing block, which greatly reduces the complexity of operation.

[0010] Furthermore, the rear end of the lower cover is hinged to an upper cover. The upper cover has a pressure block groove on one side near the lower cover. The middle of the pressure block groove has a pressure block height fine adjustment port. The four corners of the pressure block groove have pin holes. A chip pressure block is disposed in the pressure block groove. The adjusting protrusion of the chip pressure block is slidably connected to the pressure block height fine adjustment port. The two sides of the chip pressure block are elastically connected to the two sides of the pressure block groove by springs. The height of the chip pressure block is adjusted by the matching of the pins with the pin holes.

[0011] Based on the above, the beneficial effect of hinged upper cover to the rear end of lower cover is that it makes opening and closing the test mechanism very convenient, allowing users to complete the opening and closing action with one hand, thus improving work efficiency; the beneficial effect of adjusting the bump is that it slides within the height adjustment port of the pressure block, and with the elasticity of the spring, the pressure applied to the chip under test can be finely adjusted. This not only ensures that the chip is firmly fixed in the correct position, but also prevents chip damage due to excessive pressure. At the same time, the height of the chip pressure block can be adjusted by the cooperation of the pin and the pin hole, so that the test mechanism can adapt to chip packages of various thicknesses.

[0012] Furthermore, floating plate positioning blocks are provided at the four corners of the top side of the interface, the four corners of the substrate encapsulation layer are adapted to the four corners of the bottom of the interface, and the four chamfers of the encapsulation extension layer are adapted to the surface of the floating plate positioning blocks.

[0013] Based on the above, by setting floating plate positioning blocks at the top four corners inside the connector, and ensuring that the four corners of the substrate encapsulation layer are adapted to the bottom inside the connector, the beneficial effect is that the floating plate can be accurately placed in the predetermined position, improving the consistency of the contact points between the chip and the lower pin mold during the test, thereby ensuring the accuracy of the test results.

[0014] Furthermore, the front end of the lower cover is provided with a female buckle, and the front end of the upper cover is provided with a male buckle. When the upper cover is pressed against the lower cover along the hinge, the male buckle engages with the female buckle.

[0015] Based on the above, the beneficial effects of the snap-fit ​​between the male and female parts are to ensure a firm connection between them, prevent the top cover from opening accidentally during the test, and ensure that the internal chip is stably fixed in the test position, thereby improving the safety and reliability of the test.

[0016] Furthermore, the lower needle mold is electrically connected to an external testing device.

[0017] Furthermore, the floating board is suitable for chip packaging testing of BGA, QFN, LGA, QFP, and SOP.

[0018] To more clearly illustrate the above-mentioned features of this utility model and the objectives it aims to achieve, the following description, in conjunction with the accompanying drawings and specific embodiments, will further explain this utility model. Attached Figure Description

[0019] Figure 1 This is a three-dimensional schematic diagram of the present invention;

[0020] Figure 2 This is a schematic diagram of the opening of the lid of this utility model;

[0021] Figure 3 This is a three-dimensional schematic diagram of the top cover of this utility model;

[0022] Figure 4 This is a schematic diagram of the pressing groove of this utility model;

[0023] Figure 5 This is a schematic diagram of the test seat assembly of this utility model;

[0024] Figure 6 This is a three-dimensional schematic diagram of the lower cover of this utility model;

[0025] Figure 7 This is a schematic diagram showing the cooperation between the floating plate and the lower needle mold of this utility model;

[0026] Figure 8 This is a schematic diagram of the lower needle mold of this utility model.

[0027] Reference numerals: 1-Top cover, 11-Pressure block groove, 111-Pin opening, 12-Pressure block height fine adjustment opening, 13-Male snap fastener, 2-Test socket assembly, 21-Lower pin mold, 211-Lower pin lead, 22-Lower cover, 221-Connection port, 2211-Floating plate positioning block, 222-Female snap fastener, 23-Floating plate, 231-Substrate encapsulation layer, 232-Encapsulation extension layer, 2321-Second adapter groove, 233-Encapsulation groove, 2331-Pin hole, 2332-Positioning arc, 2333-First adapter groove, 3-Chip pressure block, 31-Adjustment protrusion, 32-Spring, 33-Pin. Detailed Implementation

[0028] like Figures 1-8 As shown, a simple semiconductor ATE packaging and testing mechanism includes a test socket assembly 2. The test socket assembly 2 includes a lower pin mold 21, a lower cover 22 disposed on the upper end of the lower pin mold 21, and a floating plate 23 adapted to the interface 221 in the middle of the lower cover 22. A plurality of pins 211 are uniformly exposed in the middle of the lower pin mold 21. The floating plate 23 is provided with a substrate encapsulation layer 231 and an encapsulation extension layer 232 disposed on the upper surface of the substrate encapsulation layer 231. An encapsulation groove 233 is provided in the middle of the substrate encapsulation layer 231. Pin holes 2331 adapted to the plurality of pins 211 are uniformly disposed in the encapsulation groove 233. Positioning arcs 2332 are provided at the four corners of the encapsulation groove 233, and first adapter grooves 2333 are symmetrically provided at the front and rear ends. Second adapter grooves 2321 are provided at the left and right ends of the encapsulation extension layer 232.

[0029] The lower cover 22 is hinged to the upper cover 1 at its rear end. The upper cover 1 has a pressure block groove 11 on one side near the lower cover 22. The pressure block groove 11 has a pressure block height fine adjustment port 12 in the middle. The four corners of the pressure block groove 11 have pin holes 111. A chip pressure block 3 is disposed in the pressure block groove 11. The adjusting protrusion 31 of the chip pressure block 3 is slidably connected to the pressure block height fine adjustment port 12. The two sides of the chip pressure block 3 are elastically connected to the two sides of the pressure block groove 11 by springs 32. The height of the chip pressure block 3 is adjusted by the matching of the pins 33 and the pin holes 111.

[0030] Each of the four corners of the top side of the connector 221 is provided with a floating plate positioning block 2211. The four corners of the substrate encapsulation layer 231 are adapted to the four corners of the bottom of the connector 221. The four chamfers of the encapsulation extension layer 232 are adapted to the surface of the floating plate positioning block 2211.

[0031] The lower cover 22 has a female buckle 222 at its front end, and the upper cover 1 has a male buckle 13 at its front end. When the upper cover 1 is pressed against the lower cover 22 along the hinge, the male buckle 13 is engaged with the female buckle 222.

[0032] The lower needle mold 21 is electrically connected to the external testing equipment.

[0033] The floating plate 23 is suitable for chip packaging testing of BGA, QFN, LGA, QFP and SOP.

[0034] In summary, the specific embodiments of this utility model are as follows:

[0035] First, the chip under test is placed in the encapsulation groove 233 in the middle of the substrate encapsulation layer 231 of the floating plate 23. The encapsulation groove 233 is uniformly provided with pin holes 2331 that are adapted to the pin 211. This ensures that the chip under test can be accurately positioned and its electrode points can be aligned with the pin 211 on the pin mold 21. The positioning arcs 2332 at the four corners of the encapsulation groove 233, the first adapter grooves 2333 at the front and rear ends, and the second adapter grooves 2321 at the left and right ends of the encapsulation extension layer 232 help to correctly position different types of chips.

[0036] Next, the operator closes the upper cover 1 onto the lower cover 22 along the hinge. Since the height of the chip pressing block 3 can be adjusted by the engagement of the pin 33 with the pin holes 111 at the four corners of the pressing block groove 11 to accommodate chip packages of different thicknesses, for packaged chips of different thicknesses, the chip pressing block 3 located in the pressing block groove 11 on one side of the upper cover 1 can be screwed on by the pin 33, so that the chip pressing block 3 will slide in the pressing block height fine adjustment port 12 through the adjustment protrusion 31. At the same time, the appropriate clamping force is applied to the chip by the action of the spring 32 to complete the pressing of packaged chips of different thicknesses.

[0037] As the upper cover 1 is closed, the male snap part 13 at the front end of the upper cover will engage with the female snap part 222 at the front end of the lower cover, thereby ensuring that the entire test seat assembly is tightly closed. At this time, the four chamfers of the encapsulation extension layer 232 of the floating plate 23 are adapted to the surface of the floating plate positioning block 2211 on the top side inside the connector 221, further ensuring the stability and accuracy of the floating plate 23.

[0038] Once the test socket assembly is closed and locked, the pin 211 on the lower pin mold 21 will contact the electrode point of the chip under test through the pin hole 2331 to establish an electrical signal connection. Subsequently, the lower pin mold 21 is connected to the external test equipment to start performing electrical characteristic tests such as current, resistance, and bandwidth, as well as rapid verification, functional testing, data programming, and aging tests to ensure that each chip meets the design requirements and to screen out potentially failed chips. After the test is completed, the operator releases the lock between the upper cover 1 and the lower cover 22, opens the upper cover 1, takes out the tested chip, and prepares for the next test cycle.

[0039] It should be noted that this invention is applicable to chip testing with a thickness of 0.35 to 1.3 mm, and provides 15g to 30g of elasticity to ensure contact and testing stability.

[0040] The above description is only the optimal solution embodiment of this utility model and is not intended to limit this utility model. Various modifications or substitutions made by those skilled in the art to this utility model without departing from the essence and protection scope of this utility model should also be within the protection scope of this utility model.

Claims

1. A simple semiconductor ATE packaging and testing mechanism, comprising a test socket assembly (2), characterized in that: The test socket assembly (2) includes a lower pin mold (21), a lower cover (22) disposed on the upper end of the lower pin mold (21), and a floating plate (23) adapted to the interface (221) in the middle of the lower cover (22). A plurality of lower pin pins (211) are uniformly exposed in the middle of the lower pin mold (21). The floating plate (23) is provided with a substrate encapsulation layer (231) and an encapsulation extension layer disposed on the upper surface of the substrate encapsulation layer (231). 232), the substrate encapsulation layer (231) is provided with an encapsulation groove (233) in the middle, and the encapsulation groove (233) is uniformly provided with pin holes (2331) that are adapted to a plurality of the lower pin pins (211). The four corners of the encapsulation groove (233) are provided with positioning arcs (2332), and the front and rear ends are symmetrically provided with first adapter grooves (2333). The left and right ends of the encapsulation extension layer (232) are provided with second adapter grooves (2321).

2. The simplified semiconductor ATE packaging and testing mechanism according to claim 1, characterized in that: The lower cover (22) is hinged to the upper cover (1) at its rear end. The upper cover (1) is provided with a pressure block groove (11) on one side near the lower cover (22). The pressure block groove (11) is provided with a pressure block height fine adjustment port (12) in the middle. The pressure block groove (11) is provided with pin holes (111) at its four corners. A chip pressure block (3) is disposed in the pressure block groove (11). The adjusting protrusion (31) of the chip pressure block (3) is slidably connected to the pressure block height fine adjustment port (12). The two sides of the chip pressure block (3) are elastically connected to the two sides of the pressure block groove (11) by springs (32). The height of the chip pressure block (3) is adjusted by the matching of the pin (33) and the pin hole (111).

3. The simplified semiconductor ATE packaging and testing mechanism according to claim 1, characterized in that: Each of the four corners of the top side of the connector (221) is provided with a floating plate positioning block (2211). The four corners of the substrate encapsulation layer (231) are adapted to the four corners of the bottom of the connector (221). The four chamfers of the encapsulation extension layer (232) are adapted to the surface of the floating plate positioning block (2211).

4. A simplified semiconductor ATE packaging and testing mechanism according to claim 2, characterized in that: The lower cover (22) has a female buckle (222) at its front end, and the upper cover (1) has a male buckle (13) at its front end. When the upper cover (1) is pressed against the lower cover (22) along the hinge, the male buckle (13) is engaged with the female buckle (222).

5. A simplified semiconductor ATE packaging and testing mechanism according to claim 1, characterized in that: The lower needle mold (21) is electrically connected to the external testing equipment.

6. A simplified semiconductor ATE packaging and testing mechanism according to claim 1, characterized in that: The floating plate (23) is suitable for chip packaging testing of BGA, QFN, LGA, QFP and SOP.

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