Shift register, gate drive circuit and display device

Abstract

A shift register, a gate drive circuit, and a display device, the shift register comprising: a first input sub-circuit configured to charge a pull-up node under signal control of a first input end; the pull-up sub-circuit is configured to transmit a signal of a clock signal end to a signal output end under the control of the pull-up node; the first pull-down control sub-circuit is configured to transmit a signal of the first power supply end to a pull-down node under the control of the signal of the first power supply end; the second pull-down control sub-circuit is configured to transmit the signal of the second power supply end to the pull-down node under the control of the signal of the second power supply end; the pull-down sub-circuit is configured to transmit a signal of a third power supply end to a pull-down node under the control of the pull-up node; the noise reduction sub-circuit is configured to perform noise reduction on the pull-up node and the signal output end under the control of the pull-down node; and the first gating sub-circuit is configured to pull down the potential of the pull-down node under the signal control of the first input end.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] Gate Driver On Array (GOA) is a technology that integrates gate driving circuitry onto an array substrate. The gate driving circuitry includes multiple shift registers, and the cascading relationship of the shift registers enables the sequential activation of pixels, thereby achieving display. Utility Model Content

[0003] This disclosure provides a shift register, including:

[0004] The first input sub-circuit is electrically connected to the first input terminal and the pull-up node, and is configured to charge the pull-up node under the signal control of the first input terminal;

[0005] The pull-up sub-circuit is electrically connected to the pull-up node, the signal output terminal of the shift register, and the clock signal terminal, and is configured to transmit the signal from the clock signal terminal to the signal output terminal under the control of the pull-up node.

[0006] The first pull-down control sub-circuit, electrically connected to the pull-down node and the first power supply terminal, is configured to transmit the signal of the first power supply terminal to the pull-down node under the signal control of the first power supply terminal.

[0007] The second pull-down control sub-circuit is electrically connected to the pull-down node and the second power supply terminal, and is configured to transmit the signal of the second power supply terminal to the pull-down node under the signal control of the second power supply terminal; wherein the signal of the first power supply terminal and the signal of the second power supply terminal both switch between a first level potential and a second level potential, and at least for a certain period of time, one of the signals of the first power supply terminal and the second power supply terminal is at the first level potential and the other is at the second level potential;

[0008] A pull-down sub-circuit, electrically connected to the pull-up node, the pull-down node, and the third power supply terminal, is configured to transmit the signal from the third power supply terminal to the pull-down node under the potential control of the pull-up node.

[0009] A noise reduction sub-circuit, electrically connected to the pull-up node, the pull-down node, and the signal output terminal, is configured to reduce noise at the pull-up node and the signal output terminal under the potential control of the pull-down node.

[0010] The first gating sub-circuit, electrically connected to the first input terminal and the pull-down node, is configured to pull down the potential of the pull-down node under the signal control of the first input terminal.

[0011] In some embodiments, the shift register further includes: a second input sub-circuit, which is connected to a second input terminal, the pull-up node, and the third power supply terminal, and is configured to transmit the signal from the third power supply terminal to the pull-up node under the signal control of the second input terminal;

[0012] The first selection sub-circuit is also electrically connected to the third power supply terminal and is configured to pull down the potential of the pull-down node using the signal from the third power supply terminal under the signal control of the first input terminal.

[0013] In some embodiments, the first gating sub-circuit includes: a first gating transistor, the gate of the first gating transistor being electrically connected to the first input terminal, a first terminal being electrically connected to the pull-down node, and a second terminal being electrically connected to the third power supply terminal.

[0014] In some embodiments, the second input sub-circuit includes: a second input transistor, the gate of which is electrically connected to the second input terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the third power supply terminal.

[0015] In some embodiments, the first input sub-circuit is also electrically connected to the forward scanning power supply terminal and is configured to charge the pull-up node using the signal from the forward scanning power supply terminal under the control of the first input terminal.

[0016] The shift register also includes:

[0017] The second input sub-circuit is electrically connected to the second input terminal, the pull-up node, and the reverse scan power supply terminal, and is configured to transmit the signal from the reverse scan power supply terminal to the pull-up node under the signal control of the second input terminal.

[0018] The second gating sub-circuit, electrically connected to the second input terminal, the pull-down node, and the forward scanning power supply terminal, is configured to transmit the signal from the forward scanning power supply terminal to the pull-down node under the signal control of the second input terminal.

[0019] The forward scanning power supply provides a first level signal in the forward scanning state and a second level signal in the reverse scanning state; the reverse scanning power supply provides the second level signal in the forward scanning state and the first level signal in the reverse scanning state.

[0020] In some embodiments, the first input sub-circuit includes: a first input transistor, wherein the gate of the first input transistor is electrically connected to the first input terminal, the first electrode is electrically connected to the forward scan power supply terminal, and the second electrode is electrically connected to the pull-up node;

[0021] The second input sub-circuit includes: a second input transistor, the gate of which is electrically connected to the second input terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the reverse scan power supply terminal.

[0022] In some embodiments, the first gating sub-circuit includes: a first gating transistor, wherein the gate of the first gating transistor is electrically connected to the first input terminal, the first electrode is electrically connected to the pull-down node, and the second electrode is electrically connected to the reverse scan power supply terminal;

[0023] The second gating sub-circuit includes: a second gating transistor, the gate of the second gating transistor being electrically connected to the second input terminal, the first terminal being electrically connected to the forward scanning power supply terminal, and the second terminal being electrically connected to the pull-down node.

[0024] In some embodiments, the pull-up sub-circuit includes a pull-up transistor and a storage capacitor, wherein the gate of the pull-up transistor is electrically connected to the pull-up node, the first terminal is electrically connected to the clock signal terminal, and the second terminal is electrically connected to the signal output terminal.

[0025] In some embodiments, the first pull-down control sub-circuit includes:

[0026] The first pull-down control transistor has its gate and first terminal both electrically connected to the first power supply terminal.

[0027] The second pull-down control transistor has its gate electrically connected to the second terminal of the first pull-down control transistor, its first terminal electrically connected to the first power supply terminal, and its second terminal electrically connected to the pull-down node.

[0028] The third pull-down control transistor has its gate electrically connected to the pull-up node, its first terminal electrically connected to the second terminal of the first pull-down control transistor, and its second terminal electrically connected to the third power supply terminal.

[0029] The second pull-down control sub-circuit includes:

[0030] The fourth pull-down control transistor, wherein both the gate and the first terminal of the fourth pull-down control transistor are electrically connected to the second power supply terminal;

[0031] The fifth pull-down control transistor has its gate electrically connected to the second terminal of the fourth pull-down control transistor, its first terminal electrically connected to the second power supply terminal, and its second terminal electrically connected to the pull-down node.

[0032] The sixth pull-down control transistor has its gate electrically connected to the pull-up node, its first terminal electrically connected to the second terminal of the fourth pull-down control transistor, and its second terminal electrically connected to the third power supply terminal.

[0033] In some embodiments, the first pull-down control sub-circuit includes: a first pull-down control transistor, wherein the gate and first terminal of the first pull-down control transistor are electrically connected to the first power supply terminal, and the second terminal is electrically connected to the pull-down node;

[0034] The second pull-down control sub-circuit includes: a fourth pull-down control transistor, wherein the gate and first terminal of the fourth pull-down control transistor are electrically connected to the second power supply terminal, and the second terminal is electrically connected to the pull-down node.

[0035] In some embodiments, the pull-down sub-circuit includes: a pull-down transistor, the gate of which is electrically connected to the pull-up node, a first terminal which is electrically connected to the pull-down node, and a second terminal which is electrically connected to the third power supply terminal.

[0036] In some embodiments, the noise reduction sub-circuit includes:

[0037] The first noise reduction transistor has its gate electrically connected to the pull-down node, its first terminal electrically connected to the pull-up node, and its second terminal electrically connected to the third power supply terminal.

[0038] The second noise reduction transistor has its gate electrically connected to the pull-down node, its first terminal electrically connected to the signal output terminal, and its second terminal electrically connected to the fourth power supply terminal.

[0039] The third power supply terminal is electrically connected to the fourth power supply terminal, or the third power supply terminal and the fourth power supply terminal are independent of each other.

[0040] In some embodiments, the shift register further includes:

[0041] The shift sub-circuit, electrically connected to the pull-up node, the clock signal terminal, and the cascaded output terminal of the shift register, is configured to transmit the signal from the clock signal terminal to the cascaded output terminal under the potential control of the pull-up node.

[0042] An auxiliary noise reduction sub-circuit, electrically connected to the pull-down node, the cascaded output terminal, and the fourth power supply terminal, is configured to transmit the signal from the fourth power supply terminal to the cascaded output terminal under the potential control of the pull-down node.

[0043] The third power supply terminal is electrically connected to the fourth power supply terminal, or the third power supply terminal and the fourth power supply terminal are independent of each other.

[0044] In some embodiments, the shift sub-circuit includes: a shift transistor, wherein the gate of the shift transistor is electrically connected to the pull-up node, the first terminal is electrically connected to the clock signal terminal, and the second terminal is electrically connected to the cascaded output terminal;

[0045] The auxiliary noise reduction sub-circuit includes:

[0046] The third noise reduction transistor has its gate electrically connected to the pull-down node, its first terminal electrically connected to the cascaded output terminal, and its second terminal electrically connected to the fourth power supply terminal.

[0047] In some embodiments, the shift register further includes a reset sub-circuit, which is electrically connected to the reset terminal, the pull-up node, and the signal output terminal, and is configured to reset the potential of the pull-up node and the signal output terminal under the signal control of the reset terminal.

[0048] In some embodiments, the reset sub-circuit includes:

[0049] The first reset transistor has its gate electrically connected to the reset terminal, its first terminal electrically connected to the pull-up node, and its second terminal electrically connected to the third power supply terminal.

[0050] The second reset transistor has its gate electrically connected to the reset terminal, its first terminal electrically connected to the signal output terminal, and its second terminal electrically connected to the fourth power supply terminal.

[0051] The third power supply terminal is electrically connected to the fourth power supply terminal, or the third power supply terminal and the fourth power supply terminal are independent of each other.

[0052] This disclosure also provides a gate driving circuit, including a plurality of cascaded shift registers, wherein the shift registers are those described above.

[0053] This disclosure also provides a display device, which includes the gate driving circuit described above. Attached Figure Description

[0054] Figure 1A This is a circuit diagram of a shift register provided in some embodiments.

[0055] Figure 1B This is a schematic diagram of a shift register provided in some embodiments of this disclosure.

[0056] Figure 1C A block diagram of a shift register provided for Embodiment 1 of this disclosure.

[0057] Figure 1D A specific circuit diagram of the shift register provided for Embodiment 1 of this disclosure.

[0058] Figure 1E This is a timing diagram of the shift register in Example 1 during the forward scan process.

[0059] Figure 1F This is a timing diagram of the shift register in the reverse scan process in Example 1.

[0060] Figure 2A A specific circuit diagram of the shift register provided for Embodiment 2 of this disclosure.

[0061] Figure 2B This is a timing diagram of the shift register in the second embodiment during the forward scan process.

[0062] Figure 2C This is a timing diagram of the shift register in the reverse scan process in Example 2.

[0063] Figure 3 The specific circuit diagram of the shift register provided in Embodiment 3 of this disclosure is shown.

[0064] Figure 4 The specific circuit diagram of the shift register provided in Embodiment 4 of this disclosure is shown.

[0065] Figure 5 The specific circuit diagram of the shift register provided in Embodiment 5 of this disclosure is shown.

[0066] Figure 6 The specific circuit diagram of the shift register provided in Embodiment Six of this disclosure is shown.

[0067] Figure 7 The specific circuit diagram of the shift register provided in Embodiment 7 of this disclosure is shown.

[0068] Figure 8 The specific circuit diagram of the shift register provided in Embodiment 8 of this disclosure is shown.

[0069] Figure 9 The specific circuit diagram of the shift register provided in Embodiment Nine of this disclosure is shown.

[0070] Figure 10 The specific circuit diagram of the shift register provided in Embodiment 10 of this disclosure is shown.

[0071] Figure 11 The specific circuit diagram of the shift register provided in Embodiment Eleven of this disclosure is shown.

[0072] Figure 12 The specific circuit diagram of the shift register provided in Embodiment Twelve of this disclosure is shown.

[0073] Figure 13 The specific circuit diagram of the shift register provided in Embodiment Thirteen of this disclosure is shown.

[0074] Figure 14 The specific circuit diagram of the shift register provided in Embodiment Fourteen of this disclosure is shown.

[0075] Figure 15 The specific circuit diagram of the shift register provided in Embodiment 15 of this disclosure is shown.

[0076] Figure 16 The specific circuit diagram of the shift register provided in Embodiment Sixteen of this disclosure is shown.

[0077] Figure 17 The curves show the threshold voltage of the relevant transistors in a shift register with dual PDs and a shift register with a single PD as a function of the lighting time.

[0078] Figure 18 This is a schematic diagram of the gate drive circuit provided in an embodiment of this disclosure.

[0079] Figure 19 This is a signal timing diagram of a gate drive circuit provided in an embodiment of this disclosure.

[0080] Figure 20 This is another signal timing diagram of the gate drive circuit provided in the embodiments of this disclosure.

[0081] Figure 21 This is another signal timing diagram of the gate drive circuit provided in the embodiments of this disclosure. Detailed Implementation

[0082] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this disclosure do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this disclosure are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to such processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” in this disclosure refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can indicate: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," "third," etc., used in this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0084] It should be noted that each transistor in the embodiments of this disclosure can be a thin-film transistor, a field-effect transistor, or other switching devices with the same characteristics; one of the first and second terminals of the transistor is the source of the transistor, and the other is the drain of the transistor.

[0085] Furthermore, in this disclosure, "first level potential" refers to a potential that enables the transistor to conduct, and "second level potential" refers to a potential that enables the transistor to turn off; "first level signal" refers to a signal that enables the transistor to conduct, and "second level signal" refers to a signal that enables the transistor to turn off. When the transistor is an N-type transistor, the first level potential refers to a high level potential, and the second level potential refers to a low level potential; the first level signal refers to a high level signal, and the second level signal refers to a low level signal. However, when the transistor is a P-type transistor, the first level potential refers to a low level potential, the first level signal refers to a low level signal, the second level potential refers to a high level potential, and the second level signal refers to a high level signal.

[0086] In this invention, an example is provided where all transistors are N-type transistors. In this case, the first voltage level is a high voltage level, and the second voltage level is a low voltage level.

[0087] Figure 1A Here are circuit diagrams of shift registers provided in some embodiments, such as Figure 1A As shown, the shift register includes an input sub-circuit 10, a pull-up sub-circuit 13, a reset sub-circuit 13, a first pull-down control sub-circuit 21, a second pull-down control sub-circuit 22, a first pull-down sub-circuit 31, a second pull-down sub-circuit 32, a first noise reduction sub-circuit 51, a second noise reduction sub-circuit 52, and a reset sub-circuit 60. The input sub-circuit 10 includes an input transistor M1, whose gate and first terminal are connected to the input terminal IN, and whose second terminal is connected to the pull-up node PU. The pull-up sub-circuit 40 includes a pull-up transistor M3 and a storage capacitor C1. The gate of the pull-up transistor M3 is electrically connected to the pull-up node, its first terminal is electrically connected to the clock signal terminal CLK, and its second terminal is electrically connected to the signal output terminal Out. The two ends of the storage capacitor C1 are electrically connected to the pull-up node PU and the signal output terminal Out, respectively. The reset sub-circuit 13 includes a reset transistor M2, whose gate is electrically connected to the reset terminal RST, its first terminal is electrically connected to the pull-up node PU, and its second terminal is electrically connected to the third power supply terminal V3.

[0088] The first pull-down control sub-circuit 21 includes transistors M9A, M5A, and M8A. The gate and first terminal of transistor M9A are electrically connected to the first power supply terminal VDDO, and its second terminal is electrically connected to the first terminal of transistor M8A. The gate of transistor M5A is electrically connected to the first terminal of transistor M8A, and its first terminal is electrically connected to the first power supply terminal VDDO. Its second terminal is electrically connected to the first pull-down node PD1. The gate of transistor M8A is electrically connected to the pull-up node PU, and its second terminal is electrically connected to the third power supply terminal V3. The first pull-down sub-circuit 31 includes transistor M6A, whose gate is electrically connected to the pull-up node PU, its first terminal is electrically connected to the first pull-down node PD1, and its second terminal is electrically connected to the third power supply terminal V3.

[0089] The second pull-down control sub-circuit 22 includes transistors M9B, M5B, and M8B. The gate and first terminal of transistor M9B are electrically connected to the second power supply terminal VDDE, and its second terminal is electrically connected to the first terminal of transistor M8B. The gate of transistor M5B is electrically connected to the first terminal of transistor M8B, and its first terminal is electrically connected to the second power supply terminal VDDE. Its second terminal is also electrically connected to the second pull-down node PD2. The gate of transistor M8B is electrically connected to the pull-up node PU, and its second terminal is electrically connected to the third power supply terminal V3. The second pull-down sub-circuit 32 includes transistor M6B, whose gate is electrically connected to the pull-up node PU, its first terminal is electrically connected to the second pull-down node PD2, and its second terminal is electrically connected to the third power supply terminal V3.

[0090] The first noise reduction sub-circuit 51 includes transistors M10A and M11A. The gates of transistors M10A and M11A are both electrically connected to the first pull-down node PD1. The first terminal of transistor M10A is electrically connected to the pull-up node PU, and the second terminal is electrically connected to the third power supply terminal V3. The first terminal of transistor M11A is electrically connected to the signal output terminal Out, and the second terminal is electrically connected to the third power supply terminal V3. The second noise reduction sub-circuit 52 includes transistors M10B and M11B. The gates of transistors M10B and M11B are both electrically connected to the second pull-down node PD2. The first terminal of transistor M10B is electrically connected to the pull-up node PU, and the second terminal is electrically connected to the third power supply terminal V3. The first terminal of transistor M11B is electrically connected to the signal output terminal Out, and the second terminal is electrically connected to the third power supply terminal V3.

[0091] The reset sub-circuit 60 includes transistors M4 and M7, both of which have their gates electrically connected to the reset terminal Total-Rest. The first terminal of transistor M4 is electrically connected to the pull-up node PU, and the second terminal is electrically connected to the third power supply terminal V3. The first terminal of transistor M7 is electrically connected to the signal output terminal Out, and the second terminal is electrically connected to the third power supply terminal V3.

[0092] Taking a high-level signal provided by the first power supply terminal VDDO and a low-level signal provided by the second power supply terminal VDDE as an example, during the input stage of the shift register operation, there is a competition relationship between the pull-up node PU and the first pull-down node PD1. When the input terminal provides a high-level signal, the input sub-circuit charges the storage capacitor C1. At this time, the potential of the pull-up node PU begins to rise. If the transistor M6A fails, it will cause the potential of the first pull-down node PD1 to reach a high level, thereby causing M10A to be mis-turned on, which in turn prevents the pull-up node PU from charging. As a result, the shift register at this stage has no output, leading to interlaced display.

[0093] To address this issue, this disclosure provides a shift register. Figure 1B This is a schematic diagram of a shift register provided in some embodiments of this disclosure, such as... Figure 1B As shown, the shift register includes a first input sub-circuit 11, a pull-up sub-circuit 40, a first pull-down control sub-circuit 21, a second pull-down control sub-circuit 22, a pull-down sub-circuit 30, a noise reduction sub-circuit 50, and a first gating sub-circuit 71.

[0094] The first input sub-circuit 11 is electrically connected to the first input terminal IN1 and the pull-up node PU. The first input sub-circuit 11 is configured to charge the pull-up node PU under the signal control of the first input terminal IN1.

[0095] Pull-up sub-circuit 40 is electrically connected to pull-up node PU, signal output terminal Out of shift register, and clock signal terminal CLK. Pull-up sub-circuit 40 is configured to transmit the signal of clock signal terminal CLK to signal output terminal Out under the control of pull-up node PU.

[0096] The first pull-down control sub-circuit 21 is electrically connected to the pull-down node PD and the first power supply terminal VDDO. The first pull-down control sub-circuit 21 is configured to transmit the signal of the first power supply terminal VDDO to the pull-down node PD under the signal control of the first power supply terminal VDDO.

[0097] The second pull-down control subcircuit 22 is electrically connected to the pull-down node PD and the second power supply terminal VDDE. The second pull-down control subcircuit 22 is configured to transmit the signal of the second power supply terminal VDDE to the pull-down node PD under the signal control of the second power supply terminal VDDE. The signals of both the first power supply terminal VDDO and the second power supply terminal VDDE switch between a first level and a second level, and for at least a portion of the time, one of the signals of the first power supply terminal VDDO and the second power supply terminal VDDE is at the first level, while the other is at the second level. For example, at any given time, one of the first power supply terminal VDDO and the second power supply terminal VDDE provides a first-level signal, and the other provides a second-level signal. For example, both the first power supply terminal VDDO and the second power supply terminal VDDE switch signals once after a preset duration, thereby causing the first pull-down control subcircuit 21 and the second pull-down control subcircuit 22 to work alternately, preventing threshold offset caused by prolonged conduction of the transistors in the first pull-down control subcircuit 21 and the second pull-down control subcircuit 22.

[0098] The pull-down sub-circuit 30 is electrically connected to the pull-up node PU, the pull-down node PD, and the third power supply terminal V3. The pull-down sub-circuit 30 is configured to transmit the signal of the third power supply terminal V3 to the pull-down node PD under the potential control of the pull-up node PU.

[0099] The noise reduction sub-circuit 50 is electrically connected to the pull-up node PU, the pull-down node PD, and the signal output terminal Out. The noise reduction sub-circuit 50 is configured to reduce noise at the pull-up node PU and the signal output terminal Out under the potential control of the pull-down node PD.

[0100] The first gating sub-circuit 71 is electrically connected to the first input terminal IN1 and the pull-down node PD. The first gating sub-circuit 71 is configured to pull down the potential of the pull-down node PD under the signal control of the first input terminal IN1.

[0101] In this embodiment, during the input phase of the shift register operation, when the first input terminal IN1 provides a first-level signal, the first input sub-circuit 11 charges the pull-up node PU. Simultaneously, the first gating sub-circuit 71 pulls down the potential of the pull-down node PD, ensuring that the potential of the pull-up node PU is not affected by the potential of the pull-down node PD, thereby preventing a competition relationship between the pull-up node PU and the pull-down node PD. Furthermore, the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 are electrically connected to the same pull-down node PD, controlling the potential of the same pull-down node PD. Figure 1A Compared to the shift register shown, Figure 1B The number of pull-down nodes PD in the shift register shown is reduced, which in turn reduces the number of pull-down sub-circuits 30, that is, reduces the number of transistors in the shift register, thereby simplifying the structure of the shift register and making it easier to achieve a narrow bezel design.

[0102] The shift register in this disclosure will now be described in conjunction with specific embodiments.

[0103] Figure 1C A block diagram of the shift register provided in Embodiment 1 of this disclosure is shown below. Figure 1C As shown, the first input sub-circuit 11 is also electrically connected to the forward scan power supply terminal VDS and is configured to charge the pull-up node PU using the signal from the forward scan power supply terminal VDS under the control of the first input terminal IN1. In addition to the aforementioned first input sub-circuit 11, pull-up sub-circuit 40, first pull-down control sub-circuit 21, second pull-down control sub-circuit 22, pull-down sub-circuit 30, noise reduction sub-circuit 50, and first gating sub-circuit 71, the shift register may also include: a second input sub-circuit 12 and a second gating sub-circuit 72.

[0104] The second input sub-circuit 12 is electrically connected to the second input terminal IN2, the pull-up node PU, and the reverse scan power supply terminal VSD. The second input sub-circuit 12 is configured to transmit the signal from the reverse scan power supply terminal VSD to the pull-up node PU under the signal control of the second input terminal IN2. The second gating sub-circuit 72 is electrically connected to the second input terminal IN2, the pull-down node PD, and the forward scan power supply terminal VDS. The second gating sub-circuit 72 is configured to transmit the signal from the forward scan power supply terminal VDS to the pull-down node PD under the signal control of the second input terminal IN2. Specifically, the forward scan power supply terminal VDS provides a first-level signal in the forward scan state and a second-level signal in the reverse scan state; the reverse scan power supply terminal VSD provides a second-level signal in the forward scan state and a first-level signal in the reverse scan state.

[0105] Figure 1CThe shift register shown can achieve bidirectional scanning. During the forward scan, the forward scan power supply terminal VDS provides a first-level signal, and the reverse scan power supply terminal VSD provides a second-level signal. During the input phase of the forward scan, the first input terminal IN1 provides a first-level signal. The first input sub-circuit 11 uses the first-level signal from the forward scan power supply terminal VDS to charge the pull-up node PU. Simultaneously, the first gating sub-circuit 71, under the signal control of the first input terminal IN1, pulls down the potential of the pull-down node PD. During the pull-up phase, the pull-up sub-circuit 40, under the potential control of the pull-up node PU, transmits the signal provided by the clock signal terminal CLK to the signal output terminal Out. During the reset phase, the second input terminal IN2 provides a first-level signal, and the second input sub-circuit 12 uses the reverse scan power supply terminal VSD to reset the pull-up node PU. Simultaneously, under the signal control of the second input terminal IN2, the second gating sub-circuit 72 connects the pull-down node PD to the forward scan power supply terminal VDS, keeping the pull-down node PD in the first-level state. Under the control of the pull-down node PD, the noise reduction sub-circuit 50 reduces noise on the pull-up node PU and the pull-down node PD, keeping the pull-up node PU and the signal output terminal Out at the second level potential. During the noise reduction phase of the forward scanning process, one of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 provides a first level signal to the pull-down node PD, and the noise reduction sub-circuit 50 reduces noise on the pull-up node PU and the signal output terminal Out under the potential control of the pull-down node PD.

[0106] During the reverse scan process, the forward scan power supply terminal VDS provides a second-level signal, and the reverse scan power supply terminal VSD provides a first-level signal. During the input phase of the reverse scan process, the second input terminal IN2 provides a first-level signal, and the second input sub-circuit 12 uses the first-level signal from the reverse scan power supply terminal VSD to charge the pull-up node PU. During the pull-up phase, the pull-up sub-circuit 40, under the potential control of the pull-up node PU, transmits the signal provided by the clock signal terminal CLK to the signal output terminal Out. During the reset phase, the first input terminal IN1 provides a first-level signal, and the first input sub-circuit 11 uses the forward scan power supply terminal VDS to reset the pull-up node PU. Simultaneously, under the signal control of the first input terminal IN1, the first gating sub-circuit 71 connects the pull-down node PD to the forward scan power supply terminal VDS, maintaining the pull-down node PD in the first-level state. The noise reduction sub-circuit 50, under the control of the pull-down node PD, reduces noise in the pull-up node PU and the pull-down node PD, maintaining the pull-up node PU and the signal output terminal Out at the second-level potential. During the noise reduction phase of the forward scanning process, one of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 provides a first level signal to the pull-down node PD. Under the potential control of the pull-down node PD, the noise reduction sub-circuit 50 reduces noise for the pull-up node PU and the signal output terminal Out.

[0107] In addition, the shift register also includes a reset sub-circuit 60, which is electrically connected to the reset terminal Total-Rest, the pull-up node PU, and the signal output terminal Out. It is configured to reset the potential of the pull-up node PU and the signal output terminal Out under the signal control of the reset terminal Total-Rest.

[0108] The Total-Rest reset terminal is used to provide a first-level signal before each frame. The Total-Rest reset terminals of all shift register units can be connected together, so that the pull-up nodes PU and signal output terminals Out of each shift register can be reset using the reset sub-circuit 60 of each shift register before each frame is displayed.

[0109] Figure 1D A specific circuit diagram of the shift register provided for Embodiment 1 of this disclosure is shown below. Figure 1D As shown, the first input sub-circuit 11 includes a first input transistor M1. The gate of the first input transistor M1 is electrically connected to the first input terminal IN1, the first terminal is electrically connected to the forward scan power supply terminal VDS, and the second terminal is electrically connected to the pull-up node PU. When the first input terminal IN1 provides a first level signal, the first input transistor M1 turns on the forward scan power supply terminal VDS and the pull-up node PU, thereby charging the pull-up node PU during the input phase of the forward scan process and resetting the pull-up node PU during the reset phase of the reverse scan process.

[0110] The second input sub-circuit 12 includes a second input transistor M2. The gate of the second input transistor M2 is electrically connected to the second input terminal IN2, the first terminal is electrically connected to the pull-up node PU, and the second terminal is electrically connected to the reverse scan power supply terminal VSD. When the second input terminal IN2 provides a first level signal, the second input transistor M2 turns on the reverse scan power supply terminal VSD and the pull-up node PU, thereby resetting the pull-up node PU during the reset phase of the forward scan process and charging the pull-up node PU during the input phase of the reverse scan process.

[0111] The first gating sub-circuit 71 includes a first gating transistor M16A. The gate of the first gating transistor M16A is electrically connected to the first input terminal IN1, the first terminal is electrically connected to the pull-down node PD, and the second terminal is electrically connected to the reverse scan power supply terminal VSD. When the first input terminal IN1 provides a first level signal, the first gating transistor M16A turns on the reverse scan power supply terminal VSD and the pull-down node PD.

[0112] The second selection sub-circuit 72 includes a second selection transistor M16B. The gate of the second selection transistor M16B is electrically connected to the second input terminal IN2, the first terminal is electrically connected to the forward scan power supply terminal VDS, and the second terminal is electrically connected to the pull-down node PD. When the second input terminal IN2 provides a first level signal, the second selection transistor M16B turns on the forward scan terminal and the pull-down node PD.

[0113] The pull-up sub-circuit 40 includes a pull-up transistor M3 and a storage capacitor C1. The gate of the pull-up transistor M3 is electrically connected to the pull-up node PU, the first terminal is electrically connected to the clock signal terminal CLK, and the second terminal is electrically connected to the signal output terminal Out. When the pull-up node PU is at the first level potential, the pull-up transistor M3 turns on the clock signal terminal CLK and the signal output terminal Out.

[0114] The first pull-down control sub-circuit 21 includes: a first pull-down control transistor M9A, a second pull-down control transistor M5A, and a third pull-down control transistor M8A. The gate and first terminal of the first pull-down control transistor M9A are both electrically connected to the first power supply terminal VDDO. The gate of the second pull-down control transistor M5A is electrically connected to the second terminal of the first pull-down control transistor M9A, and the first terminal of the second pull-down control transistor M5A is electrically connected to the first power supply terminal VDDO. The second terminal of the second pull-down control transistor M5A is also electrically connected to the pull-down node PD. The gate of the third pull-down control transistor M8A is electrically connected to the pull-up node PU, and the first terminal of the third pull-down control transistor M8A is electrically connected to the second terminal of the first pull-down control transistor M9A. The second terminal of the third pull-down control transistor M8A, the gate of the second pull-down control transistor M5A, and the first terminal of the third pull-down control transistor M8A are connected to the first pull-down control node PD_CN1.

[0115] The second pull-down control sub-circuit 22 includes: a fourth pull-down control transistor M9B, a fifth pull-down control transistor M5B, and a sixth pull-down control transistor M8B. The gate and first terminal of the fourth pull-down control transistor M9B are both electrically connected to the second power supply terminal VDDE. The gate of the fifth pull-down control transistor M5B is electrically connected to the second terminal of the fourth pull-down control transistor M9B, and the first terminal of the fifth pull-down control transistor M5B is electrically connected to the second power supply terminal VDDE. The second terminal of the fifth pull-down control transistor M5B is also electrically connected to the pull-down node PD. The gate of the sixth pull-down control transistor M8B is electrically connected to the pull-up node PU, and the first terminal of the sixth pull-down control transistor M8B is electrically connected to the second terminal of the fourth pull-down control transistor M9B. The second terminal of the sixth pull-down control transistor M8B is also electrically connected to the third power supply terminal V3. The second terminal of the fourth pull-down control transistor M9B, the gate of the fifth pull-down control transistor M5B, and the first terminal of the sixth pull-down control transistor M8B are connected to the second pull-down control node PD_CN2.

[0116] The pull-down sub-circuit 30 includes: a pull-down transistor M6A, the gate of which is electrically connected to the pull-up node PU, the first terminal of which is electrically connected to the pull-down node PD, and the second terminal of which is electrically connected to the third power supply terminal V3.

[0117] The noise reduction sub-circuit 50 includes a first noise reduction transistor M10A and a second noise reduction transistor M11A. The gate of the first noise reduction transistor M10A is electrically connected to the pull-down node PD, its first terminal is electrically connected to the pull-up node PU, and its second terminal is electrically connected to the third power supply terminal V3. The gate of the second noise reduction transistor M11A is electrically connected to the pull-down node PD, its first terminal is electrically connected to the signal output terminal Out, and its second terminal is electrically connected to the fourth power supply terminal V4. When the pull-down node PD is at a first-level potential, the first noise reduction transistor M10A turns on the pull-down node PD and the third power supply terminal V3; the second noise reduction transistor M11A turns on the signal output terminal Out and the fourth power supply terminal V4. Both the third power supply terminal V3 and the fourth power supply terminal V4 are used to provide a second-level signal. In Embodiment 1, the third power supply terminal V3 and the fourth power supply terminal V4 can be electrically connected to form a single power supply terminal, denoted as the second-level power supply terminal VGL.

[0118] Of course, in other embodiments, the third power supply terminal V3 and the fourth power supply terminal V4 can also be independent of each other.

[0119] The reset sub-circuit 60 includes a first reset transistor M4 and a second reset transistor M7. The gate of the first reset transistor M4 is electrically connected to the reset terminal Total-Rest, its first terminal is electrically connected to the pull-up node PU, and its second terminal is electrically connected to the third power supply terminal V3. The gate of the second reset transistor M7 is electrically connected to the reset terminal Total-Rest, its first terminal is electrically connected to the signal output terminal Out, and its second terminal is electrically connected to the fourth power supply terminal V4.

[0120] The following describes the operation of the shift register in Embodiment 1, using the example where all transistors are N-type transistors, the first level signal is a high level signal, and the second level signal is a low level signal.

[0121] The shift register in this embodiment 1 operates through a forward scan process and a reverse scan process. Figure 1E This is a timing diagram of the shift register in Example 1 during the forward scan process, as shown below. Figure 1E As shown, during the forward scan, the forward scan power supply terminal VDS provides a high-level signal, and the reverse scan power supply terminal VSD provides a low-level signal. The forward scan process includes an input phase, an output phase, a reset phase, and a noise reduction phase.

[0122] During the input phase t1 of the forward scan process, the clock signal provided by the clock signal terminal CLK is at a low level, the first input terminal IN1 provides a high level signal, and the second input terminal IN2 provides a low level signal. At this time, M2 and M16B are turned off; M1 is turned on, thereby starting to charge the storage capacitor C1, that is, the pull-up node PU starts to charge. At the same time, M16A is turned on, thereby pulling down the potential of the pull-down node PD, ensuring that the pull-up node PU can compete with the pull-down node PD. Since the pull-up node PU is at a high level, M3 is turned on, thereby transmitting the low level signal of the clock signal terminal CLK to the signal output terminal Out.

[0123] During the output phase t2 of the forward scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, while the clock signal terminal CLK provides a high-level signal. At this time, M1, M2, M16A, and M16B are turned off. Under the holding effect of the storage capacitor C1, the pull-up node PU remains at a high-level potential, thereby turning on M3 and transmitting the high-level signal of the clock signal terminal CLK to the signal output terminal Out. Under the bootstrap effect of the storage capacitor C1, the potential of the pull-up node PU further increases. Simultaneously, M6A, M8A, and M8B are turned on, thereby pulling down the potentials of the pull-down node PD, the first pull-down control node PD_CN1, and the second pull-down control node PD_CN2, ensuring that the output is completed.

[0124] During the reset phase t3 of the forward scan process, the first input terminal IN1 provides a low-level signal, the second input terminal IN2 provides a high-level signal, and the clock signal terminal CLK provides a low-level signal. At this time, M1 and M16A are turned off, and M2 is turned on, thereby pulling the potential of the pull-up node PU low. At the same time, M16B is turned on, pulling the potential of the pull-down node PD high. Since the pull-down node PD is at a high level, M10A and M11A are turned on, thereby pulling the potential of the pull-up node PU and the signal output terminal Out low.

[0125] During the noise reduction phase t4 of the forward scanning process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, while the clock signal terminal CLK alternately provides high-level and low-level signals. At this time, M1, M2, M16A, and M16B are all turned off, and the pull-up node PU maintains the low-level potential of the previous stage, thereby turning off M6A, M8A, and M8B. If the first power supply terminal VDDO provides a high-level signal and the second power supply terminal VDDE provides a low-level signal, then M9B is turned off, the second pull-down control node PD_CN2 is at a low-level potential, and M5B is turned off; while M9A is turned on, the first pull-down control node PD_CN1 reaches a high-level potential, and M5A is turned on, thereby connecting the pull-down node PD with the first power supply terminal VDDO, reaching a high-level potential. Since the pull-down node PD is at a high-level potential, M10A and M11A remain on, keeping the pull-up node PU and the signal output terminal Out connected to the second-level power supply terminal VGL, thus maintaining a low-level potential. If the first power supply terminal VDDO provides a low-level signal and the second power supply terminal VDDE provides a high-level signal, then M9A is turned off, making the first pull-down control node PD_CN1 a low-level potential, M5A is turned off, M9B is turned on, the second pull-down control node PD_CN2 is a high-level potential, thus making M5B turn on, and the pull-down node PD remains a high-level potential. Therefore, M10A and M11A are always turned on, keeping the pull-up node PU and the signal output terminal Out connected to the second-level power supply terminal, thereby maintaining a low-level potential.

[0126] Figure 1F This is a timing diagram of the shift register in the reverse scan process of Embodiment 1, as shown below. Figure 1F As shown, during the reverse scan process, the reverse scan power supply terminal VSD provides a high-level signal, while the forward scan power supply terminal VDS provides a low-level signal. The reverse scan process includes an input phase, an output phase, a reset phase, and a noise reduction phase.

[0127] During the input phase t1 of the reverse scan process, the second input terminal IN2 provides a high-level signal, while the first input terminal IN1 and the clock signal terminal CLK provide low-level signals. At this time, M1 and M16A are turned off, and M2 is turned on, thereby starting to charge the storage capacitor C1, i.e., the pull-up node PU is turned on for charging. Simultaneously, M16B is turned on, pulling down the pull-down node PD to a low-level potential, ensuring that the pull-up node PU can compete with the pull-down node PD. Since the pull-up node PU is at a high-level potential, M3 is turned on, thereby transmitting the low-level signal of the clock signal terminal CLK to the signal output terminal Out.

[0128] During the output phase t2 of the reverse scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, while the clock signal terminal CLK provides a high-level signal. At this time, M1, M2, M16A, and M16B are all turned off. Because the storage capacitor C1 has a holding effect, the pull-up node PU remains at a high level, thereby turning on M3 and transmitting the high-level potential of the clock signal terminal CLK to the signal output terminal Out. Simultaneously, M6A, M8A, and M8B are turned on, pulling down the pull-down node PD, the first pull-down control node PD_CN1, and the second pull-down control node PD_CN2 to a low level, ensuring that the output is completed.

[0129] During the reset phase t3 of the reverse scan process, the first input terminal IN1 and the clock signal terminal CLK provide low-level signals, while the second input terminal IN2 provides a high-level signal. At this time, M2 and M16B are turned off, M1 is turned on, pulling the pull-up node PU low, and M16A is turned on, pulling the pull-down node PD high. At this time, the pull-down node PD is at a high-level potential. M10A and M11A are turned on, pulling the potential of the pull-up node PU and the signal output terminal Out low.

[0130] During the noise reduction phase t4 of the reverse scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, and the clock signal terminal CLK provides a clock signal that switches between high and low levels. At this time, M1, M2, M16A, and M16B are all turned off, the pull-up node PU is at a low level, and M6A, M8A, and M8B are turned off. If the first power supply terminal VDDO provides a high-level signal and the second power supply terminal VDDE provides a low-level signal, then M9B is turned off, and the second pull-down control node PD_CN2 is at a low level, thereby turning off M5B. Simultaneously, under the control of the first power supply terminal VDDO, M9A is turned on, and the first pull-down control node PD_CN1 is at a high level, thereby turning on M5A, which in turn connects the pull-down node PD to the first power supply terminal VDDO, achieving a high level. Since the pull-down node PD is at a high level, M10A and M11A are always on, keeping the pull-up node PU and the signal output terminal Out connected to the second-level power supply terminal, thus maintaining a low level potential. Similarly, if the first power supply terminal VDDO provides a low-level signal and the second power supply terminal VDDE provides a high-level signal, then M9A is off, making the first pull-down control node PD_CN1 low, M5A is off, M9B is on, and the second pull-down control node PD_CN2 is high, thus making M5B on. The pull-down node PD remains at a high level, therefore M10A and M11A are always on, keeping the pull-up node PU and the signal output terminal Out connected to the second-level power supply terminal, thus maintaining a low level potential.

[0131] Figure 2AA specific circuit diagram of the shift register provided for Embodiment 2 of this disclosure is shown below. Figure 2A As shown, the shift register provided in Embodiment 2 is similar to that in Embodiment 1, except that in Embodiment 2, the shift register further includes a shift sub-circuit 80 and an auxiliary noise reduction sub-circuit 81. The shift sub-circuit 80 is electrically connected to the pull-up node PU, the clock signal terminal CLK, and the cascaded output terminal Out_C of the shift register. It is configured to transmit the signal from the clock signal terminal CLK to the cascaded output terminal Out_C under the potential control of the pull-up node PU. The auxiliary noise reduction sub-circuit 81 is electrically connected to the pull-down node PD, the cascaded output terminal Out_C, and the fourth power supply terminal V4. It is configured to transmit the signal from the fourth power supply terminal V4 to the cascaded output terminal Out_C under the potential control of the pull-down node PD.

[0132] In Embodiment 2, the third power supply terminal V3 and the fourth power supply terminal V4 are connected to the same second-level power supply terminal VGL.

[0133] In Embodiment 2, the signal output terminal Out of the shift register is electrically connected to the grid lines in the display area to provide a scan signal to the grid lines. The cascaded output terminal Out_C is used to cascade with adjacent shift registers to provide the output signal to the adjacent shift register.

[0134] The shift sub-circuit 80 includes a shift transistor M13, whose gate is electrically connected to the pull-up node PU, its first terminal is electrically connected to the clock signal terminal CLK, and its second terminal is electrically connected to the cascaded output terminal Out_C. The auxiliary noise reduction sub-circuit 81 includes a third noise reduction transistor M12, whose gate is electrically connected to the pull-down node PD, its first terminal is electrically connected to the cascaded output terminal Out_C, and its second terminal is electrically connected to the second-level power supply terminal VGL.

[0135] Figure 2B This is a timing diagram of the shift register in Example 2 during the forward scan process. Figure 2C This is a timing diagram of the shift register in Example 2 during the reverse scan process. Figure 2B and Figure 2CAs shown, the operation of the shift register in Embodiment 2 is similar to that in Embodiment 1, except that in the input phases of both the forward and reverse scan processes, shift transistor M13 is turned on, transmitting the low-level signal from the clock signal terminal CLK to the cascaded output terminal Out_C. Similarly, in the output phases of both the forward and reverse scan processes, shift transistor M13 is turned on, transmitting the high-level signal from the clock signal terminal CLK to the cascaded output terminal Out_C. During the reset and noise reduction phases of both the forward and reverse scan processes, the third noise reduction transistor M12 is turned on, pulling the potential of the cascaded output terminal Out_C down to a low level. That is, the on / off state of shift transistor M13 is the same as that of pull-up transistor M3; the on / off state of the third noise reduction transistor M12 is the same as that of the second noise reduction transistor M11A. The on / off states of the remaining transistors are described above in Embodiment 1 and will not be repeated here.

[0136] Figure 3 The specific circuit diagram of the shift register provided in Embodiment 3 of this disclosure is as follows: Figure 3 As shown, the shift register in Embodiment 3 is similar to that in Embodiment 1, except that in Embodiment 3, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both providing a low-level signal. In Embodiment 3, the second terminals of the first reset transistor M4, the pull-down transistor M6A, the third pull-down control transistor M8A, the sixth pull-down control transistor M8B, and the first noise reduction transistor M10A are all connected to the third power supply terminal V3, and the second terminals of the second reset transistor M7 and the second noise reduction transistor M11A are both connected to the fourth power supply terminal V4.

[0137] In this situation, when the device is powered off or experiences an abnormal power outage, the potentials of the first power supply terminal VDDO, the second power supply terminal VDDE, the fourth power supply terminal V4, and the clock signal terminal CLK can be pulled high to release the residual charge in the pixels of the display panel, preventing power-off ghosting and power-on ghosting. The third power supply terminal V3, the forward scan power supply terminal VDS, and the reverse scan power supply terminal VSD are not pulled high during power-off or abnormal power outages.

[0138] During the operation of the shift register, both the third power supply terminal V3 and the fourth power supply terminal V4 provide low-level signals. The operation of the shift register in Embodiment 3 is the same as that in Embodiment 1, and will not be described again here.

[0139] Figure 4 The specific circuit diagram of the shift register provided in Embodiment 4 of this disclosure is as follows: Figure 4As shown, the shift register in Embodiment 4 is similar to that in Embodiment 2, except that in Embodiment 4, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both providing a low-level signal. In Embodiment 4, the second terminals of the first reset transistor M4, the pull-down transistor M6A, the third pull-down control transistor M8A, the sixth pull-down control transistor M8B, and the first noise reduction transistor M10A are all connected to the third power supply terminal V3, and the second terminals of the second reset transistor M7 and the second noise reduction transistor M11A are both connected to the fourth power supply terminal V4.

[0140] During the operation of the shift register, both the third power supply terminal V3 and the fourth power supply terminal V4 provide low-level signals. The operation of the shift register in Embodiment 4 is the same as in Embodiment 2, and will not be described again here.

[0141] Figure 5 The following is a detailed circuit diagram of the shift register provided in Embodiment 5 of this disclosure. The shift register shown in Embodiment 5 is similar to that in Embodiment 1. The differences between the two will be described below.

[0142] like Figure 5 As shown, the first pull-down control sub-circuit 21 includes a first pull-down control transistor M9A. The gate and first terminal of the first pull-down control transistor M9A are both electrically connected to the first power supply terminal VDDO, and the second terminal is electrically connected to the pull-down node PD. The second pull-down control sub-circuit 22 includes a fourth pull-down control transistor M9B. The gate and first terminal of the fourth pull-down control transistor M9B are both electrically connected to the second power supply terminal VDDE, and the second terminal is electrically connected to the pull-down node PD.

[0143] The structure of the remaining sub-circuits is the same as in Embodiment 1, and will not be described again here.

[0144] The shift register in Example 5 operates through a forward scan and a reverse scan. The timing diagram for the forward scan is shown below. Figure 1E Similarly, during the forward scan, the forward scan power supply terminal VDS provides a high-level signal, while the reverse scan power supply terminal VSD provides a low-level signal. The forward scan process includes an input phase, an output phase, a reset phase, and a noise reduction phase.

[0145] During the input phase t1 of the forward scan process, the clock signal provided by the clock signal terminal CLK is at a low level, the first input terminal IN1 provides a high level signal, and the second input terminal IN2 provides a low level signal. At this time, M2 and M16B are turned off; M1 is turned on, thereby starting to charge the storage capacitor C1, that is, the pull-up node PU starts to charge. At the same time, M16A is turned on, thereby pulling down the potential of the pull-down node PD, ensuring that the pull-up node PU can compete with the pull-down node PD. Since the pull-up node PU is at a high level, M3 is turned on, thereby transmitting the low level signal of the clock signal terminal CLK to the signal output terminal Out.

[0146] During the output phase t2 of the forward scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, while the clock signal terminal CLK provides a high-level signal. At this time, M1, M2, M16A, and M16B are turned off. Under the holding effect of the storage capacitor C1, the pull-up node PU remains at a high-level potential, thereby turning on M3 and transmitting the high-level signal of the clock signal terminal CLK to the signal output terminal Out. Simultaneously, M6A is turned on, thereby pulling down the potential of the pull-down node PD, ensuring that the output is complete.

[0147] During the reset phase t3 of the forward scan process, the first input terminal IN1 provides a low-level signal, the second input terminal IN2 provides a high-level signal, and the clock signal terminal CLK provides a low-level signal. At this time, M1 and M16A are off, and M2 is on, thereby pulling the potential of the pull-up node PU low. Simultaneously, M16B is on, pulling the potential of the pull-down node PD high. Since the pull-down node PD is at a high level, M10A and M11A are on, thereby pulling the potential of the pull-up node PU and the signal output terminal Out low. During the noise reduction phase t4 of the forward scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, and the clock signal terminal CLK alternately provides high-level and low-level signals. At this time, M1, M2, M16A, and M16B are all off, and the pull-up node PU maintains the low-level potential of the previous stage, thereby turning off M6A, M8A, and M8B. If the first power supply terminal VDDO provides a high-level signal and the second power supply terminal VDDE provides a low-level signal, then M5B is disconnected and M5A is turned on, thereby connecting the pull-down node PD to the first power supply terminal VDDO, reaching a high-level potential. This, in turn, keeps M10A and M11A on, maintaining the pull-up node PU and signal output terminal Out connected to the second power supply terminal VGL, thus maintaining a low-level potential. If the first power supply terminal VDDO provides a low-level signal and the second power supply terminal VDDE provides a high-level signal, then M5A is off and M5B is on. The pull-down node PD remains at a high-level potential, therefore M10A and M11A are always on, maintaining the pull-up node PU and signal output terminal Out connected to the second power supply terminal, thus maintaining a low-level potential.

[0148] The reverse scan process of the shift register in Example 5 and Figure 1F Similarly, during the reverse scan process, the reverse scan power supply terminal VSD provides a high-level signal, while the forward scan power supply terminal VDS provides a low-level signal. The reverse scan process includes an input phase, an output phase, a reset phase, and a noise reduction phase.

[0149] During the input phase t1 of the reverse scan process, the second input terminal IN2 provides a high-level signal, while the first input terminal IN1 and the clock signal terminal CLK provide low-level signals. At this time, M1 and M16BA are turned off, and M2 is turned on, thus starting to charge the storage capacitor C1, i.e., the pull-up node PU is turned on for charging. Simultaneously, M16B is turned on, pulling down the pull-down node PD to a low-level potential, ensuring that the pull-up node PU can compete with the pull-down node PD. Since the pull-up node PU is at a high-level potential, M3 is turned on, thereby transmitting the low-level signal of the clock signal terminal CLK to the signal output terminal Out.

[0150] During the output phase t2 of the reverse scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, while the clock signal terminal CLK provides a high-level signal. At this time, M1, M2, M16A, and M16B are all turned off. Because the storage capacitor C1 has a holding effect, the pull-up node PU remains at a high level, thereby turning on M3 and transmitting the high-level potential of the clock signal terminal CLK to the signal output terminal Out. Simultaneously, M6A turns on, pulling the pull-down node PD low to a low level, ensuring that the output is complete.

[0151] During the reset phase t3 of the reverse scan process, the first input terminal IN1 and the clock signal terminal CLK provide low-level signals, while the second input terminal IN2 provides a high-level signal. At this time, M2 and M16B are turned off, M1 is turned on, pulling the pull-up node PU low, and M16A is turned on, pulling the pull-down node PD high. At this time, the pull-down node PD is at a high-level potential. M10A and M11A are turned on, pulling the potential of the pull-up node PU and the signal output terminal Out low.

[0152] During the noise reduction phase t4 of the reverse scan process, both the first input terminal IN1 and the second input terminal IN2 provide low-level signals, and the clock signal terminal CLK provides a clock signal that switches between high and low levels. At this time, M1, M2, M16A, and M16B are all off. The pull-up node PU is at a low level, and M6A is off. If the first power supply terminal VDDO provides a high-level signal and the second power supply terminal VDDE provides a low-level signal, then M5B is off, M5A is on, and this connects the pull-down node PD to the first power supply terminal VDDO, achieving a high-level potential. Since the pull-down node PD is at a high level, M10A and M11A remain on, keeping the pull-up node PU and the signal output terminal Out connected to the second-level power supply terminal, thus maintaining a low-level potential. Similarly, if the first power supply terminal VDDO provides a low-level signal and the second power supply terminal VDDE provides a high-level signal, then M5A is turned off and M5B is turned on. The pull-down node PD remains at a high-level potential, so M10A and M11A are always turned on, keeping the pull-up node PU and the signal output terminal Out connected to the second-level power supply terminal, thereby maintaining a low-level potential.

[0153] Figure 6 This is a specific circuit diagram of the shift register provided in Embodiment Six of this disclosure. The shift register shown in Embodiment Six is ​​similar to that in Embodiment Five, except that... Figure 6 The shift register also includes a shift sub-circuit 80 and an auxiliary noise reduction sub-circuit 81. The shift sub-circuit 80 is electrically connected to the pull-up node PU, the clock signal terminal CLK, and the cascaded output terminal Out_C of the shift register. It is configured to transmit the signal from the clock signal terminal CLK to the cascaded output terminal Out_C under the potential control of the pull-up node PU. The auxiliary noise reduction sub-circuit 81 is electrically connected to the pull-down node PD, the cascaded output terminal Out_C, and the fourth power supply terminal V4. It is configured to transmit the signal from the fourth power supply terminal V4 to the cascaded output terminal Out_C under the potential control of the pull-down node PD.

[0154] In Embodiment Six, the third power supply terminal V3 and the fourth power supply terminal V4 are connected to the same second-level power supply terminal VGL.

[0155] In Embodiment Six, the signal output terminal Out of the shift register is electrically connected to the grid lines in the display area to provide a scan signal to the grid lines. The cascaded output terminal Out_C is used to cascade with adjacent shift registers to provide the output signal to the adjacent shift register.

[0156] The shift sub-circuit 80 includes a shift transistor M13, whose gate is electrically connected to the pull-up node PU, its first terminal is electrically connected to the clock signal terminal CLK, and its second terminal is electrically connected to the cascaded output terminal Out_C. The auxiliary noise reduction sub-circuit 81 includes a third noise reduction transistor M12, whose gate is electrically connected to the pull-down node PD, its first terminal is electrically connected to the cascaded output terminal Out_C, and its second terminal is electrically connected to the second-level power supply terminal VGL.

[0157] The signal timing diagram of the shift register during the forward scan process in Example 6 is as follows: Figure 2B Similarly, the signal timing diagram during the reverse scan process is the same as... Figure 2C The on / off states of each transistor in the shift register of Embodiment Six are the same as those described above for Embodiment Five. Specifically, during the input phase of the forward scan process and the input phase of the reverse scan process, shift transistor M13 is turned on, thereby transmitting the low-level signal of the clock signal terminal CLK to the cascaded output terminal Out_C. During the output phase of the forward scan process and the output phase of the reverse scan process, shift transistor M13 is turned on, thereby transmitting the high-level signal provided by the clock signal terminal CLK to the cascaded output terminal Out_C. During the reset and noise reduction phases of the forward scan process, and the reset and noise reduction phases of the reverse scan process, the third noise reduction transistor M12 is turned on, thereby pulling the potential of the cascaded output terminal Out_C down to a low level. That is, the on / off state of shift transistor M13 is the same as that of pull-up transistor M3; the on / off state of the third noise reduction transistor M12 is the same as that of the second noise reduction transistor M11A. The on / off states of the remaining transistors are described in the above description of Embodiment 5, and will not be repeated here.

[0158] Figure 7 This is a specific circuit diagram of the shift register provided in Embodiment Seven of this disclosure. The shift register shown in Embodiment Seven is similar to that in Embodiment Five, except that... Figure 7 In the middle, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both of which provide low-level signals.

[0159] The operation of the shift register in Embodiment 7 is the same as that of the shift register in Embodiment 5, and will not be described again here.

[0160] Figure 8 This is a specific circuit diagram of the shift register provided in Embodiment 8 of this disclosure. The shift register shown in Embodiment 8 is similar to that in Embodiment 6, except that... Figure 8 In the middle, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both of which provide low-level signals.

[0161] The operation of the shift register in Embodiment 8 is the same as that of the shift register in Embodiment 6, and will not be described again here.

[0162] Figure 9 This is a specific circuit diagram of the shift register provided in Embodiment Nine of this disclosure. The shift register shown in Embodiment Nine is similar to that in Embodiment One, except that in Embodiment Nine, the first input sub-circuit 11 is no longer connected to the forward scan input terminal VDS. The first input sub-circuit 11 is configured to transmit the signal provided by the first input terminal IN1 to the pull-up node PU under the signal control of the first input terminal IN1, thereby charging the pull-up node PU. The first input sub-circuit 11 includes a first input transistor M1, whose gate and first terminal are electrically connected to the first input terminal IN1, and its second terminal is electrically connected to the pull-up node PU. In addition, in Embodiment Nine, the second input sub-circuit 12 is connected to the second input terminal IN2, the pull-up node PU, and the third power supply terminal V3, and is configured to transmit the signal from the third power supply terminal V3 to the pull-up node PU under the signal control of the second input terminal IN2. The first gating sub-circuit 71 is also electrically connected to the third power supply terminal V3 and is configured to pull down the potential of the pull-down node PD using the signal from the third power supply terminal V3 under the signal control of the first input terminal IN1.

[0163] The first selection sub-circuit 71 includes a first selection transistor M16A. The gate of the first selection transistor M16A is electrically connected to the first input terminal IN1, the first terminal is electrically connected to the pull-down node PD, and the second terminal is electrically connected to the third power supply terminal V3. When the first input terminal IN1 provides a first level signal, the first selection transistor M16A is turned on, thereby transmitting the second level signal provided by the third power supply terminal V3 to the pull-down node PD.

[0164] The second input sub-circuit 12 includes a second input transistor M2, whose gate is electrically connected to the second input terminal IN2, its first terminal is electrically connected to the pull-up node PU, and its second terminal is electrically connected to the third power supply terminal V3. When the second input terminal IN2 provides a first-level signal, the second input transistor M2 is turned on, thereby transmitting the second-level signal provided by the third power supply terminal V3 to the pull-up node PU, thus resetting the pull-up node PU.

[0165] The shift register in Embodiment 9 can achieve unidirectional scanning, and the timing reference of each signal terminal during the unidirectional scanning process... Figure 1E The unidirectional operation process of Embodiment Nine includes an input stage, an output stage, a reset stage, and a noise reduction stage. The on / off state of the second input transistor M2 is the same as that of the second input transistor M2 in the forward scanning process in Embodiment One. The on / off states of the other transistors in each stage can be found in the description of the forward scanning process in Embodiment One above, and will not be repeated here.

[0166] Figure 10 The following is a detailed circuit diagram of the shift register provided in Embodiment 10 of this disclosure. The shift register in Embodiment 10 is similar to that in Embodiment 9, except that in Embodiment 10, the shift register further includes a shift sub-circuit 80 and an auxiliary noise reduction sub-circuit 81.

[0167] The shift sub-circuit 80 is electrically connected to the pull-up node PU, the clock signal terminal CLK, and the cascaded output terminal Out_C of the shift register. It is configured to transmit the clock signal terminal CLK to the cascaded output terminal Out_C under the potential control of the pull-up node PU. The auxiliary noise reduction sub-circuit 81 is electrically connected to the pull-down node PD, the cascaded output terminal Out_C, and the fourth power supply terminal V4. It is configured to transmit the signal from the fourth power supply terminal V4 to the cascaded output terminal Out_C under the potential control of the pull-down node PD.

[0168] In Embodiment 10, the third power supply terminal V3 and the fourth power supply terminal V4 are connected to the same second-level power supply terminal VGL.

[0169] The shift sub-circuit 80 includes a shift transistor M13, whose gate is electrically connected to the pull-up node PU, its first terminal is electrically connected to the clock signal terminal CLK, and its second terminal is electrically connected to the cascaded output terminal Out_C. The auxiliary noise reduction sub-circuit 81 includes a third noise reduction transistor M12, whose gate is electrically connected to the pull-down node PD, its first terminal is electrically connected to the cascaded output terminal Out_C, and its second terminal is electrically connected to the second-level power supply terminal VGL.

[0170] The operation of the shift register in Embodiment 10 is similar to that in Embodiment 9. The on / off state of the added shift transistor M13 in each stage is the same as that of the pull-up transistor M3 in each stage, and the on / off state of the auxiliary noise reduction transistor in each stage is the same as that of the second noise reduction transistor in each stage.

[0171] Figure 11 Here is a detailed circuit diagram of the shift register provided in Embodiment Eleven of this disclosure, as shown below. Figure 11 As shown, the shift register in Embodiment Eleven is similar to that in Embodiment Ten, except that in Embodiment Eleven, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both of which provide low-level signals.

[0172] Figure 11 The working process of the shift register and Figure 10 The operation of the shift register is the same.

[0173] Figure 12 This is a schematic diagram of the specific circuit of the shift register provided in Embodiment Twelve of this disclosure, as follows: Figure 12As shown, the shift register in Embodiment Twelve is similar to that in Embodiment Eleven, except that in Embodiment Twelve, the shift register further includes a shift sub-circuit 80 and an auxiliary noise reduction sub-circuit 81. The shift sub-circuit 80 is electrically connected to the pull-up node PU, the clock signal terminal CLK, and the cascaded output terminal Out_C of the shift register, and is configured to transmit the signal of the clock signal terminal CLK to the cascaded output terminal Out_C under the potential control of the pull-up node PU. The auxiliary noise reduction sub-circuit 81 is electrically connected to the pull-down node PD, the cascaded output terminal Out_C, and the fourth power supply terminal V4, and is configured to transmit the signal of the fourth power supply terminal V4 to the cascaded output terminal Out_C under the potential control of the pull-down node PD.

[0174] In Example 12, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both of which provide low-level signals.

[0175] In Embodiment Twelve, the shift sub-circuit 80 includes a shift transistor M13, and the auxiliary noise reduction sub-circuit 81 includes a third noise reduction transistor M12. The specific connection relationship between the shift transistor M13 and the third noise reduction transistor M12 is described above in Embodiment Four, and will not be repeated here.

[0176] The operation of the shift register in Embodiment Twelve is similar to that in Embodiment Eleven. The on / off states of the added shift transistor M13 in each stage are the same as those of the pull-up transistor M3 in each stage. The on / off states of the third noise reduction transistor M12 in each stage are the same as those of the second noise reduction transistor M11A in each stage.

[0177] Figure 13 This is a schematic diagram of the specific circuit of the shift register provided in Embodiment Thirteen of this disclosure, as follows: Figure 13 As shown, the shift register of Embodiment Thirteen is similar to that of Embodiment Nine, except that in Embodiment Thirteen, the first pull-down control sub-circuit 21 includes the first pull-down control transistor M9A, but does not include the second pull-down control transistor M5A and the third pull-down control transistor M8A; the second pull-down control sub-circuit 22 includes the fourth pull-down control transistor M9B, but does not include the fifth pull-down control transistor M5B and the sixth pull-down control transistor M8B.

[0178] In this embodiment, the shift register can achieve unidirectional scanning. The unidirectional scanning process includes an input stage, an output stage, a reset stage, and a noise reduction stage. The on / off states of the first pull-down control transistor M9A and the fourth pull-down control transistor M9B in each stage are the same as those of the first pull-down control transistor M9A and the fourth pull-down control transistor M9B in the forward scanning process in embodiment 7. The on / off states of the other transistors in embodiment 13 can be found in the description of embodiment 9, and will not be repeated here.

[0179] Figure 14 This is a schematic diagram of the specific circuit of the shift register provided in Embodiment Fourteen of this disclosure, as shown below. Figure 14 As shown, the shift register of Embodiment Fourteen is similar to that of Embodiment Thirteen. The difference is that in Embodiment Fourteen, the shift register also includes a shift sub-circuit 80 and an auxiliary noise reduction sub-circuit 81, the structure of which is described in Embodiment Twelve.

[0180] The operation of the shift register in Embodiment Fourteen is similar to that in Embodiment Thirteen. The on / off states of the added shift transistor M13 in each stage are the same as those of the pull-up transistor M3 in each stage, and the on / off states of the third noise reduction transistor M12 in each stage are the same as those of the second noise reduction transistor M11A in each stage.

[0181] Figure 15 This is a schematic diagram of the specific circuit of the shift register provided in Embodiment Fifteen of this disclosure, as follows: Figure 15 As shown, the shift register in Embodiment Fifteen is similar to that in Embodiment Thirteen, except that in Embodiment Fifteen, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both providing a low-level signal. The operation of the shift register in Embodiment Fifteen is the same as that in Embodiment Thirteen.

[0182] Figure 16 This is a schematic diagram of the specific circuit of the shift register provided in Embodiment Sixteen of this disclosure, as follows: Figure 16 As shown, the shift register in Embodiment Sixteen is similar to that in Embodiment Fourteen, except that in Embodiment Sixteen, the third power supply terminal V3 and the fourth power supply terminal V4 are two independent power supply terminals, both of which provide a low-level signal. The operation of the shift register in Embodiment Sixteen is the same as that in Embodiment Fourteen.

[0183] This disclosure also simulates the change trend of the threshold voltage (Vth) of the transistor corresponding to the pull-down node PD with the lamp-on time. Figure 17 The graphs show the threshold voltage of the relevant transistors in a shift register with dual PDs and a shift register with a single PD, as a function of the lamp-lighting time. The shift register with a single PD is the shift register with a single pull-down node PD provided in embodiments one through sixteen of this disclosure, and the shift register with dual PDs is... Figure 1A The shift register shown. (Through...) Figure 17 It can be seen that the threshold voltages of M5A, M9A, M5B, and M9B continuously increase with the increase of the lamp-on time. However, the threshold voltages of M10A, M10B, M11A, and M11B in the pull-down sub-circuit become essentially uniform after 1000 hours. Therefore, the shift registers in embodiments one through sixteen of this disclosure are configured as a single pull-down node PD, and the [other function / function] is omitted. Figure 1AThe M10B and M11B in the shift register do not change the lifespan or reliability of the shift register.

[0184] Figure 18 This is a schematic diagram of the gate drive circuit provided in the embodiments of this disclosure, as shown below. Figure 18 As shown, the gate drive circuit includes multiple cascaded shift registers (such as...). Figure 18 SR_1, SR_2, SR_3, SR_4... in the above embodiments, the shift register is the shift register of any of the above embodiments.

[0185] Figure 18 The diagram schematically illustrates the connections between multiple shift registers. When the shift register does not contain a shift sub-circuit 80, in three consecutive shift registers, the signal output terminal Out of the intermediate shift register is electrically connected to the first input terminal IN1 of the next shift register and to the second input terminal IN2 of the previous shift register. Specifically, the clock signal terminal CLK of the odd-numbered shift registers is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the even-numbered shift registers is electrically connected to the second clock signal line CLKB.

[0186] When the shift register contains a shift sub-circuit 80, in a series of three shift registers, the cascaded output terminal Out_C of the intermediate shift register is electrically connected to the first input terminal IN1 of the next shift register and to the second input terminal IN2 of the previous shift register. Specifically, the clock signal terminal CLK of the odd-numbered shift registers is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the even-numbered shift registers is electrically connected to the second clock signal line CLKB.

[0187] Figure 19 This is a signal timing diagram of a gate driving circuit provided in an embodiment of this disclosure. Figure 20 This is another signal timing diagram of the gate driving circuit provided in the embodiments of this disclosure. When the shift register in the gate driving circuit adopts the shift register of embodiments one to eight, the gate driving circuit can achieve bidirectional scanning, wherein... Figure 19 This is a timing diagram of the gate drive circuit during the forward scan process. Figure 20 The timing diagram of the gate drive circuit during the reverse scan process is shown below. Figure 19As shown, during the forward scan, the forward scan power supply VDS continuously provides a high-level signal Vgh, while the reverse scan power supply VSD continuously provides a low-level signal Vgl. During the blanking phase between two adjacent frames (i.e., two adjacent display cycles), a high-level signal is provided to the Total-Rest reset terminal of each shift register, thereby resetting each shift register. In each frame, a high-level frame start signal STV is provided to the first input terminal IN1 of the first-stage shift register, so that under the shifting action of each shift register, each shift register from the first stage to the last stage sequentially outputs a high-level signal. Figure 20 As shown, during the reverse scan process, the reverse scan power supply VSD continuously provides a high-level signal Vgh, while the forward scan power supply VDS continuously provides a low-level signal Vgl. During the blanking phase between two adjacent frames (i.e., two adjacent display cycles), a high-level signal is provided to the Total-Rest reset terminal of each shift register, thereby resetting each shift register. In each frame, a high-level frame start signal STV is provided to the second input terminal IN2 of the last-stage shift register, so that under the shifting action of each shift register, each shift register from the last stage to the first stage sequentially outputs a high-level signal.

[0188] Figure 21 This is another signal timing diagram of the gate driving circuit provided in this embodiment. When the shift register in the gate driving circuit adopts any one of the shift registers in embodiments nine to sixteen, the gate driving circuit can realize unidirectional scanning. The signal timing diagram during the unidirectional scanning process is as follows: Figure 21 As shown. During the blanking phase between two adjacent frames (i.e., two adjacent display cycles), a high-level signal is provided to the Total-Rest terminal of each shift register, thereby resetting each shift register. In each frame, a high-level frame start signal STV is provided to the first input terminal IN1 of the first-stage shift register, so that under the shifting action of each shift register, each shift register from the first stage to the last stage sequentially outputs a high-level signal.

[0189] During the forward scan, reverse scan, and unidirectional scan processes, the signals at the first power supply terminal VDDO and the second power supply terminal VDDE switch between high and low levels. Furthermore, at any given time, when one of the first power supply terminals VDDO and VDDE provides a high-level signal, the other provides a low-level signal. For example, the first power supply terminal VDDO and the second power supply terminal VDDE switch signals every 1 to 3 seconds. Of course, the switching frequency can be adjusted according to actual needs.

[0190] This disclosure also provides a display device, including a display substrate and the gate driving circuit in the above embodiments, wherein the display substrate may include multiple gate lines, and the signal output terminal Out of each shift register in the gate driving circuit is electrically connected to a gate line.

[0191] This disclosure also provides a method for driving a shift register, wherein the operation of the shift register includes a forward scan process, and the driving method includes:

[0192] During the input phase of the forward scanning process, a first level signal is provided to the first input terminal IN1, the first input sub-circuit 11 charges the pull-up node PU, the pull-down sub-circuit 30 transmits the second level signal of the third power supply terminal V3 to the pull-down node PD, and the first gating sub-circuit 71 pulls down the potential of the pull-down node PD.

[0193] During the output phase of the forward scanning process, the pull-up sub-circuit 40 transmits the clock signal CLK to the signal output terminal Out under the control of the pull-up node PU.

[0194] During the noise reduction phase of the forward scanning process, one of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 provides a first level signal to the pull-down node PD. Under the potential control of the pull-down node PD, the noise reduction sub-circuit 50 reduces noise for the pull-up node PU and the signal output terminal Out.

[0195] It should be noted that a shift register can be a shift register that can perform bidirectional scanning or a shift register that can perform unidirectional scanning. When the shift register can only perform unidirectional scanning, the unidirectional scanning process is equivalent to the forward scanning process.

[0196] In some embodiments, the shift register further includes a second input sub-circuit 12 connected to the second input terminal IN2 and the third power supply terminal V3, that is, the shift register is any one of the shift registers in embodiments nine to sixteen described above. In this case, the driving method further includes:

[0197] During the reset phase of the forward scan process, a first level signal is provided to the second input terminal IN2. The second input sub-circuit 12 transmits the second level signal provided by the third power supply terminal V3 to the pull-up node PU. One of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 transmits the first level signal provided by the first power supply terminal VDDO or the second power supply terminal VDDE to the pull-down node PD. The noise reduction sub-circuit 50 reduces noise at the signal output terminal Out under the potential control of the pull-down node PD.

[0198] In other embodiments, the first input sub-circuit 11 is also electrically connected to the forward scan power supply terminal VDS. The shift register further includes a second input sub-circuit 12 and a second gating sub-circuit 72. The second input sub-circuit 12 is electrically connected to the second input terminal IN2, the pull-up node PU, and the reverse scan power supply terminal VSD. The second gating sub-circuit 72 is electrically connected to the second input terminal IN2, the pull-down node PD, and the forward scan power supply terminal VDS. That is, the shift register adopts any one of the structures in embodiments one to eight described above. In this case, the operation of the shift register also includes a reverse scan process, and the driving method further includes:

[0199] During the reset phase of the forward scan process, a first level signal is provided to the second input terminal IN2. The second input sub-circuit 12 transmits the second level signal provided by the reverse scan power supply terminal VSD to the pull-up node PU. One of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 transmits the first level signal provided by the first power supply terminal VDDO or the second power supply terminal VDDE to the pull-down node PD. The noise reduction sub-circuit 50 reduces noise at the signal output terminal Out under the potential control of the pull-down node PD.

[0200] During the input phase of the reverse scan process, a first level signal is provided to the second input terminal IN2, and the second input sub-circuit 12 transmits the first level signal provided by the reverse scan power supply terminal VSD to the pull-up node PU.

[0201] During the output phase of the reverse scan process, the pull-up sub-circuit 40 transmits the clock signal CLK to the signal output terminal Out under the control of the pull-up node PU.

[0202] During the reset phase of the reverse scan process, a first level signal is provided to the first input terminal IN1. The first input sub-circuit 11 transmits the second level signal provided by the forward scan power supply terminal VDS to the pull-up node PU. One of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 transmits the first level signal provided by the first power supply terminal VDDO or the second power supply terminal VDDE to the pull-down node PD. The noise reduction sub-circuit 50 reduces noise at the signal output terminal Out under the potential control of the pull-down node PD.

[0203] During the noise reduction phase of the reverse scanning process, one of the first pull-down control sub-circuit 21 and the second pull-down control sub-circuit 22 provides a first level signal to the pull-down node PD. Under the potential control of the pull-down node PD, the noise reduction sub-circuit 50 reduces noise for the pull-up node PU and the signal output terminal Out.

[0204] The specific working process of the shift register has been described above and will not be repeated here.

[0205] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, characterized in that, include: The first input sub-circuit is electrically connected to the first input terminal and the pull-up node, and is configured to charge the pull-up node under the signal control of the first input terminal; The pull-up sub-circuit is electrically connected to the pull-up node, the signal output terminal of the shift register, and the clock signal terminal, and is configured to transmit the signal from the clock signal terminal to the signal output terminal under the control of the pull-up node. The first pull-down control sub-circuit, electrically connected to the pull-down node and the first power supply terminal, is configured to transmit the signal of the first power supply terminal to the pull-down node under the signal control of the first power supply terminal. The second pull-down control sub-circuit is electrically connected to the pull-down node and the second power supply terminal, and is configured to transmit the signal of the second power supply terminal to the pull-down node under the signal control of the second power supply terminal; wherein the signal of the first power supply terminal and the signal of the second power supply terminal both switch between a first level potential and a second level potential, and at least for a certain period of time, one of the signals of the first power supply terminal and the second power supply terminal is at the first level potential and the other is at the second level potential; A pull-down sub-circuit, electrically connected to the pull-up node, the pull-down node, and the third power supply terminal, is configured to transmit the signal from the third power supply terminal to the pull-down node under the potential control of the pull-up node. A noise reduction sub-circuit, electrically connected to the pull-up node, the pull-down node, and the signal output terminal, is configured to reduce noise at the pull-up node and the signal output terminal under the potential control of the pull-down node. The first gating sub-circuit, electrically connected to the first input terminal and the pull-down node, is configured to pull down the potential of the pull-down node under the signal control of the first input terminal.

2. The shift register according to claim 1, characterized in that, The shift register further includes a second input sub-circuit, which is connected to the second input terminal, the pull-up node, and the third power supply terminal, and is configured to transmit the signal from the third power supply terminal to the pull-up node under the signal control of the second input terminal. The first selection sub-circuit is also electrically connected to the third power supply terminal and is configured to pull down the potential of the pull-down node using the signal from the third power supply terminal under the signal control of the first input terminal.

3. The shift register according to claim 2, characterized in that, The first gating sub-circuit includes: a first gating transistor, the gate of the first gating transistor being electrically connected to the first input terminal, the first terminal being electrically connected to the pull-down node, and the second terminal being electrically connected to the third power supply terminal.

4. The shift register according to claim 2, characterized in that, The second input sub-circuit includes: a second input transistor, the gate of which is electrically connected to the second input terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the third power supply terminal.

5. The shift register according to claim 1, characterized in that, The first input sub-circuit is also electrically connected to the forward scanning power supply terminal and is configured to charge the pull-up node using the signal from the forward scanning power supply terminal under the control of the first input terminal. The shift register also includes: The second input sub-circuit is electrically connected to the second input terminal, the pull-up node, and the reverse scan power supply terminal, and is configured to transmit the signal from the reverse scan power supply terminal to the pull-up node under the signal control of the second input terminal. The second gating sub-circuit, electrically connected to the second input terminal, the pull-down node, and the forward scanning power supply terminal, is configured to transmit the signal from the forward scanning power supply terminal to the pull-down node under the signal control of the second input terminal. The forward scanning power supply provides a first level signal in the forward scanning state and a second level signal in the reverse scanning state; the reverse scanning power supply provides the second level signal in the forward scanning state and the first level signal in the reverse scanning state.

6. The shift register according to claim 5, characterized in that, The first input sub-circuit includes: a first input transistor, the gate of the first input transistor being electrically connected to the first input terminal, the first electrode being electrically connected to the forward scan power supply terminal, and the second electrode being electrically connected to the pull-up node; The second input sub-circuit includes: a second input transistor, the gate of which is electrically connected to the second input terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the reverse scan power supply terminal.

7. The shift register according to claim 5, characterized in that, The first gating sub-circuit includes: a first gating transistor, the gate of the first gating transistor being electrically connected to the first input terminal, the first terminal being electrically connected to the pull-down node, and the second terminal being electrically connected to the reverse scan power supply terminal; The second gating sub-circuit includes: a second gating transistor, the gate of the second gating transistor being electrically connected to the second input terminal, the first terminal being electrically connected to the forward scanning power supply terminal, and the second terminal being electrically connected to the pull-down node.

8. The shift register according to any one of claims 1 to 7, characterized in that, The pull-up sub-circuit includes a pull-up transistor and a storage capacitor. The gate of the pull-up transistor is electrically connected to the pull-up node, the first terminal is electrically connected to the clock signal terminal, and the second terminal is electrically connected to the signal output terminal.

9. The shift register according to any one of claims 1 to 7, characterized in that, The first pull-down control sub-circuit includes: The first pull-down control transistor has its gate and first terminal both electrically connected to the first power supply terminal. The second pull-down control transistor has its gate electrically connected to the second terminal of the first pull-down control transistor, its first terminal electrically connected to the first power supply terminal, and its second terminal electrically connected to the pull-down node. The third pull-down control transistor has its gate electrically connected to the pull-up node, its first terminal electrically connected to the second terminal of the first pull-down control transistor, and its second terminal electrically connected to the third power supply terminal. The second pull-down control sub-circuit includes: The fourth pull-down control transistor, wherein both the gate and the first terminal of the fourth pull-down control transistor are electrically connected to the second power supply terminal; The fifth pull-down control transistor has its gate electrically connected to the second terminal of the fourth pull-down control transistor, its first terminal electrically connected to the second power supply terminal, and its second terminal electrically connected to the pull-down node. The sixth pull-down control transistor has its gate electrically connected to the pull-up node, its first terminal electrically connected to the second terminal of the fourth pull-down control transistor, and its second terminal electrically connected to the third power supply terminal.

10. The shift register according to any one of claims 1 to 7, characterized in that, The first pull-down control sub-circuit includes: a first pull-down control transistor, wherein the gate and first terminal of the first pull-down control transistor are electrically connected to the first power supply terminal, and the second terminal is electrically connected to the pull-down node; The second pull-down control sub-circuit includes: a fourth pull-down control transistor, wherein the gate and first terminal of the fourth pull-down control transistor are electrically connected to the second power supply terminal, and the second terminal is electrically connected to the pull-down node.

11. The shift register according to any one of claims 1 to 7, characterized in that, The pull-down sub-circuit includes: a pull-down transistor, the gate of which is electrically connected to the pull-up node, a first terminal which is electrically connected to the pull-down node, and a second terminal which is electrically connected to the third power supply terminal.

12. The shift register according to any one of claims 1 to 7, characterized in that, The noise reduction sub-circuit includes: The first noise reduction transistor has its gate electrically connected to the pull-down node, its first terminal electrically connected to the pull-up node, and its second terminal electrically connected to the third power supply terminal. The second noise reduction transistor has its gate electrically connected to the pull-down node, its first terminal electrically connected to the signal output terminal, and its second terminal electrically connected to the fourth power supply terminal. The third power supply terminal is electrically connected to the fourth power supply terminal, or the third power supply terminal and the fourth power supply terminal are independent of each other.

13. The shift register according to any one of claims 1 to 7, characterized in that, The shift register also includes: The shift sub-circuit, electrically connected to the pull-up node, the clock signal terminal, and the cascaded output terminal of the shift register, is configured to transmit the signal from the clock signal terminal to the cascaded output terminal under the potential control of the pull-up node. An auxiliary noise reduction sub-circuit, electrically connected to the pull-down node, the cascaded output terminal, and the fourth power supply terminal, is configured to transmit the signal from the fourth power supply terminal to the cascaded output terminal under the potential control of the pull-down node. The third power supply terminal is electrically connected to the fourth power supply terminal, or the third power supply terminal and the fourth power supply terminal are independent of each other.

14. The shift register according to claim 13, characterized in that, The shift sub-circuit includes: a shift transistor, wherein the gate of the shift transistor is electrically connected to the pull-up node, the first terminal is electrically connected to the clock signal terminal, and the second terminal is electrically connected to the cascaded output terminal; The auxiliary noise reduction sub-circuit includes: The third noise reduction transistor has its gate electrically connected to the pull-down node, its first terminal electrically connected to the cascaded output terminal, and its second terminal electrically connected to the fourth power supply terminal.

15. The shift register according to any one of claims 1 to 7, characterized in that, The shift register further includes a reset sub-circuit, which is electrically connected to the reset terminal, the pull-up node, and the signal output terminal, and is configured to reset the potential of the pull-up node and the signal output terminal under the signal control of the reset terminal.

16. The shift register according to claim 15, characterized in that, The reset sub-circuit includes: The first reset transistor has its gate electrically connected to the reset terminal, its first terminal electrically connected to the pull-up node, and its second terminal electrically connected to the third power supply terminal. The second reset transistor has its gate electrically connected to the reset terminal, its first terminal electrically connected to the signal output terminal, and its second terminal electrically connected to the fourth power supply terminal. The third power supply terminal is electrically connected to the fourth power supply terminal, or the third power supply terminal and the fourth power supply terminal are independent of each other.

17. A gate driving circuit, characterized in that, It includes a plurality of cascaded shift registers, wherein the shift registers are any one of claims 1 to 16.

18. A display device, characterized in that, Includes the gate drive circuit as described in claim 17.

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