Power supply voltage protection circuit

Abstract

The utility model relates to the field of power supply voltage protection, in particular to a power supply voltage protection circuit. Comprising a current cut-off circuit and an overcurrent suppression circuit, and the current cut-off circuit comprises a control end, a cut-off triode and a PMOS tube and is used for cutting off a current path. The over-current suppression circuit comprises a voltage stabilizing triode and is used for carrying out over-current suppression on the PMOS tube. The on-off of the PMOS tube is controlled through the control signal of the control end, so that the circuit is cut off in time when the circuit fails, a relay is not needed, and the defects of the relay in response time, installation space and power loss are overcome. Through the arrangement of the voltage stabilizing diode, the voltage stabilizing triode, the current limiting resistor and the protection resistor, the overcurrent flowing through the PMOS tube is inhibited, the service life of the circuit is prolonged, the use safety of the circuit is enhanced, and the circuit is prevented from being damaged by transient peak voltage.

Description

Technical Field

[0001] This application relates to the field of power supply voltage protection, and more particularly to a power supply voltage protection circuit. Background Technology

[0002] In DC power supply systems, faults such as short circuits or overloads can occur, causing equipment to generate enormous heat and potentially damaging it, while also posing safety hazards. Therefore, DC power supply systems are often equipped with power voltage protection circuits to promptly cut off the power supply in the event of a fault. In existing technology, power voltage protection circuits typically consist of relays, which use electromagnetic principles to disconnect contacts in the event of a power failure. However, such devices operating on mechanical principles have a relatively long response time. In high-speed data communication equipment, the power supply may experience instantaneous spikes or surges in voltage, and the relay may fail to provide effective protection due to its delayed response. Furthermore, relays require a large drive current to engage or disengage their contacts, resulting in power loss. Additionally, relays are relatively large, which can hinder installation in devices with limited space. Utility Model Content

[0003] This application provides a power supply voltage protection circuit.

[0004] It includes a current cutoff circuit and an overcurrent suppression circuit. The current cutoff circuit includes a control terminal, a cutoff transistor, and a PMOS transistor. The control terminal is connected to the emitter of the cutoff transistor, the collector of the cutoff transistor is connected to the gate of the PMOS transistor, the base of the cutoff transistor is grounded through a first grounding resistor, the drain of the PMOS transistor is connected to the voltage output terminal, and the source of the PMOS transistor is connected to the voltage input terminal.

[0005] The overcurrent suppression circuit includes a Zener transistor, the gate of which is connected to the collector of the Zener transistor, the emitter of which is connected to the voltage input terminal, the base of which is connected to the first end of a base bias resistor, and the second end of the base bias resistor is connected to the voltage input terminal.

[0006] Specifically, the control terminal is connected to the cut-off transistor via a first Zener diode;

[0007] The control terminal is connected to the positive terminal of the first Zener diode, and the cut-off transistor is connected to the negative terminal of the first Zener diode.

[0008] Specifically, the collector of the cut-off transistor is connected to the gate of the PMOS transistor through a current-limiting resistor and a filter capacitor;

[0009] The collector of the cut-off transistor is connected to the first end of the current-limiting resistor and the first end of the filter capacitor. The second end of the current-limiting resistor is connected to the gate of the PMOS transistor, and the second end of the filter capacitor is connected to the base of the cut-off transistor.

[0010] Specifically, the source of the PMOS transistor is connected to the collector of the Zener transistor through a protection resistor and a second Zener diode;

[0011] The source of the PMOS transistor is connected to the first terminal of the protection resistor and the negative terminal of the second Zener diode. The second terminal of the protection resistor is connected to the gate of the PMOS transistor and the collector of the Zener transistor. The positive terminal of the second Zener diode is connected to the collector of the Zener transistor.

[0012] Specifically, the emitter of the Zener transistor is grounded through a second grounding resistor.

[0013] Specifically, the voltage input terminal is connected to the base bias resistor via an input resistor, wherein the voltage input terminal is connected to the first end of the input resistor, and the second end of the input resistor is connected to the base bias resistor.

[0014] This application has the following technical advantages:

[0015] By controlling the switching of the PMOS transistor through the control signal at the control terminal, the circuit can be cut off in time when there is a circuit fault. This eliminates the need for a relay and makes up for the shortcomings of relays in terms of response time, installation space, and power loss.

[0016] By setting up Zener diodes, Zener transistors, current-limiting resistors, and protection resistors, overcurrent flowing through the PMOS transistor is suppressed, extending the circuit's lifespan, enhancing its safety, and preventing damage from transient voltage spikes. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts.

[0018] Figure 1 This is a circuit diagram of the power supply voltage protection circuit of this application;

[0019] In the diagram, Enable is the control terminal; Vout is the voltage output terminal; Vin is the voltage input terminal; Q1 is a PMOS transistor; Q2 is a Zener transistor; Q3 is a cutoff transistor; R1 is a current-limiting resistor; R2 is a second grounding resistor; R3 is an input resistor; R4 is a base bias resistor; R5 is a protection resistor; R6 is a first grounding resistor; Z1 is a first Zener diode; Z2 is a second Zener diode; and C1 is a filter capacitor. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0021] like Figure 1 As shown, this embodiment includes a current cutoff circuit and an overcurrent suppression circuit. The current cutoff circuit includes a control terminal Enable, a cutoff transistor Q3, and a PMOS transistor Q1. The control terminal Enable is connected to the emitter of the cutoff transistor Q3, the collector of the cutoff transistor Q3 is connected to the gate of the PMOS transistor Q1, the base of the cutoff transistor Q3 is grounded through a first grounding resistor R6, the drain of the PMOS transistor Q1 is connected to the voltage output terminal Vout, and the source of the PMOS transistor Q1 is connected to the voltage input terminal, used to cut off the current path. In this embodiment, the cutoff transistor Q3 is an NPN transistor, and the control terminal is in logic control mode. When the signal input to the control terminal changes, for example, from low level to high level, the cutoff transistor Q3 is turned on, thereby increasing the gate voltage of the PMOS transistor Q1, making the PMOS transistor Q1 in a conducting or partially conducting state, allowing current to flow. When the control terminal changes from high level to low level, the cutoff transistor Q3 will be cut off. At this time, the gate voltage of the PMOS transistor Q1 will decrease, causing the PMOS transistor Q1 to be cut off. The conductive channel between its source (S) and drain (D) will be closed, cutting off the current path of the subsequent circuit and playing the role of controlling the circuit to turn on and off.

[0022] The overcurrent suppression circuit includes a Zener transistor Q2. The source and gate of a PMOS transistor Q1 are connected to the collector of the Zener transistor Q2. The emitter of the Zener transistor Q2 is connected to the voltage input terminal, and the base of the Zener transistor Q2 is connected to the base bias resistor R4. This circuit is used to suppress overcurrent in the PMOS transistor Q1. In this embodiment, the Zener transistor Q2 is an NPN transistor. When an overcurrent occurs in the circuit, the current through Q1 will exceed its rated value. Under overcurrent conditions, the base voltage of the Zener transistor Q2 will decrease, thereby reducing the collector current of the Zener transistor Q2 and consequently reducing the gate voltage of the PMOS transistor Q1. This prevents excessively high voltage from being applied to the gate of the PMOS transistor Q1, thus avoiding damage to the PMOS transistor Q1 due to overvoltage caused by overcurrent. Simultaneously, it narrows the conductive path between the source and drain of the PMOS transistor Q1, further reducing the current flowing through the PMOS transistor Q1, achieving the purpose of overcurrent suppression.

[0023] A first Zener diode Z1 is positioned between the control terminal Enable and the cutoff transistor Q3. The control terminal Enable is connected to the anode of the first Zener diode Z1, and the cutoff transistor Q3 is connected to the cathode of the first Zener diode Z1. When the signal input to the control terminal Enable experiences voltage spikes or fluctuations, the first Zener diode Z1 can limit the voltage within a certain range. Simultaneously, the first Zener diode Z1 also prevents reverse current, filters out low-amplitude interference signals, and avoids false triggering.

[0024] A current-limiting resistor R1 and a filter capacitor C1 are placed between transistor Q3 and PMOS transistor Q1. The collector of transistor Q3 is connected to one end of the current-limiting resistor R1 and the filter capacitor C1. The other end of the current-limiting resistor R1 is connected to the gate of PMOS transistor Q1, and the other end of the filter capacitor C1 is connected to the base of transistor Q3. The filter capacitor C1 filters high-frequency noise in the power supply voltage, providing a more stable DC voltage for subsequent circuits. The filter capacitor C1 and the current-limiting resistor R1 together form an RC delay circuit. When the circuit's operating state changes (such as startup, shutdown, or being affected by external control signals), the charging and discharging process of the filter capacitor C1 will produce a time delay. During charging or discharging, because the capacitor voltage cannot change instantaneously, it will delay the change of the circuit's node voltage for a certain period of time. For example, when a voltage signal is input to the control terminal, the filter capacitor C1 begins to charge, preventing PMOS transistor Q1 from being subjected to a sudden large current surge. The current-limiting resistor R1 can also limit the magnitude of the current. For example, when the transistor Q3 is turned off, the current-limiting resistor R1 can limit the current flowing to the gate of the PMOS transistor Q1.

[0025] A second Zener diode Z2 and a protective resistor R5 are connected between PMOS transistor Q1 and Zener transistor Q2. The source of PMOS transistor Q1 is connected to one end of the protective resistor R5 and the cathode of the second Zener diode Z2. The other end of the protective resistor R5 is connected to the gate of PMOS transistor Q1 and the collector of Zener transistor Q2. The anode of the second Zener diode Z2 is connected to the collector of Zener transistor Q2. When voltage fluctuations or overvoltage occurs, the second Zener diode Z2 begins to reverse break down, discharging excess voltage to prevent damage to the PMOS transistor. When the second Zener diode Z2 is conducting, current flows through it. The protective resistor R5 limits the current flowing through the second Zener diode Z2, preventing excessive current from damaging the second Zener diode Z2 or other related components.

[0026] The emitter of the Zener transistor Q2 is grounded through the second grounding resistor, which protects the circuit and allows for adjustment of the base bias voltage of the Zener transistor Q2.

[0027] An input resistor R3 is connected between the voltage input terminal Vin and the base bias resistor R4. One end of the input resistor R3 is connected to the voltage input terminal Vin, and the other end of the input resistor R3 is connected to the base bias resistor R4. The other end of the input resistor R3 is connected to the source of the PMOS transistor Q1. When the input current increases, R3 limits the current of subsequent circuits and, together with the second grounding resistor R2 and the base bias resistor R4, forms a voltage divider network to adjust the base bias voltage of the Zener transistor Q2. Connecting the input resistor R3 to the source of the PMOS transistor Q1 means that changes in the source voltage of Q1 will affect the voltage across the input resistor R3, thus affecting the base voltage of the Zener transistor Q2. For example, if the conduction level of the PMOS transistor Q1 decreases, its source voltage increases, and the voltage drop across the input resistor R3 decreases, thereby increasing the base voltage of the Zener transistor Q2, reducing its conduction level, and thus regulating the circuit to achieve a protection function.

[0028] Obviously, the embodiments described above are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] It should be understood that when the terms "first," "second," etc., are used in the claims, description, and drawings of this application, they are only used to distinguish different objects and not to describe a specific order. The terms "comprising" and "including" used in the description and claims of this application indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

Claims

1. A power supply voltage protection circuit, comprising a current cutoff circuit and an overcurrent suppression circuit, wherein the current cutoff circuit comprises a control terminal, a cutoff transistor and a PMOS transistor, the control terminal is connected to the emitter of the cutoff transistor, the collector of the cutoff transistor is connected to the gate of the PMOS transistor, the base of the cutoff transistor is grounded through a first grounding resistor, the drain of the PMOS transistor is connected to a voltage output terminal, and the source of the PMOS transistor is connected to a voltage input terminal; The overcurrent suppression circuit includes a Zener transistor, the gate of which is connected to the collector of the Zener transistor, the emitter of which is connected to the voltage input terminal, the base of which is connected to the first end of a base bias resistor, and the second end of the base bias resistor is connected to the voltage input terminal.

2. The power supply voltage protection circuit according to claim 1, characterized in that, The control terminal is connected to the cut-off transistor via a first Zener diode. The control terminal is connected to the positive terminal of the first Zener diode, and the cut-off transistor is connected to the negative terminal of the first Zener diode.

3. The power supply voltage protection circuit according to claim 1, characterized in that, The collector of the cut-off transistor is connected to the gate of the PMOS transistor through a current-limiting resistor and a filter capacitor. The collector of the cut-off transistor is connected to the first end of the current-limiting resistor and the first end of the filter capacitor. The second end of the current-limiting resistor is connected to the gate of the PMOS transistor, and the second end of the filter capacitor is connected to the base of the cut-off transistor.

4. The power supply voltage protection circuit according to claim 1, characterized in that, The source of the PMOS transistor is connected to the collector of the Zener transistor through a protection resistor and a second Zener diode. The source of the PMOS transistor is connected to the first terminal of the protection resistor and the negative terminal of the second Zener diode. The second terminal of the protection resistor is connected to the gate of the PMOS transistor and the collector of the Zener transistor. The positive terminal of the second Zener diode is connected to the collector of the Zener transistor.

5. The power supply voltage protection circuit according to claim 1, characterized in that, The emitter of the Zener transistor is grounded through a second grounding resistor.

6. The power supply voltage protection circuit according to claim 1, characterized in that, The voltage input terminal is connected to the base bias resistor via an input resistor, wherein the voltage input terminal is connected to the first end of the input resistor, and the second end of the input resistor is connected to the base bias resistor.

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