Video conversion circuit of optical waveguide display screen

Abstract

The utility model discloses a video conversion circuit of an optical waveguide display screen, which comprises an MCU, the data transmission end of the MCU is connected with the data transmission end of a level conversion module, the data transmission end of the level conversion module is connected with the data transmission end of an optical machine, and the data sending end of a high-speed differential transceiver LVDS is connected with the data receiving end of a filtering module LVDS. The LVDS data transmitting end of the filtering module is connected with the LVDS data receiving end of the video bridging chip U7, and the MIPI data transmitting end of the video bridging chip U7 is connected with the MIPI data receiving end of the optical machine. Signal conversion and display can be stably carried out.

Description

Technical Field

[0001] This utility model relates to the field of optical waveguide display technology, specifically to a video conversion circuit for an optical waveguide display screen. Background Technology

[0002] With the development of automotive technology, people are increasingly valuing the functionality of cars. Traditionally, sun visors integrate displays, giving them a display function and improving vehicle comfort. However, current displays typically transmit signals via cables, making their image quality susceptible to interference from the external environment. This can result in displays failing to display or displaying poor quality, thus reducing viewing comfort.

[0003] Optical waveguide technology guides a light beam to the user's eyes through total internal reflection, enabling superimposed image display and thus providing a better viewing experience. However, since traditional displays rely on cables for signal transmission, and the signals transmitted via cables differ from those transmitted via optical waveguides, a conversion circuit capable of stable display is urgently needed. Utility Model Content

[0004] This utility model aims to solve the technical problems existing in the prior art, and innovatively proposes a video conversion circuit for an optical waveguide display screen, which can stably perform signal conversion and display.

[0005] To achieve the above objectives, this utility model provides a video conversion circuit for an optical waveguide display screen, including an MCU. The data transmission terminal of the MCU is connected to the data transmission terminal of a level conversion module, which is connected to the data transmission terminal of an optomechanical system. The data transmission terminal of a high-speed differential transceiver (LVDS) is connected to the data receiving terminal of a filter module (LVDS). The data transmission terminal of the filter module (LVDS) is connected to the data receiving terminal of a video bridging chip (U7LVDS), which is connected to the data receiving terminal of an optomechanical system (U7MIPI).

[0006] The above scheme also includes a wake-up circuit, wherein the low-dropout wake-up signal output terminal of the wake-up circuit is connected to the power supply module, the wake-up sampling signal output terminal of the wake-up circuit is connected to the wake-up sampling signal input terminal of the MCU, and the system wake-up signal output terminal of the wake-up circuit is connected to the system wake-up signal input terminal of the MCU.

[0007] In the above scheme: the wake-up circuit includes diode D3. The positive terminal of diode D3 is connected to the vehicle wake-up signal output terminal, and the negative terminal of diode D3 is the low-dropout wake-up signal output terminal. It is connected to one end of resistor R73 and one end of resistor R59. The other end of resistor R59 is the wake-up sampling signal output terminal, and is connected to one end of resistor R60, one end of capacitor C59 and the MCU wake-up sampling signal input terminal. The other ends of resistor R60 and capacitor C59 are both connected to power ground.

[0008] The other end of resistor R73 is connected to one end of resistor R56, one end of capacitor C61, and the base of transistor Q1. The emitter of transistor Q1, the other end of resistor R56, and the other end of capacitor C61 are all connected to the power supply ground. The collector of transistor Q1 is connected to one end of resistor R58. The other end of resistor R58 is connected to one end of resistor R3 and the base of transistor Q19. The other end of resistor R3 and the emitter of transistor Q19 are both connected to the 3.3V MCU power supply terminal. The collector of transistor Q19 is the system wake-up signal output terminal of the wake-up circuit, which is connected to one end of resistor R2, one end of capacitor C2, and the MCU wake-up signal input terminal.

[0009] The above solution also includes a power supply module, which comprises a DC-DC conversion circuit, a step-down circuit, a differential voltage regulation circuit, and a battery sampling circuit.

[0010] In the above scheme: the DC-DC conversion circuit includes a DC-DC converter. The voltage input terminal of the DC-DC converter is connected to one end of resistor R115, one end of capacitor C53, one end of capacitor C58, and one end of capacitor C54. The other ends of capacitors C53, C58, and C54 are all connected to power ground. The other end of resistor R115 is connected to the battery operating voltage output terminal. The enable terminal of the DC-DC converter is connected to the MCU 3.3V switch enable signal output terminal and one end of resistor R51. The other end of resistor R51 is connected to power ground.

[0011] The clock terminal of the DC-DC converter is connected to one end of resistor R74, the SS terminal of the DC-DC converter is connected to one end of capacitor C92 and one end of capacitor C56, the other end of capacitor C92 is connected to one end of resistor R101, and one end of resistor R74, one end of resistor R101, one end of capacitor C56 and the ground terminal of the DC-DC converter are all connected to the power supply ground.

[0012] The bias terminal of the DC-DC converter is connected to one end of resistor R52, the other end of resistor R52 is connected to one end of capacitor C48, the other end of capacitor C48 is connected to one end of resistor R64, the other end of resistor R64 is connected to one end of capacitor C57, and the other end of capacitor C57 is connected to power ground.

[0013] The output terminal of the DC-DC converter's voltage regulator switch is connected to one end of inductor L6 and the negative terminal of diode D2. The positive terminal of diode D2 is connected to the power supply ground. The other end of inductor L6 is connected to one end of capacitor C49, one end of capacitor C50, one end of capacitor C51, and one end of capacitor C52. The other ends of capacitors C49, C50, C51, and C52 are all connected to the power supply ground. The other end of inductor L6 is the DC-DC conversion voltage output terminal of the DC-DC conversion circuit, outputting a 3.3V voltage. The other end of inductor L6 is also connected to one end of resistor R65. The other end of resistor R65 is the MCU power supply terminal of the DC-DC conversion circuit, used to output a 3.3V voltage, and connected to the internal voltage input terminal of the MCU.

[0014] The feedback terminal of the DC-DC converter is connected to one end of resistor R63 and one end of resistor R61. The other end of resistor R63 is connected to the power supply ground. The other end of resistor R61 is connected to one end of resistor R62 and the other end of resistor R61 is connected to the other end of inductor L6.

[0015] In the above scheme: the step-down circuit includes a step-down chip. The power input terminal of the step-down chip is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit, one end of resistor R72, and one end of capacitor C69. The other end of resistor R72 is connected to the enable terminal of the step-down chip. The other end of capacitor C69 is connected to the power ground. The NR terminal of the step-down chip is connected to one end of capacitor C8. The other end of capacitor C8 and the ground terminal of the step-down chip are both connected to the power ground. The step-down output terminal of the step-down chip is used to output a 1.8V voltage and is connected to one end of resistor R13, one end of capacitor C7, and one end of capacitor C68. The other end of capacitor C68 is connected to the power ground. The other ends of resistor R13 and capacitor C7 are connected to the feedback terminal of the step-down chip and one end of resistor R76. The other end of resistor R76 is connected to the power ground.

[0016] The differential pressure regulation circuit includes a low-dropout regulator. The power input terminal of the low-dropout regulator is connected to the negative terminal of diode D13, one end of capacitor C124, one end of capacitor C116, one end of capacitor C118, and one end of capacitor C123. The other ends of capacitors C124, C116, C118, and C123 are all connected to power ground. The positive terminal of diode D13 is connected to the battery power supply terminal. The enable signal terminal of the low-dropout regulator is connected to the third terminal of switching diode D1 and one end of resistor R116. The other end of resistor R116 and the ground terminal of the low-dropout regulator are both connected to power ground. The first terminal of switching diode D1 is connected to one end of resistor R31 and one end of capacitor C114. The other end of capacitor C114 is connected to power ground. The other end of resistor R31 is connected to the low-dropout wake-up signal output terminal of the wake-up circuit. The second terminal of switching diode D1 is connected to the MCU 3.3V switch enable signal output terminal.

[0017] The battery sampling circuit includes a resistor R69. One end of the resistor R69 is connected to the MCU battery sampling enable signal output terminal. The other end of the resistor R69 is connected to one end of the resistor R70, one end of the capacitor C1, and the base of the transistor Q3. The other ends of the resistor R70, the other end of the capacitor C1, and the emitter of the transistor Q3 are all connected to the power supply ground. The collector of the transistor Q3 is connected to one end of the resistor R66 and one end of the resistor R215. The other end of the resistor R66 is connected to one end of the resistor R71 and the base of the transistor Q2. The other end of the resistor R71 and the emitter of the transistor Q2 are both connected to the battery power supply terminal. The collector of the transistor Q2 is connected to one end of the resistor R67. The other end of the resistor R67 is the battery sampling signal output terminal of the battery sampling circuit, and is connected to one end of the resistor R68, one end of the capacitor C67, and the MCU battery sampling signal input terminal. The other ends of the resistor R68 and the other end of the capacitor C67 are both connected to the power supply ground.

[0018] The other end of resistor R215 is connected to one end of resistor R218 and the base of transistor Q16. The other end of resistor R218 and the emitter of transistor Q16 are both connected to the battery power supply terminal. The collector of transistor Q16 is connected to one end of resistor R217. The other end of resistor R217 is the DC bus sampling signal output terminal of the battery sampling circuit, and is connected to one end of resistor R216, one end of capacitor C141 and the DC bus sampling signal input terminal of MCU. The other ends of resistor R216 and capacitor C141 are both connected to power ground.

[0019] In the above scheme: the input / output voltage terminals of the high-speed differential transceiver are connected to one end of inductor L2, one end of capacitor C11, one end of capacitor C12, one end of capacitor C13, and one end of capacitor C14; the other ends of capacitors C11, C12, C13, and C14 are all connected to power ground; the other end of inductor L2 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit; the operating voltage terminal of the high-speed differential transceiver is connected to one end of inductor L7, one end of capacitor C22, one end of capacitor C23, one end of capacitor C24, and one end of capacitor C14. One end of capacitor C25, one end of capacitor C26, one end of capacitor C27, and one end of capacitor C28; the other ends of capacitors C22, C23, C24, C25, C26, C27, and C28 are all connected to the power supply ground; the other end of inductor L7 is connected to the voltage output terminal of the step-down circuit; the first terminal of the high-speed differential transceiver crystal oscillator is connected to one end of resistor R14, one end of capacitor C35, and the third terminal of crystal oscillator Y2; the fourth terminal of crystal oscillator Y2 and the other end of capacitor C35 are connected to the power supply ground. The second terminal of the high-speed differential transceiver crystal oscillator is connected to the other end of resistor R14, one end of capacitor C29, and the first terminal of crystal oscillator Y2. The second terminal of crystal oscillator Y2 and the other end of capacitor C29 are both connected to power ground. The SIOB+ terminal of the high-speed differential transceiver is connected to one end of capacitor C38, the other end of capacitor C38 is connected to one end of resistor R17, and the other end of resistor R17 is connected to power ground. The SIOB- terminal of the high-speed differential transceiver is connected to one end of capacitor C42, the other end of capacitor C42 is connected to one end of resistor R18, and the other end of resistor R18 is connected to power ground. The PWDN high-speed differential transceiver... Terminal B is connected to one end of resistor R21, one end of resistor R230, and one end of capacitor C153. The other end of capacitor C153 is connected to the power ground. The other end of resistor R230 is connected to the voltage terminal of the input / output port of the high-speed differential transceiver. The other end of resistor R21 is connected to the MCU PTE1 / LPSPI0 terminal. The serial clock terminal of the high-speed differential transceiver is connected to one end of resistor R81 and one end of resistor R20. The other end of resistor R81 is connected to the voltage terminal of the input / output port of the high-speed differential transceiver. The other end of resistor R20 is connected to the low-voltage differential signal transmission terminal of the MCU.The high-speed differential transceiver's serial data input is connected to one end of resistor R11, and the other end of resistor R11 is connected to the Bluetooth chip's serial data output. The high-speed differential transceiver's serial word select input is connected to one end of resistor R233, and the other end of resistor R233 is connected to the MCU PTD16 terminal. The high-speed differential transceiver's I2C serial data receiver is connected to one end of resistor R30, and the other end of resistor R30 is connected to the MCU I2C serial data transmitter. The high-speed differential transceiver's I2C serial data clock is connected to one end of resistor R36, and the other end of resistor R36 is connected to the MCU I2C serial data clock. The high-speed differential transceiver is general-purpose. The input / output terminals are connected to one end of resistor R38. The other end of resistor R38 is connected to the low-voltage differential reset terminal of the MCU. The high-impedance terminal of the high-speed differential transceiver is connected to one end of resistor R32. The other end of resistor R32 is connected to the PTE7 terminal of the MCU. The power supply terminal of the digital regulator of the high-speed differential transceiver is connected to one end of inductor L5, one end of capacitors C15, C16, C17, C18, and one end of capacitor C19. The other ends of capacitors C15, C16, C17, C18, and C19 are all connected to power ground. The other end of inductor L5 is connected to the voltage output terminal of the step-down circuit.

[0020] In the above scheme: the filtering module includes common-mode filter L15, common-mode filter L16, common-mode filter L17, common-mode filter L18, common-mode filter L19, common-mode filter L10, common-mode filter L14, common-mode filter L13, common-mode filter L12 and common-mode filter L11;

[0021] The positive terminal of the first group of LVDS data output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L15, the negative terminal of the first group of LVDS data output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L15, the third terminal of the common-mode filter L15 is connected to the positive terminal of the first group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L15 is connected to the negative terminal of the first group of differential signal input of the video bridge chip U7.

[0022] The positive terminal of the second group of LVDS data output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L16, the negative terminal of the second group of LVDS data output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L16, the third terminal of the common-mode filter L16 is connected to the positive terminal of the second group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L16 is connected to the negative terminal of the second group of differential signal input of the video bridge chip U7.

[0023] The positive terminal of the third group of LVDS data output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L17, the negative terminal of the third group of LVDS data output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L17, the third terminal of the common-mode filter L17 is connected to the positive terminal of the third group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L17 is connected to the negative terminal of the third group of differential signal input of the video bridge chip U7.

[0024] The positive terminal of the fourth group of LVDS data output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L18, the negative terminal of the fourth group of LVDS data output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L18, the third terminal of the common-mode filter L18 is connected to the positive terminal of the fourth group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L18 is connected to the negative terminal of the fourth group of differential signal input of the video bridge chip U7.

[0025] The positive terminal of the LVDS clock signal of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L19, the negative terminal of the LVDS clock signal of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L19, the third terminal of the common-mode filter L19 is connected to the positive terminal of the clock input of the video bridge chip U7LVDS, and the fourth terminal of the common-mode filter L19 is connected to the negative terminal of the clock input of the video bridge chip U7LVDS.

[0026] The positive terminal of the first group of differential signal output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L14, the negative terminal of the first group of differential signal output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L14, the third terminal of the common-mode filter L14 is connected to the positive terminal of the first group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L14 is connected to the negative terminal of the first group of differential signal input of the video bridge chip U7.

[0027] The positive terminal of the second group of differential signal output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L13, the negative terminal of the second group of differential signal output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L16, the third terminal of the common-mode filter L13 is connected to the positive terminal of the second group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L13 is connected to the negative terminal of the second group of differential signal input of the video bridge chip U7.

[0028] The positive terminal of the third differential signal output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L11, the negative terminal of the third differential signal output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L11, the third terminal of the common-mode filter L11 is connected to the positive terminal of the third differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L11 is connected to the negative terminal of the third differential signal input of the video bridge chip U7.

[0029] The positive terminal of the fourth differential signal output of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L10, the negative terminal of the fourth differential signal output of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L10, the third terminal of the common-mode filter L10 is connected to the positive terminal of the fourth differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L10 is connected to the negative terminal of the fourth differential signal input of the video bridge chip U7.

[0030] The positive terminal of the differential clock signal of the high-speed differential transceiver is connected to the second terminal of the common-mode filter L12, the negative terminal of the differential clock signal of the high-speed differential transceiver is connected to the first terminal of the common-mode filter L12, the third terminal of the common-mode filter L12 is connected to the positive terminal of the differential clock input of the video bridge chip U7, and the fourth terminal of the common-mode filter L12 is connected to the negative terminal of the differential clock input of the video bridge chip U7.

[0031] In the above scheme: the open-drain lockout indicator output terminal of the high-speed differential transceiver is connected to one end of resistor R128 and one end of resistor R22. The other end of resistor R128 is connected to the voltage terminal of the input / output port of the high-speed differential transceiver. The other end of resistor R22 is connected to the MCUDES lockout terminal. The open-drain error indicator output terminal of the high-speed differential transceiver is connected to one end of resistor R26 and one end of resistor R102. The other end of resistor R102 is connected to the voltage terminal of the input / output port of the high-speed differential transceiver (U1). The other end of resistor R26 is connected to the MCUDES error terminal.

[0032] The video bridging chip U7 MIPI data transmission terminal is connected to the optomechanical MIPI data transmission terminal; the video conversion clock terminal of the video bridging chip U7 is connected to one end of resistor R117, the other end of resistor R117 is connected to one end of resistor R118 and the video conversion clock input terminal of level converter U14, the video conversion clock output terminal of level converter U14 is connected to the optomechanical video conversion clock input terminal, and the other end of resistor R118 is connected to the DC conversion voltage output terminal of DC-DC conversion circuit;

[0033] The video bridging chip U7's video conversion data terminal is connected to one end of resistor R122. The other end of resistor R122 is connected to one end of resistor R123 and the video conversion data input terminal of level converter U14. The video conversion data output terminal of level converter U14 is connected to the video conversion data input terminal of the optical engine. The other end of resistor R123 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit. The video conversion reset terminal of video bridging chip U7 is connected to one end of resistor R124. The other end of resistor R124 is connected to the MCU video conversion reset terminal. The video bridging chip U7's INT terminal is connected to one end of resistor R136. The other end of resistor R136 is connected to the MCUCONV INT terminal. The MCUDLP Display ON terminal is connected to the level converter U13DLP Display ON terminal, which is connected to the optical engine Display ON terminal. The MCUDLP Status terminal is connected to the level converter U13DLP Status terminal, which is connected to the optical engine DLP Status terminal. The MCUOption 1 terminal is connected to the level converter U13DLP Option 1. At terminal 1, the level converter U13 Option 1 is connected to the optomechanical Option 1 terminal; the MCU PROG EN terminal is connected to the level converter U14 PROG EN terminal, the level converter U14 SPI_Flash_PROG_EN terminal is connected to the optomechanical SPI_Flash_PROG_EN terminal, the MCU FPGA RST terminal is connected to the level converter U14 MCU FPGA RST terminal, and the level converter U14 FPGA RST terminal is connected to the optomechanical FPGA RST terminal.

[0034] In summary, the beneficial effects of this utility model are: it can stably convert electrical signals into optical signals for imaging and display, ensuring display quality and improving viewing comfort. The filtering module can filter out noise during transmission, and the level conversion module can effectively convert electrical signals to ensure stable signal transmission between the video bridging chip and the optical engine. Attached Figure Description

[0035] Figure 1 This is a system diagram of this utility model.

[0036] Figure 2 This is a circuit diagram of a DC-DC converter circuit.

[0037] Figure 3 This is the circuit diagram of a step-down circuit.

[0038] Figure 4This is a circuit diagram of a voltage sampling circuit.

[0039] Figure 5 This is the circuit diagram of an MCU.

[0040] Figure 6 This is a circuit diagram of a high-speed differential transceiver.

[0041] Figure 7 This is the circuit diagram of the filter module.

[0042] Figure 8 This is the circuit diagram of the video bridging chip U7.

[0043] Figure 9 This is the circuit diagram of level converter U13.

[0044] Figure 10 This is the circuit diagram of level converter U14.

[0045] Figure 11 This is the circuit diagram of the wake-up circuit. Detailed Implementation

[0046] The present invention will be further described below with reference to embodiments and accompanying drawings:

[0047] like Figures 1 to 11 As shown, a video conversion circuit for an optical waveguide display screen includes an MCU U6. The data transmission terminal of the MCU U6 is connected to the data transmission terminal of a level conversion module, which is connected to the data transmission terminal of an optomechanical system. The data transmission terminal of a high-speed differential transceiver U1LVDS is connected to the data receiving terminal of a video bridge chip U7LVDS, which is connected to the data receiving terminal of an optomechanical system.

[0048] It also includes a wake-up circuit, which includes a diode D3. The positive terminal of diode D3 is connected to the vehicle wake-up signal output terminal, and the negative terminal of diode D3 is the low-dropout wake-up signal output terminal. It is connected to one end of resistor R73 and one end of resistor R59. The other end of resistor R59 is the wake-up sampling signal output terminal, and is connected to one end of resistor R60, one end of capacitor C59 and the wake-up sampling signal input terminal of MCUU6. The other ends of resistor R60 and capacitor C59 are both connected to power ground.

[0049] The other end of resistor R73 is connected to one end of resistor R56, one end of capacitor C61, and the base of transistor Q1. The emitter of transistor Q1, the other end of resistor R56, and the other end of capacitor C61 are all connected to the power supply ground. The collector of transistor Q1 is connected to one end of resistor R58. The other end of resistor R58 is connected to one end of resistor R3 and the base of transistor Q19. The other end of resistor R3 and the emitter of transistor Q19 are both connected to the 3.3V MCU power supply terminal. The collector of transistor Q19 is the system wake-up signal output terminal of the wake-up circuit, which is connected to one end of resistor R2, one end of capacitor C2, and the MCUU6 wake-up signal input terminal.

[0050] The DC-DC conversion circuit includes a DC-DC converter U2. The voltage input terminal of the DC-DC converter U2 is connected to one end of resistor R115, one end of capacitor C53, one end of capacitor C58, and one end of capacitor C54. The other ends of capacitors C53, C58, and C54 are all connected to the power supply ground. The other end of resistor R115 is connected to the battery operating voltage output terminal. The enable terminal of the DC-DC converter U2 is connected to the 3.3V switch enable signal output terminal of MCU U6 and one end of resistor R51. The other end of resistor R51 is connected to the power supply ground.

[0051] The clock terminal of DC-DC converter U2 is connected to one end of resistor R74. The SS terminal of DC-DC converter U2 is connected to one end of capacitor C92 and one end of capacitor C56. The other end of capacitor C92 is connected to one end of resistor R101. One end of resistor R74, one end of resistor R101, one end of capacitor C56, and the ground terminal of DC-DC converter U2 are all connected to the power supply ground.

[0052] The bias terminal of DC-DC converter U2 is connected to one end of resistor R52, the other end of resistor R52 is connected to one end of capacitor C48, the other end of capacitor C48 is connected to one end of resistor R64, the other end of resistor R64 is connected to one end of capacitor C57, and the other end of capacitor C57 is connected to power ground.

[0053] The output terminal of the DC-DC converter U2's voltage regulator switch is connected to one end of inductor L6 and the negative terminal of diode D2. The positive terminal of diode D2 is connected to the power supply ground. The other end of inductor L6 is connected to one end of capacitor C49, one end of capacitor C50, one end of capacitor C51, and one end of capacitor C52. The other ends of capacitors C49, C50, C51, and C52 are all connected to the power supply ground. The other end of inductor L6 is the DC-DC conversion voltage output terminal of the DC-DC conversion circuit, outputting a 3.3V voltage. The other end of inductor L6 is also connected to one end of resistor R65. The other end of resistor R65 is the MCU power supply terminal of the DC-DC conversion circuit, used to output a 3.3V voltage, and connected to the internal voltage input terminal of MCU U6.

[0054] The feedback terminal of DC-DC converter U2 is connected to one end of resistor R63 and one end of resistor R61. The other end of resistor R63 is connected to the power supply ground. The other end of resistor R61 is connected to one end of resistor R62. The other end of resistor R61 is connected to the other end of inductor L6.

[0055] The step-down circuit includes a step-down chip U4. The power input terminal of the step-down chip U4 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit, one end of resistor R72, and one end of capacitor C69. The other end of resistor R72 is connected to the enable terminal of the step-down chip U4, and the other end of capacitor C69 is connected to the power ground. The NR terminal of the step-down chip U4 is connected to one end of capacitor C8. The other end of capacitor C8 and the ground terminal of the step-down chip U4 are both connected to the power ground. The step-down output terminal of the step-down chip U4 is used to output a 1.8V voltage and is connected to one end of resistor R13, one end of capacitor C7, and one end of capacitor C68. The other end of capacitor C68 is connected to the power ground. The other ends of resistor R13 and capacitor C7 are connected to the feedback terminal of the step-down chip U4 and one end of resistor R76. The other end of resistor R76 is connected to the power ground.

[0056] The differential pressure regulation circuit includes a low-dropout regulator U5. The power input terminal of the low-dropout regulator U5 is connected to the negative terminal of diode D13, one end of capacitor C124, one end of capacitor C116, one end of capacitor C118, and one end of capacitor C123. The other ends of capacitors C124, C116, C118, and C123 are all connected to the power ground. The positive terminal of diode D13 is connected to the battery power supply terminal. The enable signal terminal of the low-dropout regulator U5 is connected to the third terminal of switching diode D1 and one end of resistor R116. The other end of resistor R116 and the ground terminal of the low-dropout regulator U5 are both connected to the power ground. The first terminal of switching diode D1 is connected to one end of resistor R31 and one end of capacitor C114. The other end of capacitor C114 is connected to the power ground. The other end of resistor R31 is connected to the low-dropout wake-up signal output terminal of the wake-up circuit. The second terminal of switching diode D1 is connected to the 3.3V switch enable signal output terminal of MCU U6.

[0057] The battery sampling circuit includes resistor R69. One end of resistor R69 is connected to the battery sampling enable signal output terminal of MCUU6. The other end of resistor R69 is connected to one end of resistor R70, one end of capacitor C1, and the base of transistor Q3. The other ends of resistor R70, capacitor C1, and the emitter of transistor Q3 are all connected to the power supply ground. The collector of transistor Q3 is connected to one end of resistor R66 and one end of resistor R215. The other end of resistor R66 is connected to one end of resistor R71 and the base of transistor Q2. The other end of resistor R71 and the emitter of transistor Q2 are both connected to the battery power supply terminal. The collector of transistor Q2 is connected to one end of resistor R67. The other end of resistor R67 is the battery sampling signal output terminal of the battery sampling circuit, and is connected to one end of resistor R68, one end of capacitor C67, and the battery sampling signal input terminal of MCUU6. The other ends of resistor R68 and capacitor C67 are both connected to the power supply ground.

[0058] The other end of resistor R215 is connected to one end of resistor R218 and the base of transistor Q16. The other end of resistor R218 and the emitter of transistor Q16 are both connected to the battery power supply terminal. The collector of transistor Q16 is connected to one end of resistor R217. The other end of resistor R217 is the DC bus sampling signal output terminal of the battery sampling circuit, and is connected to one end of resistor R216, one end of capacitor C141 and the DC bus sampling signal input terminal of MCUU6. The other ends of resistor R216 and capacitor C141 are both connected to power ground.

[0059] The input / output voltage terminals of the high-speed differential transceiver U1 are connected to one end of inductor L2, one end of capacitors C11, C12, C13, and C14. The other ends of capacitors C11, C12, C13, and C14 are all connected to the power supply ground. The other end of inductor L2 is connected to the DC-DC converter voltage output terminal. The operating voltage terminals of the high-speed differential transceiver U1 are connected to one end of inductor L7, one end of capacitor C22, one end of capacitor C23, one end of capacitor C24, and one end of capacitor C25. One end of capacitor C26, one end of capacitor C27, and one end of capacitor C28; the other ends of capacitors C22, C23, C24, C25, C26, C27, and C28 are all connected to the power supply ground. The other end of inductor L7 is connected to the voltage output terminal of the step-down circuit. The first terminal of the high-speed differential transceiver U1 crystal oscillator is connected to one end of resistor R14, one end of capacitor C35, and the third terminal of crystal oscillator Y2. The fourth terminal of crystal oscillator Y2 and the other end of capacitor C35 are connected to the power supply ground. The second terminal is connected to the other end of resistor R14, one end of capacitor C29, and the first terminal of crystal oscillator Y2. The second terminal of crystal oscillator Y2 and the other end of capacitor C29 are both connected to power ground. The high-speed differential transceiver U1SIOB+ terminal is connected to one end of capacitor C38. The other end of capacitor C38 is connected to one end of resistor R17. The other end of resistor R17 is connected to power ground. The high-speed differential transceiver U1SIOB- terminal is connected to one end of capacitor C42. The other end of capacitor C42 is connected to one end of resistor R18. The other end of resistor R18 is connected to power ground. The high-speed differential transceiver U1PWDNB terminal is connected to a resistor... One end of R21, one end of resistor R230, and one end of capacitor C153 are connected. The other end of capacitor C153 is connected to the power supply ground. The other end of resistor R230 is connected to the voltage terminal of the input / output port of high-speed differential transceiver U1. The other end of resistor R21 is connected to the PTE1 / LPSPI0 terminal of MCUU6. The serial clock terminal of high-speed differential transceiver U1 is connected to one end of resistor R81 and one end of resistor R20. The other end of resistor R81 is connected to the voltage terminal of the input / output port of high-speed differential transceiver U1. The other end of resistor R20 is connected to the low-voltage differential signal transmission terminal of MCUU6.The serial data input terminal of the high-speed differential transceiver U1 is connected to one end of resistor R11, and the other end of resistor R11 is connected to the serial data output terminal of the Bluetooth chip U3. The serial word select input terminal of the high-speed differential transceiver U1 is connected to one end of resistor R233, and the other end of resistor R233 is connected to the MCU U6PTD16 terminal. The serial data receiver terminal of the high-speed differential transceiver U1I2C is connected to one end of resistor R30, and the other end of resistor R30 is connected to the MCU U6I2C serial data transmitter terminal. The serial data clock terminal of the high-speed differential transceiver U1I2C is connected to one end of resistor R36, and the other end of resistor R36 is connected to the MCU U6I2C serial data clock terminal. 1. Connect one end of resistor R38 to the general-purpose input / output terminal. Connect the other end of resistor R38 to the low-voltage differential reset terminal of MCUU6. Connect one end of resistor R32 to the high-impedance terminal of high-speed differential transceiver U1. Connect the other end of resistor R32 to the PTE7 terminal of MCUU6. Connect one end of inductor L5, one end of capacitor C15, one end of capacitor C16, one end of capacitor C17, one end of capacitor C18, and one end of capacitor 19 to the power supply. Connect the other ends of capacitors C15, C16, C17, C18, and 19 to the power supply ground. Connect the other end of inductor L5 to the voltage output terminal of the step-down circuit.

[0060] The positive terminal of the first group of LVDS data output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L15, the negative terminal of the first group of LVDS data output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L15, the third terminal of the common-mode filter L15 is connected to the positive terminal of the first group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L15 is connected to the negative terminal of the first group of differential signal input of the video bridge chip U7.

[0061] The positive terminal of the second group of LVDS data output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L16, the negative terminal of the second group of LVDS data output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L16, the third terminal of the common-mode filter L16 is connected to the positive terminal of the second group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L16 is connected to the negative terminal of the second group of differential signal input of the video bridge chip U7.

[0062] The positive terminal of the third group LVDS data output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L17, the negative terminal of the third group LVDS data output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L17, the third terminal of the common-mode filter L17 is connected to the positive terminal of the third group differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L17 is connected to the negative terminal of the third group differential signal input of the video bridge chip U7.

[0063] The positive terminal of the fourth group LVDS data output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L18, the negative terminal of the fourth group LVDS data output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L18, the third terminal of the common-mode filter L18 is connected to the positive terminal of the fourth group differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L18 is connected to the negative terminal of the fourth group differential signal input of the video bridge chip U7.

[0064] The positive terminal of the clock signal of the high-speed differential transceiver U1LVDS is connected to the second terminal of the common-mode filter L19, the negative terminal of the clock signal of the high-speed differential transceiver U1LVDS is connected to the first terminal of the common-mode filter L19, the third terminal of the common-mode filter L19 is connected to the positive terminal of the clock input of the video bridge chip U7LVDS, and the fourth terminal of the common-mode filter L19 is connected to the negative terminal of the clock input of the video bridge chip U7LVDS.

[0065] The positive terminal of the first differential signal output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L14, the negative terminal of the first differential signal output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L14, the third terminal of the common-mode filter L14 is connected to the positive terminal of the first differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L14 is connected to the negative terminal of the first differential signal input of the video bridge chip U7.

[0066] The positive terminal of the second group differential signal output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L13, the negative terminal of the second group differential signal output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L16, the third terminal of the common-mode filter L13 is connected to the positive terminal of the second group differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L13 is connected to the negative terminal of the second group differential signal input of the video bridge chip U7.

[0067] The positive terminal of the third differential signal output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L11, the negative terminal of the third differential signal output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L11, the third terminal of the common-mode filter L11 is connected to the positive terminal of the third differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L11 is connected to the negative terminal of the third differential signal input of the video bridge chip U7.

[0068] The positive terminal of the fourth differential signal output of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L10, the negative terminal of the fourth differential signal output of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L10, the third terminal of the common-mode filter L10 is connected to the positive terminal of the fourth differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L10 is connected to the negative terminal of the fourth differential signal input of the video bridge chip U7.

[0069] The positive terminal of the differential clock signal of the high-speed differential transceiver U1 is connected to the second terminal of the common-mode filter L12, the negative terminal of the differential clock signal of the high-speed differential transceiver U1 is connected to the first terminal of the common-mode filter L12, the third terminal of the common-mode filter L12 is connected to the positive terminal of the differential clock input of the video bridge chip U7, and the fourth terminal of the common-mode filter L12 is connected to the negative terminal of the differential clock input of the video bridge chip U7.

[0070] The open-drain lockout indicator output terminal of the high-speed differential transceiver U1 is connected to one end of resistor R128 and one end of resistor R22. The other end of resistor R128 is connected to the input / output port voltage terminal of the high-speed differential transceiver U1. The other end of resistor R22 is connected to the MCUU6DES lockout terminal. The open-drain error indicator output terminal of the high-speed differential transceiver U1 is connected to one end of resistor R26 and one end of resistor R102. The other end of resistor R102 is connected to the input / output port voltage terminal of the high-speed differential transceiver (U1). The other end of resistor R26 is connected to the MCUU6DES error terminal.

[0071] The video bridging chip U7 MIPI data transmission terminal is connected to the optomechanical MIPI data transmission terminal; the video conversion clock terminal of the video bridging chip U7 is connected to one end of resistor R117, the other end of resistor R117 is connected to one end of resistor R118 and the video conversion clock input terminal of level converter U14, the video conversion clock output terminal of level converter U14 is connected to the optomechanical video conversion clock input terminal, and the other end of resistor R118 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit;

[0072] The video bridging chip U7's video conversion data terminal is connected to one end of resistor R122. The other end of resistor R122 is connected to one end of resistor R123 and the video conversion data input terminal of level converter U14. The video conversion data output terminal of level converter U14 is connected to the video conversion data input terminal of the optical engine. The other end of resistor R123 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit. The video conversion reset terminal of video bridging chip U7 is connected to one end of resistor R124. The other end of resistor R124 is connected to the video conversion reset terminal of MCUU6. The INT terminal of video bridging chip U7 is connected to one end of resistor R136. The other end of resistor R136 is connected to the CONV INT terminal of MCUU6. The DLP Display ON terminal of MCUU6 is connected to the DLP Display ON terminal of level converter U13. The Display ON terminal of level converter U13 is connected to the Display ON terminal of the optical engine. The DLP Status terminal of MCUU6 is connected to the DLP Status terminal of level converter U13. The DLP Status terminal of level converter U13 is connected to the DLP Status terminal of the optical engine. The Option 1 terminal of MCUU6 is connected to the MCU level converter U13. Option 1 terminal: Level converter U13 Option 1 terminal connects to the optomechanical Option 1 terminal; MCUU6 MCU PROG EN terminal connects to the level converter U14 PROG EN terminal; Level converter U14 SPI_Flash_PROG_EN terminal connects to the optomechanical SPI_Flash_PROG_EN terminal; MCUU6 MCU FPGA RST terminal connects to the level converter U14 MCU FPGA RST terminal; Level converter U14 FPGA RST terminal connects to the optomechanical FPGA RST terminal.

Claims

1. A video conversion circuit for an optical waveguide display screen, characterized in that: The system includes an MCU (U6), whose data transmission terminal is connected to the data transmission terminal of a level conversion module, which is connected to the data transmission terminal of an optomechanical system. A high-speed differential transceiver (U1) LVDS data transmission terminal is connected to the data receiving terminal of a filtering module. The filtered data transmission terminal of the filtering module is connected to the LVDS data receiving terminal of a video bridging chip U7, and the MIPI data transmission terminal of the video bridging chip U7 is connected to the MIPI data receiving terminal of the optomechanical system.

2. The video conversion circuit for an optical waveguide display screen according to claim 1, characterized in that: It also includes a wake-up circuit, wherein the low-dropout wake-up signal output terminal of the wake-up circuit is connected to the power supply module, the wake-up sampling signal output terminal of the wake-up circuit is connected to the wake-up sampling signal input terminal of the MCU (U6), and the system wake-up signal output terminal of the wake-up circuit is connected to the system wake-up signal input terminal of the MCU (U6).

3. The video conversion circuit for an optical waveguide display screen according to claim 2, characterized in that: The wake-up circuit includes a diode D3. The positive terminal of the diode D3 is connected to the vehicle wake-up signal output terminal, and the negative terminal of the diode D3 is the low-dropout wake-up signal output terminal. It is connected to one end of resistor R73 and one end of resistor R59. The other end of resistor R59 is the wake-up sampling signal output terminal, and it is connected to one end of resistor R60, one end of capacitor C59, and the wake-up sampling signal input terminal of MCU (U6). The other ends of resistor R60 and capacitor C59 are both connected to power ground. The other end of resistor R73 is connected to one end of resistor R56, one end of capacitor C61, and the base of transistor Q1. The emitter of transistor Q1, the other end of resistor R56, and the other end of capacitor C61 are all connected to the power supply ground. The collector of transistor Q1 is connected to one end of resistor R58. The other end of resistor R58 is connected to one end of resistor R3 and the base of transistor Q19. The other end of resistor R3 and the emitter of transistor Q19 are both connected to the 3.3V MCU power supply terminal. The collector of transistor Q19 is the system wake-up signal output terminal of the wake-up circuit, which is connected to one end of resistor R2, one end of capacitor C2, and the MCU (U6) wake-up signal input terminal.

4. The video conversion circuit for an optical waveguide display screen according to claim 1, characterized in that: It also includes a power supply module, which comprises a DC-DC conversion circuit, a step-down circuit, a differential voltage regulation circuit, and a battery sampling circuit.

5. The video conversion circuit for an optical waveguide display screen according to claim 4, characterized in that: The DC-DC conversion circuit includes a DC-DC converter (U2). The voltage input terminal of the DC-DC converter (U2) is connected to one end of resistor R115, one end of capacitor C53, one end of capacitor C58, and one end of capacitor C54. The other ends of capacitors C53, C58, and C54 are all connected to power ground. The other end of resistor R115 is connected to the battery operating voltage output terminal. The enable terminal of the DC-DC converter (U2) is connected to the 3.3V switch enable signal output terminal of MCU (U6) and one end of resistor R51. The other end of resistor R51 is connected to power ground. The clock terminal of the DC-DC converter (U2) is connected to one end of resistor R74. The SS terminal of the DC-DC converter (U2) is connected to one end of capacitor C92 and one end of capacitor C56. The other end of capacitor C92 is connected to one end of resistor R101. One end of resistor R74, one end of resistor R101, one end of capacitor C56, and the ground terminal of the DC-DC converter (U2) are all connected to the power supply ground. The bias terminal of the DC-DC converter (U2) is connected to one end of resistor R52, the other end of resistor R52 is connected to one end of capacitor C48, the other end of capacitor C48 is connected to one end of resistor R64, the other end of resistor R64 is connected to one end of capacitor C57, and the other end of capacitor C57 is connected to power ground. The output terminal of the DC-DC converter (U2) is connected to one end of inductor L6 and the negative terminal of diode D2. The positive terminal of diode D2 is connected to the power supply ground. The other end of inductor L6 is connected to one end of capacitor C49, one end of capacitor C50, one end of capacitor C51, and one end of capacitor C52. The other ends of capacitors C49, C50, C51, and C52 are all connected to the power supply ground. The other end of inductor L6 is the DC-DC conversion voltage output terminal of the DC-DC conversion circuit, and outputs a 3.3V voltage. The other end of inductor L6 is also connected to one end of resistor R65. The other end of resistor R65 is the MCU power supply terminal of the DC-DC conversion circuit, used to output a 3.3V voltage, and connected to the internal voltage input terminal of the MCU (U6). The feedback terminal of the DC-DC converter (U2) is connected to one end of resistor R63 and one end of resistor R61. The other end of resistor R63 is connected to the power supply ground. The other end of resistor R61 is connected to one end of resistor R62 and the other end of resistor R61 is connected to the other end of inductor L6.

6. The video conversion circuit for an optical waveguide display screen according to claim 5, characterized in that: The step-down circuit includes a step-down chip (U4). The power input terminal of the step-down chip (U4) is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit, one end of resistor R72, and one end of capacitor C69. The other end of resistor R72 is connected to the enable terminal of the step-down chip (U4), and the other end of capacitor C69 is connected to the power ground. The NR terminal of the step-down chip (U4) is connected to one end of capacitor C8. The other end of capacitor C8 and the ground terminal of the step-down chip (U4) are both connected to the power ground. The step-down output terminal of the step-down chip (U4) is used to output a 1.8V voltage and is connected to one end of resistor R13, one end of capacitor C7, and one end of capacitor C68. The other end of capacitor C68 is connected to the power ground. The other ends of resistor R13 and capacitor C7 are connected to the feedback terminal of the step-down chip (U4) and one end of resistor R76. The other end of resistor R76 is connected to the power ground. The differential pressure regulation circuit includes a low-dropout regulator (U5). The power input terminal of the low-dropout regulator (U5) is connected to the negative terminal of diode D13, one end of capacitor C124, one end of capacitor C116, one end of capacitor C118, and one end of capacitor C123. The other ends of capacitors C124, C116, C118, and C123 are all connected to ground. The positive terminal of diode D13 is connected to the battery power supply terminal. The low-dropout regulator (U5) is enabled. The signal terminal is connected to the third terminal of the switching diode D1 and one end of the resistor R116. The other end of the resistor R116 and the ground terminal of the low-dropout regulator (U5) are both connected to the power supply ground. The first terminal of the switching diode D1 is connected to one end of the resistor R31 and one end of the capacitor C114. The other end of the capacitor C114 is connected to the power supply ground. The other end of the resistor R31 is connected to the low-dropout wake-up signal output terminal of the wake-up circuit. The second terminal of the switching diode D1 is connected to the 3.3V switch enable signal output terminal of the MCU (U6). The battery sampling circuit includes a resistor R69. One end of the resistor R69 is connected to the battery sampling enable signal output terminal of the MCU (U6). The other end of the resistor R69 is connected to one end of the resistor R70, one end of the capacitor C1, and the base of the transistor Q3. The other ends of the resistor R70, the other end of the capacitor C1, and the emitter of the transistor Q3 are all connected to the power supply ground. The collector of the transistor Q3 is connected to one end of the resistor R66 and one end of the resistor R215. The other end of the resistor R66 is connected to one end of the resistor R71 and the base of the transistor Q2. The other end of the resistor R71 and the emitter of the transistor Q2 are both connected to the battery power supply terminal. The collector of the transistor Q2 is connected to one end of the resistor R67. The other end of the resistor R67 is the battery sampling signal output terminal of the battery sampling circuit, and is connected to one end of the resistor R68, one end of the capacitor C67, and the battery sampling signal input terminal of the MCU (U6). The other ends of the resistor R68 and the other end of the capacitor C67 are both connected to the power supply ground. The other end of resistor R215 is connected to one end of resistor R218 and the base of transistor Q16. The other end of resistor R218 and the emitter of transistor Q16 are both connected to the battery power supply terminal. The collector of transistor Q16 is connected to one end of resistor R217. The other end of resistor R217 is the DC bus sampling signal output terminal of the battery sampling circuit, and is connected to one end of resistor R216, one end of capacitor C141 and the DC bus sampling signal input terminal of MCU (U6). The other ends of resistor R216 and capacitor C141 are both connected to power ground.

7. The video conversion circuit for an optical waveguide display screen according to claim 6, characterized in that: The input / output voltage terminals of the high-speed differential transceiver (U1) are connected to one end of inductor L2, one end of capacitor C11, one end of capacitor C12, one end of capacitor C13, and one end of capacitor C14. The other ends of capacitors C11, C12, C13, and C14 are all connected to the power supply ground. The other end of inductor L2 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit. The operating voltage terminals of the high-speed differential transceiver (U1) are connected to one end of inductor L7, one end of capacitor C22, one end of capacitor C23, one end of capacitor C24, and one end of capacitor C25. One end of capacitor C26, one end of capacitor C27, and one end of capacitor C28; the other ends of capacitors C22, C23, C24, C25, C26, C27, and C28 are all connected to the power supply ground; the other end of inductor L7 is connected to the voltage output terminal of the step-down circuit; the first terminal of the high-speed differential transceiver (U1) crystal oscillator is connected to one end of resistor R14, one end of capacitor C35, and the third terminal of crystal oscillator Y2; the fourth terminal of crystal oscillator Y2 and the other end of capacitor C35 are connected to the power supply ground; the second terminal of the high-speed differential transceiver (U1) crystal oscillator... Connect the other end of resistor R14, one end of capacitor C29, and the first end of crystal oscillator Y2. The second end of crystal oscillator Y2 and the other end of capacitor C29 are both connected to power ground. The SIOB+ terminal of the high-speed differential transceiver (U1) is connected to one end of capacitor C38. The other end of capacitor C38 is connected to one end of resistor R17, and the other end of resistor R17 is connected to power ground. The SIOB- terminal of the high-speed differential transceiver (U1) is connected to one end of capacitor C42. The other end of capacitor C42 is connected to one end of resistor R18, and the other end of resistor R18 is connected to power ground. The PWDNB terminal of the high-speed differential transceiver (U1) is connected to resistor R21. One end of the resistor R230 and one end of the capacitor C153 are connected to the power supply ground. The other end of the resistor R230 is connected to the input / output port voltage terminal of the high-speed differential transceiver (U1). The other end of the resistor R21 is connected to the PTE1 / LPSPI0 terminal of the MCU (U6). The serial clock terminal of the high-speed differential transceiver (U1) is connected to one end of the resistor R81 and one end of the resistor R20. The other end of the resistor R81 is connected to the input / output port voltage terminal of the high-speed differential transceiver (U1). The other end of the resistor R20 is connected to the low-voltage differential signal transmission terminal of the MCU (U6).The serial data input terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R11, and the other end of resistor R11 is connected to the serial data output terminal of the Bluetooth chip (U3). The serial word select input terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R233, and the other end of resistor R233 is connected to the PTD16 terminal of the MCU (U6). The I2C serial data receiver terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R30, and the other end of resistor R30 is connected to the I2C serial data transmitter terminal of the MCU (U6). The I2C serial data clock terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R36, and the other end of resistor R36 is connected to the I2C serial data clock terminal of the MCU (U6). The general-purpose input / output terminals of the transceiver (U1) are connected to one end of resistor R38. The other end of resistor R38 is connected to the low-voltage differential reset terminal of the MCU (U6). The high-impedance terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R32. The other end of resistor R32 is connected to the PTE7 terminal of the MCU (U6). The power supply terminal of the digital regulator of the high-speed differential transceiver (U1) is connected to one end of inductor L5, one end of capacitors C15, C16, C17, C18, and one end of capacitor C19. The other ends of capacitors C15, C16, C17, C18, and C19 are all connected to power ground. The other end of inductor L5 is connected to the voltage output terminal of the step-down circuit.

8. The video conversion circuit for an optical waveguide display screen according to claim 7, characterized in that: The filtering module includes common-mode filters L15, L16, L17, L18, L19, L10, L14, L13, L12, and L11. The positive terminal of the first group of LVDS data output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L15, the negative terminal of the first group of LVDS data output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L15, the third terminal of the common-mode filter L15 is connected to the positive terminal of the first group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L15 is connected to the negative terminal of the first group of differential signal input of the video bridge chip U7. The positive terminal of the second group of LVDS data output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L16, the negative terminal of the second group of LVDS data output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L16, the third terminal of the common-mode filter L16 is connected to the positive terminal of the second group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L16 is connected to the negative terminal of the second group of differential signal input of the video bridge chip U7. The positive terminal of the third group of LVDS data output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L17, the negative terminal of the third group of LVDS data output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L17, the third terminal of the common-mode filter L17 is connected to the positive terminal of the third group of differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L17 is connected to the negative terminal of the third group of differential signal input of the video bridge chip U7. The positive terminal of the fourth group LVDS data output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L18, the negative terminal of the fourth group LVDS data output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L18, the third terminal of the common-mode filter L18 is connected to the positive terminal of the fourth group differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L18 is connected to the negative terminal of the fourth group differential signal input of the video bridge chip U7. The positive terminal of the LVDS clock signal of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L19, the negative terminal of the LVDS clock signal of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L19, the third terminal of the common-mode filter L19 is connected to the positive terminal of the LVDS clock input of the video bridge chip U7, and the fourth terminal of the common-mode filter L19 is connected to the negative terminal of the LVDS clock input of the video bridge chip U7. The positive terminal of the first group of differential signal output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L14, the negative terminal of the first group of differential signal output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L14, the third terminal of the common-mode filter L14 is connected to the positive terminal of the first group of differential signal input of the video bridging chip U7, and the fourth terminal of the common-mode filter L14 is connected to the negative terminal of the first group of differential signal input of the video bridging chip U7. The positive terminal of the second group differential signal output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L13, the negative terminal of the second group differential signal output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L16, the third terminal of the common-mode filter L13 is connected to the positive terminal of the second group differential signal input of the video bridging chip U7, and the fourth terminal of the common-mode filter L13 is connected to the negative terminal of the second group differential signal input of the video bridging chip U7. The positive terminal of the third differential signal output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L11, the negative terminal of the third differential signal output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L11, the third terminal of the common-mode filter L11 is connected to the positive terminal of the third differential signal input of the video bridge chip U7, and the fourth terminal of the common-mode filter L11 is connected to the negative terminal of the third differential signal input of the video bridge chip U7. The positive terminal of the fourth differential signal output of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L10, the negative terminal of the fourth differential signal output of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L10, the third terminal of the common-mode filter L10 is connected to the positive terminal of the fourth differential signal input of the video bridging chip U7, and the fourth terminal of the common-mode filter L10 is connected to the negative terminal of the fourth differential signal input of the video bridging chip U7. The positive terminal of the differential clock signal of the high-speed differential transceiver (U1) is connected to the second terminal of the common-mode filter L12, the negative terminal of the differential clock signal of the high-speed differential transceiver (U1) is connected to the first terminal of the common-mode filter L12, the third terminal of the common-mode filter L12 is connected to the positive terminal of the differential clock input of the video bridge chip U7, and the fourth terminal of the common-mode filter L12 is connected to the negative terminal of the differential clock input of the video bridge chip U7.

9. The video conversion circuit for an optical waveguide display screen according to claim 6, characterized in that: The open-drain lockout indicator output terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R128 and one end of resistor R22. The other end of resistor R128 is connected to the input / output port voltage terminal of the high-speed differential transceiver (U1). The other end of resistor R22 is connected to the DES lockout terminal of the MCU (U6). The open-drain error indicator output terminal of the high-speed differential transceiver (U1) is connected to one end of resistor R26 and one end of resistor R102. The other end of resistor R102 is connected to the input / output port voltage terminal of the high-speed differential transceiver (U1). The other end of resistor R26 is connected to the DES error terminal of the MCU (U6). The video bridging chip U7 MIPI data transmission terminal is connected to the optomechanical MIPI data transmission terminal; the video conversion clock terminal of the video bridging chip U7 is connected to one end of resistor R117, the other end of resistor R117 is connected to one end of resistor R118 and the video conversion clock input terminal of level converter U14, the video conversion clock output terminal of level converter U14 is connected to the optomechanical video conversion clock input terminal, and the other end of resistor R118 is connected to the DC conversion voltage output terminal of DC-DC conversion circuit; The level conversion module includes level converters U13 and U14. The video conversion data terminal of the video bridging chip U7 is connected to one end of resistor R122. The other end of resistor R122 is connected to one end of resistor R123 and the video conversion data input terminal of level converter U14. The video conversion data output terminal of level converter U14 is connected to the video conversion data input terminal of the optical engine. The other end of resistor R123 is connected to the DC-DC conversion voltage output terminal of the DC-DC conversion circuit. The video conversion reset terminal of the video bridging chip U7 is connected to one end of resistor R124. The other end of resistor R124 is connected to the video conversion reset terminal of MCU (U6). The INT terminal of the video bridging chip U7 is connected to one end of resistor R136. The other end of resistor R136 is connected to the CONV INT terminal of MCU (U6). The DLP Display ON terminal of MCU (U6) is connected to the DLP Display ON terminal of level converter U13. The Display ON terminal of level converter U13 is connected to the Display ON terminal of the optical engine. The MCU DLP Status terminal of MCU (U6) is connected to the MCU DLP level converter U13. The Status terminal of the level converter U13DLP Status terminal is connected to the DLP Status terminal of the optical engine; the MCU (U6) MCU Option 1 terminal is connected to the MCU Option 1 terminal of the level converter U13, and the MCU Option 1 terminal of the level converter U13 is connected to the Option 1 terminal of the optical engine; the MCU (U6) MCU PROG EN terminal is connected to the PROG EN terminal of the level converter U14, the SPI_Flash_PROG_EN terminal of the level converter U14 is connected to the SPI_Flash_PROG_EN terminal of the optical engine, the MCU (U6) MCU FPGA RST terminal is connected to the FPGA RST terminal of the level converter U14, and the FPGA RST terminal of the level converter U14 is connected to the FPGA RST terminal of the optical engine.

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