Chip stack structure

Abstract

The utility model provides a chip stack structure. The chip stack structure comprises a first semiconductor crystal grain, a second semiconductor crystal grain, a bridging crystal grain and a gap filling material, the first semiconductor die includes an integrated circuit region. The second semiconductor die is disposed on the first semiconductor die and electrically connected to the first semiconductor die. The bridge die is disposed on the first semiconductor die and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. And a gap filling material disposed over the first semiconductor die to laterally cover the bridge die and the second semiconductor die.

Description

Technical Field

[0001] This utility model relates to a chip stack structure. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers or materials on a semiconductor substrate and pattern, and then forming circuit components and assemblies thereon. Typically, dozens or hundreds of integrated circuits are fabricated on a single semiconductor wafer. Individual dies can be obtained by dicing the integrated circuits along dicing lines. Then, for example, the individual dies can be individually packaged in multi-chip assemblies or other types of packages.

[0003] The semiconductor industry continuously improves the integration of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the smallest feature size, allowing more components to be integrated into a given area. In some applications, these smaller electronic components (such as integrated circuit dies) may also require smaller and more reliable packages that use less area than previous packages. Utility Model Content

[0004] According to some embodiments disclosed herein, a chip stack structure is provided, comprising a first semiconductor die, a second semiconductor die, a bridging die, and a gap-filling material. The first semiconductor die includes multiple integrated circuit regions. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The bridging die is disposed above and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridging die. The gap-filling material is disposed on the first semiconductor die to laterally cover the bridging die and the second semiconductor die.

[0005] According to some alternative embodiments disclosed herein, a chip stack structure is provided, comprising a first semiconductor die, a second semiconductor die, and a bridging die. The first semiconductor die includes a first integrated circuit region and a second integrated circuit region spaced apart from the first integrated circuit region. The second semiconductor die is disposed above and electrically connected to the first and second integrated circuit regions. The bridging die is disposed above and electrically connected to the first and second integrated circuit regions.

[0006] According to some alternative embodiments disclosed herein, a chip stack structure is provided, comprising a first semiconductor die, a second semiconductor die, and a bridging die. The first semiconductor die includes an integrated circuit region and a bonding structure, wherein the bonding structure covers the integrated circuit region, and the integrated circuit regions are laterally spaced apart from each other. The second semiconductor die is thus disposed on the integrated circuit region and electrically connected to the integrated circuit region through the bonding structure. The bridging die is disposed on the bonding structure and electrically connected to the integrated circuit region through the bonding structure.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figures 1A to 1L A cross-sectional view schematically illustrating a process flow for manufacturing a chip stack structure in some embodiments of this disclosure is shown.

[0009] Figures 2A to 2I A cross-sectional view schematically illustrating a process flow for manufacturing a PoP (PoP) structure in some embodiments of this disclosure is shown. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of this invention. Specific examples of components and configurations are described below to simplify the invention. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this invention. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one component or feature and another, as illustrated in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of components in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0012] Embodiments of this invention may further include other features and processes. For example, the apparatus may include a test structure to assist in verification testing of 3D packaged or 3D integrated circuit (3DIC) components. For example, the test structure may include test pads formed in redistribution layers or on a substrate, and the test pads allow for testing of the 3D package or 3DIC, the use of probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with intermediate verification testing methods that incorporate known good dies to increase yield and reduce cost.

[0013] Figures 1A to 1L A cross-sectional view schematically illustrating a process flow for manufacturing a chip stack structure in some embodiments of this disclosure is shown.

[0014] Please refer to Figure 1A A semiconductor wafer 10 is provided, comprising an integrated circuit region 10a and a dummy region 10b. In the semiconductor wafer 10, the integrated circuit region 10a and the dummy region 10b are laterally spaced apart from each other. The integrated circuit region 10a may be a logic die, a system-on-a-chip (SoC) die, or other suitable semiconductor die. The dummy region 10b may have a mesh pattern, and multiple integrated circuit regions 10a may be laterally spaced apart from each other through the mesh patterned dummy region 10b. At this stage, the multiple integrated circuit regions 10a are electrically insulated from each other through the dummy region 10b. The semiconductor wafer 10 may include a substrate 12 (e.g., a semiconductor substrate), through-substrate vias 14 embedded in the substrate 10, interconnect structures 16 disposed on the substrate 12, and a protective layer 18 disposed on the interconnect structures 16, wherein the through-substrate vias 14 are electrically connected to the interconnect structures 16. The substrate 12 of the semiconductor wafer 10 may include a crystalline silicon wafer. Depending on design requirements, the substrate 12 may include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped region may be doped with p-type or n-type dopants. The doped region may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped region may be configured as an n-type fin field-effect transistor (n-type FinFET) and / or a p-type fin field-effect transistor (p-type FinFET). In some alternative embodiments, the substrate 12 may be made of some other suitable elemental semiconductor, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0015] Through-substrate via 14 can be formed by creating a recess in substrate 12, for example, by etching, milling, laser technology, and / or a combination of the aforementioned processes. A thin barrier layer can be conformally deposited above the front side of substrate 12 and within the opening, for example, via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, and / or a combination of the aforementioned processes. The barrier layer may comprise nitrides or oxides of nitride, such as titanium nitride, titanium oxide nitride, tantalum nitride, tantalum oxide nitride, tungsten nitride, and / or a combination of the aforementioned materials. A conductive material is deposited above the thin barrier layer and within the opening. The conductive material can be formed by electrochemical plating, CVD, ALD, PVD, and / or a combination of the aforementioned processes. The conductive material may be, for example, copper, tungsten, aluminum, silver, gold, and / or a combination of the aforementioned materials. Excess conductive material and the barrier layer can be removed from the front side of substrate 12, for example, by chemical mechanical polishing. Therefore, in some embodiments, the through-substrate via 14 may include a conductive material and a thin barrier layer located between the conductive material and the substrate 12.

[0016] Interconnect structure 16 may include one or more dielectric layers (e.g., one or more sandwich dielectric (ILD) layers, inter-metal dielectric (IMD) layers, or the like) and interconnect wiring embedded in one or more dielectric layers, wherein the interconnect wiring is electrically connected to semiconductor components (e.g., FinFETs) formed in substrate 12 and / or through-holes 14 in the substrate. The material in one or more dielectric layers may include silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric material. Interconnect wiring may include metallic wiring. For example, interconnect wiring includes copper wiring, copper pads, aluminum pads, or combinations thereof. In some embodiments, through-substrate via 14 may extend through one or more layers in interconnect structure 16 and into substrate 12.

[0017] The protective layer 18 may be or include a dielectric layer. The material of the protective layer 18 may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y The protective layer 18 may be formed by depositing the dielectric material via a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes).

[0018] like Figure 1AAs shown, the through-substrate via 14 is embedded in the substrate 12 and the interconnect structure 16. At this stage, the through-substrate via 14 is not exposed on the back side of the substrate 12.

[0019] refer to Figure 1A and Figure 1B A wafer dicing process performed along dicing track SL1 is used to dice semiconductor wafer 10 to obtain monomeric semiconductor dies 20. Each monomeric semiconductor die 20 may include a substrate 12, a through-substrate via 14 embedded in the substrate 12, an interconnect structure 16 disposed on the substrate 12, and a protective layer 18 disposed on the interconnect structure 16. Each monomeric semiconductor die 20 includes at least two integrated circuit regions 10a and at least one dummy region 10b, wherein the at least two integrated circuit regions 10a are laterally spaced from each other through the at least one dummy region 10b. In some embodiments, the at least two integrated circuit regions 10a include a first integrated circuit region 10a (e.g., Figure 1B The integrated circuit region shown on the left side of the middle section) and the second integrated circuit region 10a (e.g., Figure 1B The first integrated circuit region 10a is shown on the right side of the diagram. The dummy region 10b is an elongated dummy region located between the first and second integrated circuit regions 10a, such that the side-by-side first and second integrated circuit regions 10a can be laterally spaced apart from each other through the elongated dummy region 10b. In some other embodiments, the aforementioned at least two integrated circuit regions 10a include four integrated circuit regions 10a arranged in a (2x2) array, and the dummy region 10b is a cross-shaped or grid-shaped dummy region, such that the four integrated circuit regions 10a arranged in an array can be laterally spaced apart from each other through the cross-shaped or grid-shaped dummy region 10b.

[0020] refer to Figure 1C The monomerized semiconductor die 20 is picked up and placed side-by-side on the carrier plate C1, so that the front surface of the monomerized semiconductor die 20 is bonded to the carrier plate C1. Although Figure 1COnly one monolithic semiconductor die 20 is shown, but the number of monolithic semiconductor dies 20 placed on the carrier C1 is unlimited. The carrier C1 can be a semiconductor wafer, such as a silicon wafer. The carrier C1 can have a circular top-view shape and the size of a silicon wafer. For example, the carrier C1 can have an 8-inch diameter, a 12-inch diameter, or other sizes. The monolithic semiconductor die 20 is bonded to the carrier C1 through a chip-to-wafer bonding process. A bonding process is performed to bond the protective layer 18 of the monolithic semiconductor die 20 to the carrier C1. The bonding process can be a direct bonding process. After performing the above direct bonding process, a semiconductor-to-dielectric bonding interface, such as a silicon-to-nitride (Si-SiN) bonding interface, can be formed between the protective layer 18 and the carrier C1. x bonding interface).

[0021] In some alternative embodiments, the monomerization process of semiconductor wafer 102 can be omitted. In other words, semiconductor wafer 10 is picked up and placed on carrier C1 such that the front surface of semiconductor wafer 10 is bonded to carrier C1 through a wafer-to-wafer bonding process.

[0022] refer to Figure 1D A gap-filling material is formed on a carrier substrate C1 to cover the monomerized semiconductor die 20 bonded to the carrier substrate C1. The gap-filling material can be a dielectric material (e.g., tetraethoxysilane formed from oxide or other suitable dielectric materials), a molding compound (e.g., epoxy resin or other suitable resin) formed via a gap-filling process, an over-molding process, or other similar processes. The gap-filling material can cover the back side of the monomerized semiconductor die 20. After the gap-filling material is formed on the carrier substrate C1, the gap-filling material and the semiconductor substrate 12 of the monomerized semiconductor die 20 are partially removed to thin the semiconductor substrate 12 of the semiconductor die 20 and to laterally cover the monomerized semiconductor die 20 with the gap-filling layer 22. The gap-filling material and the semiconductor substrate 12 of the monomerized semiconductor die 20 can be partially removed by a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, or a combination of similar processes. After the planarization process described above is completed, the thickness of the gap filling layer 22 is substantially equal to the thickness of the monomeric semiconductor die 20. In other words, the top surface of the gap filling layer 22 is substantially flush with the back surface of the monomeric semiconductor die 20.

[0023] like Figure 1D As shown, at this stage, after performing the planarization process described above, the through-substrate via 14 will be exposed on the back side of the semiconductor substrate 12. The through-substrate via 14 can protrude from the back side of the semiconductor substrate 12.

[0024] In some alternative embodiments where the monomerization process of semiconductor wafer 10 is omitted, the formation of gap filling layer 22 can be omitted because semiconductor wafer 10 is bonded to carrier C1 via wafer-to-wafer bonding process.

[0025] refer to Figure 1E A dielectric material can be formed on the back surface of the semiconductor substrate 12 and the top surface of the gap filling layer 22 to cover the exposed through-hole 14. The dielectric material can be or includes silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric material. A planarization process, such as chemical mechanical polishing (CMP), mechanical polishing, or a combination thereof, can be performed to partially remove the dielectric material, thereby forming a planarization layer 24 on the back side of the semiconductor substrate 12 and the top surface of the gap fill layer 22. The top surface of the planarization layer 24 is substantially flush with the top ends of the through-hole 14 in the substrate.

[0026] After the planarization layer 24 is formed, a bonding structure 26 is formed, and the bonding structure 26 includes a bonding dielectric layer 26a and a bonding conductor 26b embedded in the bonding dielectric layer 26a. The material of the bonding dielectric layer 26a may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N yThe bonding structure 26a can be formed by the following steps: depositing a dielectric material using a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes); patterning the dielectric material to form a bonding dielectric layer 26a including openings or vias; filling the openings or vias defined in the bonding dielectric layer 26a with conductive material to form a bonding conductor 26b embedded in the bonding dielectric layer 26a. In some embodiments, the conductive material used to form the bonding conductor 26b can be formed by a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes) followed by a planarization process (e.g., chemical mechanical polishing (CMP) and / or mechanical polishing).

[0027] After forming the bonding structure 26, at least two semiconductor dies 30 and at least one bridging die 35 are provided on the bonding structure 26. The at least two semiconductor dies 30 are disposed on and cover the integrated circuit region 10a of the semiconductor die 20, and the at least one bridging die 35 is disposed on and covers the dummy region 10b of the semiconductor die 20. The semiconductor dies 30 may be logic dies, system-on-a-chip (SoC) dies, or other suitable semiconductor dies. For example, the semiconductor dies 30 are manufactured using an N3 process. Semiconductor dies 20 and 30 may perform the same or different functions. For example, semiconductor dies 20 and 30 are system-on-a-chip (SoC) dies. Each semiconductor die 30 may include a semiconductor substrate 32 and an interconnect structure 34 disposed on the semiconductor substrate 32. Furthermore, a bonding structure 36 may be formed on the interconnect structure 34 of the semiconductor die 30. The bonding structure 36 includes a bonding dielectric layer 36a and a bonding conductor 36b embedded in the bonding dielectric layer 36a. The material of the bonding dielectric layer 36a may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N yThe bonding structure 36a may be formed by the following steps: depositing a dielectric material using a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes); patterning the dielectric material to form a bonding dielectric layer 36a including openings or vias; and filling conductive material into the openings or vias defined in the bonding dielectric layer 36a to form a bonding conductor 36b embedded in the bonding dielectric layer 36a. In some embodiments, the conductive material used to form the bonding conductor 36b may be formed by a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes) followed by a planarization process (e.g., chemical mechanical polishing (CMP) and / or mechanical polishing).

[0028] The bridging die 35 may include a semiconductor substrate 35a and an interconnect structure 35b disposed on the semiconductor substrate 35a. Furthermore, a bonding structure 35c is formed on the interconnect structure 35b. The bonding structure 35c includes a bonding dielectric layer 35c1 and a bonding conductor 35c2 embedded in the bonding dielectric layer 35c1. The material of the bonding dielectric layer 35c1 may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N yThe bonding structure 35c can be formed by the following steps: depositing a dielectric material using a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes); patterning the dielectric material to form a bonding dielectric layer 35c1 including openings or vias; filling the openings or vias defined in the bonding dielectric layer 35c1 with conductive material to form a bonding conductor 35c2 embedded in the bonding dielectric layer 35c1. In some embodiments, the conductive material used to form the bonding conductor 35c2 can be formed using a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes) followed by a planarization process (e.g., chemical mechanical polishing (CMP) and / or mechanical polishing). The bridging die 35 can include bridging wiring distributed in the interconnect structure 35b and / or the bonding structure 35c. In some embodiments, only bridging die 35 provides signal bridging functionality, and bridging die 35 does not perform signal processing. In some other embodiments, bridging die 35 may not only provide signal bridging functionality, but may also provide less signal processing capability than individual semiconductor dies 30. In other words, semiconductor dies 30 may provide better signal processing capability than bridging die 35. In some alternative embodiments, semiconductor dies 30 are manufactured using advanced wafer processes with small technology nodes (e.g., 7 nanometer (nm) process, 3 nanometer process, 2 nanometer process, 1 nanometer process, etc.), and bridging die 35 is manufactured using wafer processes with large technology nodes (e.g., 14 nanometer process, 28 nanometer process, etc.).

[0029] In some embodiments, the semiconductor substrate 35a of the bridging die 35 does not have transistors (e.g., planar FETs, FinFETs, and / or gate-all-around FETs) or isolation structures (e.g., shallow trench isolation (STI) structures, field oxide (FOX) structures, etc.) manufactured by front-end processes (FEOL). In other words, the fabrication of the bridging die 35 may be solely related to back-end processes (BEOL).

[0030] In some embodiments, the number of semiconductor dies 30 is equal to the number of integrated circuit regions 10a in each semiconductor die 20, and the number of bridging dies 35 may vary depending on the number of integrated circuit regions 10a in the semiconductor die 20. In embodiments where each semiconductor die 20 includes two integrated circuit regions 10a, the two integrated circuit regions 10a can communicate with each other through one or more bridging dies 35. In embodiments where each semiconductor die 20 includes four integrated circuit regions 10a arranged in a 2×2 array, the four integrated circuit regions 10a can communicate with each other through four or more bridging dies 35.

[0031] A bonding process (e.g., chip-to-wafer bonding) is performed to bond the bonding structure 26 formed on the semiconductor die 30 and the bonding structure 35c of the bridging die 35 to the bonding region of the bonding structure 36. The bonding process may include a hybrid bonding process of dielectric-to-dielectric bonding and metal-to-metal bonding. After the above bonding process, dielectric-to-dielectric bonding interfaces are formed between the bonding dielectric layer 26a and the bonding dielectric layer 36a, and between the bonding dielectric layer 35c1 and the bonding dielectric layer 36a; and metal-to-metal bonding interfaces are formed between the bonding conductors 26b and 36b, and between the bonding conductors 26b and 35c2. After the bonding process, the semiconductor die 30 and the integrated circuit region 10a of the semiconductor die 20 are electrically connected to each other through the bridging die 35 and the bonding structure 26.

[0032] like Figure 1E As shown, the lateral dimensions (e.g., width and / or length) of semiconductor die 30 and bridging die 35 may be smaller than the lateral dimensions (e.g., width and / or length) of semiconductor die 20. In other words, the footprint of semiconductor die 20 may be larger than the footprints of semiconductor die 30 and bridging die 35. Since the bonding structure 36 of semiconductor die 30 and the bonding structure 35c of bridging die 35 are bonded only to multiple bonding regions of bonding structure 26, a portion of the bonding dielectric layer 26a is not covered by bonding structures 36 and 35c.

[0033] Please refer to Figure 1F and Figure 1GA gap-filling material 38 is formed to cover the back surface of the semiconductor die 30, the sidewalls of the semiconductor die 30, the back surface of the bridging die 35, the sidewalls of the bridging die 35, the sidewalls of the bonding structure 36, the sidewalls of the bonding structure 35c, and multiple portions of the bonding dielectric layer 26a not covered by the bonding structures 36 and 35c. The gap-filling material 38 can be a dielectric material (e.g., tetraethoxysilane formed from oxide or other suitable dielectric material), a molding compound (e.g., epoxy resin or other suitable resin) formed via a gap-filling process, an over-molding process, or other similar processes. The gap-filling material 38 fills the gaps between adjacent semiconductor dies 30 and bridging dies 35. After forming the gap-filling material 38, it is partially removed until the substrate 32 of the semiconductor die 30 and the substrate 35a of the bridging die 35 are exposed, thereby forming a gap-filling layer 40. The gap filler material 38 can be partially removed by a planarization process such as chemical mechanical polishing (CMP) and / or mechanical polishing. After the planarization process described above, the top surface of the gap filler 40 is substantially flush with the back surface of the semiconductor die 30 and the back surface of the bridging die 35.

[0034] Please refer to Figure 1H A support substrate C2 is provided, and the support substrate C2 includes an adhesive layer 42 formed thereon. In some embodiments, the support substrate C2 is a silicon substrate, a glass substrate, a ceramic substrate, or the like. The support substrate C2 may have a circular top view shape. For example, the support substrate C2 may have an 8-inch diameter, a 12-inch diameter, or other dimensions. The adhesive layer 42 may be formed of a polymer-based adhesive material, and the adhesive layer 42 may adhere between the resulting structure formed on the substrate C1 and the support substrate C2. In some embodiments, the adhesive layer 42 may be applied in a liquid state and then cured. In an alternative embodiment, the adhesive layer 42 is a laminate film, and the adhesive layer 42 is laminated onto the support substrate C2. The top surface of the adhesive layer 42 is substantially planar.

[0035] A bonding process (e.g., wafer-to-wafer bonding process) is performed to bond the structure formed on the carrier C1 to the adhesive layer 42 supported by the support substrate C2. After the structure formed on the carrier C1 is bonded to the adhesive layer 42 supported by the support substrate C2, the top surface of the gap filling layer 40, the back surface of the semiconductor die 30, and the back surface of the bridging die 35 come into contact with the adhesive layer 42.

[0036] Please refer to Figure 1H and Figure 1IAfter the structure formed on the carrier plate C1 is bonded to the adhesive layer 42 supported by the support substrate C2, the carrier plate C1 is debonded from the protective layer 18 and the gap filling layer 22, thereby exposing the protective layer 18 and the gap filling layer 22.

[0037] Please refer to Figure 1I and Figure 1J The protective layer 18 is patterned to form openings, exposing the topmost interconnect wiring of the interconnect structure 16 within the openings formed in the protective layer 18. The formation of the openings in the protective layer 18 can be performed using a photolithography process. A passivation layer 44, including the openings formed therein, can be formed to cover the protective layer 18, exposing the topmost interconnect wiring of the interconnect structure 16 through the openings in the passivation layer 44. The formation of the openings in the passivation layer 44 can be performed using a photolithography process. The width of the openings defined in the passivation layer 44 can be smaller than the width of the openings defined in the protective layer 18. The passivation layer 44 can cover the top surface of the protective layer 18 and the top surface of the gap fill layer 22. The passivation layer 44 can further extend into the openings defined in the protective layer 18, so that the passivation layer 44 contacts the topmost interconnect wiring of the interconnect structure 16.

[0038] After the passivation layer 44 is formed, conductive terminals 46 are formed over the passivation layer 44. The conductive terminals 46 are electrically connected to the interconnect wiring of the interconnect structure 16 and protrude from the passivation layer 44. Each conductive terminal 46 may include a conductive post 46a and a solder cap 46b disposed on the conductive post 46a. The conductive post 46a fills an opening defined in the passivation layer 44 and protrudes from the passivation layer 44. The solder cap 46b covers the top surface of the conductive post 46a. After the conductive terminals 46 are formed, a chip probing process can be performed to increase yield. The formation of the conductive terminals 46 may include forming a seed layer (not shown) over the passivation layer 44, forming a patterned mask (not shown), such as a photoresist layer, over the seed layer, and then performing an electroplating process on the exposed seed layer. The patterned mask and portions of the seed layer covered by the patterned mask are then removed to leave the conductive terminals 46. A reflow process may be further performed to reshape the contour of the solder cap 46a. According to some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, the seed layer can be formed using physical vapor deposition (PVD). For example, electroplating can be performed using electroless plating.

[0039] Please refer to Figure 1J and Figure 1KAfter performing the chip probing process, the solder cap 46b is removed, and a dielectric layer 48 is formed over the passivation layer 44 to cover the conductive pillars 46a. In some embodiments, the dielectric layer 48 is formed of a polymer, which may be a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other similar materials. In some embodiments, the dielectric layer 48 is formed of nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or other similar materials.

[0040] Please refer to Figure 1K and Figure 1L Provides TP tape supported by the frame, and will Figure 1K The resulting structure is attached to adhesive tape TP. Then, a monomerization process is performed along dicing track SL2 to obtain multiple monomerized chip stack structures 100 (i.e., multiple SoIC structures). During the monomerization process, dielectric layer 48, passivation layer 44, gap fill layer 22, planarization layer 24, bonding structure 26, gap fill layer 40, adhesive layer 42, and support substrate C2 are diced along dicing track SL2. In some embodiments, gap fill layer 22 laterally covers semiconductor die 20, and the sidewalls of gap fill layer 40 are substantially aligned with the sidewalls of gap fill layer 22.

[0041] like Figure 1L As shown, the monolithic chip stack structure 100 (i.e., SoIC structure) includes a semiconductor die 20, a semiconductor die 30, a bridging die 35, and a gap filler material 40. The semiconductor die 20 includes laterally spaced integrated circuit regions 10a (e.g., a first integrated circuit region and a second integrated circuit region laterally spaced from the first integrated circuit region). The semiconductor die 30 is disposed on and electrically connected to the semiconductor die 20. The bridging die 35 is disposed on and electrically connected to the semiconductor die 20, and the plurality of integrated circuit regions 10 are electrically connected to each other through the bridging die 35. The gap filler material 40 is disposed on the semiconductor die 20 to laterally cover the bridging die 35 and the semiconductor die 30.

[0042] In some embodiments, semiconductor die 20 includes a bonding structure 26, each semiconductor die 30 includes a bonding structure 36, bridging die 35 includes a bonding structure 35c, the bonding structure 36 of each semiconductor die 30 is in contact with and electrically connected to the bonding structure 26, and the bonding structure 35c is in contact with and electrically connected to the bonding structure 26. In some embodiments, a semiconductor die 20 includes a semiconductor substrate 12, an interconnect structure 16 disposed on the semiconductor substrate 12, and a bonding structure 26 disposed on and electrically connected to the interconnect structure 16; each semiconductor die 30 includes a semiconductor substrate 32, an interconnect structure 34 disposed on the semiconductor substrate 32, and a bonding structure 36 disposed on and electrically connected to the interconnect structure 34; a bridging die 35 includes a semiconductor substrate 35a, an interconnect structure 35b disposed on the semiconductor substrate 35a, and a bonding structure 35c disposed on and electrically connected to the interconnect structure 35b; the bonding structure 36 of each semiconductor die 30 contacts and is electrically connected to the bonding structure 26; the bonding structure 35c contacts and is electrically connected to the bonding structure 26. In some embodiments, the semiconductor die 20 further includes a through-substrate via 14 through the semiconductor substrate 12, the interconnect structure 16 and the bonding structure 26 are disposed on opposite sides of the semiconductor substrate 12, and the interconnect structure 16 is electrically connected to the bonding structure 26 via the through-substrate via 14. In some embodiments, a plurality of integrated circuit regions 10 are electrically connected to each other via bridging dies 35 and bonding structures 26.

[0043] In some embodiments, the monolithic chip stack structure 100 (i.e., SoIC structure) further includes conductive terminals 46a disposed on the interconnect structure 16 of the semiconductor die 20, and the conductive terminals 46a are electrically connected to the interconnect structure 16. In some embodiments, such as Figure 1EAs shown, bonding structure 26 includes bonding dielectric layer 26a and bonding conductor 26b embedded in bonding dielectric layer 26a; bonding structure 36 includes bonding dielectric layer 36a and bonding conductor 36b embedded in bonding dielectric layer 36a; bonding structure 35c includes bonding dielectric layer 35c1 and bonding conductor 35c2 embedded in bonding dielectric layer 35c1, wherein bonding conductor 26b is bonded to bonding conductor 36b and bonding conductor 35c2, and bonding dielectric layer 36a and bonding dielectric layer 35c1 are bonded to multiple portions of bonding dielectric layer 26a. In some embodiments, semiconductor dies 30 are arranged side-by-side on semiconductor dies 20, and bridging dies 35 are disposed between semiconductor dies 30. In some embodiments, the monolithic chip stack structure 100 (i.e., SoC structure) further includes a support substrate C2, wherein gap filler material 40, semiconductor dies 30 and bridging dies 35 are disposed between support substrate C2 and semiconductor dies 20. In some embodiments, the semiconductor die 20 further includes a dummy region 10b, and a plurality of integrated circuit regions 10a are spaced apart from each other through the dummy region 10b. In some embodiments, a bridging die 35 is disposed above the dummy region 10b and covers the dummy region 10b.

[0044] In some embodiments, the monolithic chip stack structure 100 (i.e., SoIC structure) further includes an adhesive layer 42, through which the support substrate C2 is adhered to the gap filler material 40, the semiconductor die 30, and the bridging die 35. In some embodiments, the sidewalls of the support substrate C2 are substantially aligned with the sidewalls of the gap filler material 40 and the semiconductor die 20. In some embodiments, the lateral dimensions of the support substrate C2 are substantially the same as the lateral dimensions of the semiconductor die 20. In some embodiments, the thickness of the semiconductor die 30 is substantially the same as the thickness of the bridging die 35.

[0045] like Figure 1L As shown, no gap-filling material is formed between the integrated circuit regions 10a of the semiconductor die 20, and the dummy region of the semiconductor die 20 covered by the bridging die 35 is a semiconductor dummy region (e.g., a silicon dummy region). In this architecture of the chip stack structure 100 (i.e., the SoIC structure), the manufacturing process and chip integration can be simplified. Therefore, the manufacturing cost of the chip stack structure 100 (i.e., the SoIC structure) can be reduced.

[0046] The monolithic chip stack structure 100 (i.e., SoIC structure) can be derived from, for example... Figures 2A to 2IThe illustrated Integral Fan-Out (InFO) packaging process is used for packaging. However, the monolithic chip stack structure 100 (i.e., the SoIC structure) can also be packaged using other suitable packaging processes, such as Chip-on-Wafer-on-S (CoWoS) packaging process, System-on-Integrated Substrate (SoIS) packaging process, etc.

[0047] Figures 2A to 2I A cross-sectional view schematically illustrating a process flow for manufacturing a PoP (PoP) structure in some embodiments of this disclosure is shown.

[0048] Please refer to Figure 2A A carrier plate 60 is provided, comprising a bond remover layer 62 formed thereon. In some embodiments, the carrier plate 60 is a glass substrate, a ceramic carrier, etc. The carrier plate 60 may have a circular top-view shape and may be the size of a silicon wafer. For example, the carrier plate 60 may have an 8-inch diameter, a 12-inch diameter, or other sizes. The bond remover layer 62 may be formed of a polymer base material (e.g., a light-to-heat-conversion (LTHC) material), which may then be removed together with the carrier plate 60 from an overlying structure to be formed in subsequent steps. In some embodiments, the bond remover layer 62 is formed of an epoxy-based heat-release material. In other embodiments, the bond remover layer 62 is formed of a UV adhesive. The bond remover layer 62 may be applied and cured in a liquid state. In an alternative embodiment, the bond remover layer 62 is a laminated film, and the bond remover layer 62 is laminated onto the carrier plate 60. The top surface of the bond remover layer 62 is substantially planar.

[0049] Please refer to Figures 2A to 2C A redistribution structure 61, including a dielectric layer 64, redistribution wiring 66, and a dielectric layer 68, is formed on the debonding layer 62, such that the debonding layer 62 is located between the carrier board 60 and the dielectric layer 64 of the redistribution structure 61. Figure 2A As shown, a dielectric layer 64 is formed on the bonding layer 62. In some embodiments, the dielectric layer 64 is formed of a polymer, which may also be a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or similar materials, which can be easily patterned using photolithography. In some embodiments, the dielectric layer 64 is formed of nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. Figure 2BAs shown, a redistribution wiring 66 is formed on dielectric layer 64. The formation of the redistribution wiring 66 may include forming a seed layer (not shown) above dielectric layer 64, forming a patterned mask (not shown), such as a photoresist layer, above the seed layer, and then performing an electroplating process on the exposed seed layer. The patterned mask and portions of the seed layer covered by the patterned mask are then removed to leave, as shown... Figure 2B The redistribution wiring 66 is shown. According to some embodiments, the seed layer includes a titanium layer and a copper layer covering the titanium layer. For example, the seed layer can be formed using physical vapor deposition (PVD). For example, electroplating can be performed using electroless plating. Figure 2C As shown, dielectric layer 68 is formed on dielectric layer 64 to cover redistribution wiring 66. The bottom surface of dielectric layer 68 contacts the top surface of redistribution wiring 66 and the top surface of dielectric layer 64. According to some embodiments of this disclosure, dielectric layer 68 is formed of a polymer, which may be a photosensitive material such as PBO, PI, BCB, etc. In some embodiments, dielectric layer 68 is formed of oxides such as silicon nitride, silicon oxide, phosphosilicate glass, borosilicate glass, and borosilicate glass. The dielectric layer 68 is then patterned to form openings 70 therein. Therefore, multiple portions of redistribution wiring 66 are exposed through the openings 70 in dielectric layer 68. For illustrative purposes, Figure 2C The following diagrams illustrate a single redistribution wiring structure 61 with a single layer of redistribution wiring 66, and some embodiments may have multiple layers of redistribution wiring 66 by repeating the process discussed above.

[0050] Please refer to Figure 2D After a redistribution wiring structure 61 is formed on the bonding layer 62 supported by the carrier 60, metal pillars 72 are formed on the redistribution wiring structure 61, and the metal pillars 72 are electrically connected to the redistribution wiring 66 of the redistribution wiring structure 61. Throughout the description of this disclosure, because the metal pillars 72 penetrate the subsequently formed molding material (such as... Figure 2G As shown), the metal pillar 72 may be referred to as a conductive via 72. In some embodiments, the conductive via 72 is formed by electroplating. The electroplating of the conductive via 72 may include forming a blanket-type seed layer (not shown) over the dielectric layer 68 and extending to... Figure 2C Within the opening 70 shown, photoresist (not shown) is formed and patterned; and conductive vias 72 are electroplated on multiple portions of the seed layer exposed by the opening in the photoresist. Then, the photoresist and the multiple portions of the seed layer covered by the photoresist are removed. The material of the conductive via 72 may include copper, aluminum, or other similar materials. The conductive via 72 may be rod-shaped. The top view shape of the conductive via 72 may be circular, rectangular, square, hexagonal, etc.

[0051] Please refer to Figure 2EAfter forming the conductive via 72, a grain attachment film 50 is provided on the bottom surface of the supporting substrate C2. In some embodiments, in Figure 1L Prior to the monomerization process illustrated, a grain attachment film 50 is formed on the bottom surface of the supporting substrate C2. In some other embodiments, Figure 2E The attached film 54 shown is a selective component.

[0052] At least one monolithic chip stack structure 100 is picked up and placed onto the redistribution structure 61. The at least one monolithic chip stack structure 100 can be bonded to the redistribution structure 61 through the die-attachment film 50. For illustrative purposes, Figure 2E Only a single chip stack structure 100 and its surrounding conductive vias 72 are shown. However, it should be noted that... Figures 2A to 2I The process steps illustrated herein can be described as wafer-level processes. The chip stack structure 100 is surrounded by conductive vias 72. For example... Figure 2E As shown, the die attachment film 50 is attached between the chip stack structure 100 and the redistribution circuit structure 61, and the die attachment film 50 is attached to the redistribution circuit structure 61.

[0053] refer to Figure 2F An insulating encapsulation material 76 is formed over the redistributed circuit structure 61 to cover the chip stack structure 100 and the conductive vias 72. The insulating encapsulation material 76 can be a molding compound (e.g., epoxy resin or other suitable resin) formed through an over-molding process. The insulating encapsulation material 76 fills not only the gaps between adjacent conductive vias 72, but also the gaps between the conductive vias 72 and the chip stack structure 100. The insulating encapsulation material 76 covers the top surface of the dielectric layer 48 of the chip stack structure 100.

[0054] Next, as Figure 2F and Figure 2G As shown, planarization is performed, such as chemical mechanical polishing (CMP) and / or mechanical polishing, to partially remove the insulating encapsulation material 76 and dielectric layer 48 of the chip stack structure 100 until the conductive vias 72 and conductive pillars 46a of the chip stack structure 100 are exposed. After the insulating encapsulation material 76 is thinned, as... Figure 2GAs shown, an insulating enclosure 76' is formed that laterally covers the chip stack structure 100 and the conductive via 72. Due to planarization, the conductive via 72 penetrates the insulating enclosure 76'. The top of the conductive via 72 is substantially flush with or coplanar with the top surface of the dielectric layer 48, and within process variations, the top of the conductive via 72 is substantially flush with or coplanar with the top surface of the insulating enclosure 76'. In the exemplary embodiment shown, planarization is performed until the conductive via 72 and the conductive post 46a of the chip stack structure 100 are exposed.

[0055] refer to Figure 2H A redistribution circuit structure 77, including a dielectric layer 78, redistribution wiring 80, dielectric layer 82, redistribution wiring 86, and dielectric layer 88, is formed on the chip stack structure 100 and the insulating encapsulation 76'. After forming the redistribution circuit structure 77, a plurality of solder areas are formed on the redistribution circuit structure 77, and the solder areas include under bump metal (UBM) 92 and electrical connectors 94 disposed on the UBM 92.

[0056] A dielectric layer 78 is formed to cover the dielectric layer 48, the conductive pillar 46a, and the insulating encapsulation 76'. In some embodiments, the dielectric layer 78 is formed of a polymer such as PBO or PI. In some other embodiments, the dielectric layer 78 is formed of silicon nitride, silicon oxide, or the like. Openings may be formed in the dielectric layer 78 to expose conductive vias 72 and conductive pillars 46a. The formation of openings in the dielectric layer 78 can be performed using a photolithography process.

[0057] Next, a redistribution wiring 80 is formed to connect to the conductive post 46a and the conductive via 72. The redistribution wiring 80 may also interconnect the conductive post 46a and the conductive via 72. The redistribution wiring 80 may include metal traces (metal lines) located above the dielectric layer 78 and metal vias extending into openings defined in the dielectric layer 78 to facilitate electrical connection to the conductive via 72 and the conductive post 46a. In some embodiments, the redistribution wiring 80 is formed by an electroplating process, wherein each redistribution wiring 80 includes a seed layer (not shown) and an electroplated metal material located above the seed layer. The seed layer and the electroplated material may be formed of the same material or different materials. The redistribution wiring 80 may include metal or metal alloys comprising aluminum, copper, tungsten, and alloys of the aforementioned materials. The redistribution wiring 80 may be formed of a non-solder material. The via portions of the redistribution wiring 80 may physically contact the top surfaces of the conductive via 72 and the conductive post 46a.

[0058] Then, a dielectric layer 82 is formed over the redistribution wiring 80 and the dielectric layer 78. The dielectric layer 82 can be formed using a polymer, and the polymer can be selected from the same candidate materials as the dielectric layer 78. For example, the dielectric layer 82 may include PBO, PI, BCB, etc. In some embodiments, the dielectric layer 82 may include an organic dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. Openings may also be formed in the dielectric layer 82 to expose the redistribution wiring 80. The formation of the openings defined in the dielectric layer 82 can be performed using a photolithography process. The formation and materials of the redistribution wiring 86 can employ similar methods and materials as those used to form the redistribution wiring 80.

[0059] The dielectric layer 88 may be a polymer layer, and this polymer layer may also be formed to cover the redistribution wiring 86 and the dielectric layer 82. The dielectric layer 88 may be selected from the same candidate polymers used to form the dielectric layers 78 and 82. Openings may be formed in the dielectric layer 88 to expose the metal pad portions of the redistribution wiring 86. The formation of the openings defined in the dielectric layer 88 may be performed using a photolithography process.

[0060] The formation of UBM92 may include deposition and patterning. The formation of electrical connector 94 may include placing solder on an exposed portion of UBM92 and then reflowing the solder to form solder balls. In some embodiments, the formation of electrical connector 94 includes performing an electroplating step to form solder regions on redistribution wiring 86 and then reflowing the solder regions. In some other embodiments, electrical connector 94 includes metal pillars or includes metal pillars and solder caps, and the solder caps may also be formed by electroplating. Throughout the description of this disclosure, the combined structure including chip stack structure 100, conductive via 72, insulating encapsulation 76', redistribution wiring structure 61, redistribution wiring structure 77, UBM92, and electrical connector 94 may be referred to as a wafer-level package, and this wafer-level package may represent a composite wafer having a circular top view.

[0061] Please refer to Figure 2H and Figure 2IThen, a de-bonding process is performed to separate the carrier 60 from the wafer-level package. After the de-bonding process, the dielectric layer 64 of the redistributed circuitry 61 is exposed. During the de-bonding process, the debonding layer 62 is also removed from the wafer-level package. Debonding can be performed by irradiating the debonding layer 62 with light such as UV light or a UV laser to break it down. In the de-bonding process, tape (not shown) can be adhered to the dielectric layer 88 and the electrical connectors 94. In subsequent steps, the carrier 60 and the debonding layer 62 are removed from the wafer-level package. A monomerization process is then performed to... Figure 2H The chip-scale package shown in the figure is cut into Figure 2I The diagram shows multiple individualized integrated fan-out packages P1.

[0062] A patterning process is performed to form openings in the dielectric layer 64 to expose the redistribution wiring 66. The formation of the openings defined in the dielectric layer 64 can be performed using a photolithography process. A top package P2 is then provided and bonded to an integrated fan-out package P1 (i.e., a bottom package) to form a stacked package (PoP) structure. In some embodiments disclosed herein, the bonding between the top package P2 and the integrated fan-out package P1 is achieved via electrical connectors 96 (e.g., solder pads) that connect the metal pad portions of the redistribution wiring 66 to metal pads in the top package P2. An underfill adhesive 98 can be formed to fill the gap between the top package P2 and the integrated fan-out package P1, such that the underfill adhesive 98 laterally covers the electrical connector 96, and the reliability of the electrical connector 96 is enhanced. In some embodiments, the top package P2 includes a semiconductor die 202, which may be a memory die, such as a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. In some exemplary embodiments, the memory die may also be bonded to the package substrate 204.

[0063] According to some embodiments disclosed herein, a chip stack structure is provided, comprising a first semiconductor die, a second semiconductor die, a bridging die, and a gap-filling material. The first semiconductor die includes a plurality of integrated circuit regions. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The bridging die is disposed above and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridging die. The gap-filling material is disposed on the first semiconductor die to laterally cover the bridging die and the second semiconductor die. In some embodiments, the first semiconductor die includes a first bonding structure, each second semiconductor die includes a second bonding structure, the bridging die includes a third bonding structure, the second bonding junctions of each second semiconductor die contact and are electrically connected to the first bonding structure, and the third bonding structure contacts and is electrically connected to the first bonding structure. In some embodiments, a first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first bonding structure disposed on and electrically connected to the first interconnect structure; each second semiconductor die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second bonding structure disposed on and electrically connected to the second interconnect structure; a bridging die includes a third semiconductor substrate, a third interconnect structure disposed on the third semiconductor substrate, and a third bonding structure disposed on and electrically connected to the third interconnect structure; the second bonding structure of each second semiconductor die contacts and is electrically connected to the first bonding structure; and the third bonding structure contacts and is electrically connected to the first bonding structure. In some embodiments, the first semiconductor die further includes a conductive via through the first semiconductor substrate, the first interconnect structure and the first bonding structure are disposed on opposite sides of the first semiconductor substrate, and the first interconnect structure is electrically connected to the first bonding structure via the conductive via. In some embodiments, the aforementioned chip stack structure further includes conductive terminals disposed on and electrically connected to the first interconnect structure of the first semiconductor die. In some embodiments, a first bonding structure includes a first bonding dielectric layer and a first bonding conductor embedded in the first bonding dielectric layer; a second bonding structure includes a second bonding dielectric layer and a second bonding conductor embedded in the second bonding dielectric layer; a third bonding structure includes a third bonding dielectric layer and a third bonding conductor embedded in the third bonding dielectric layer, wherein the first bonding conductor is bonded to the second bonding conductor and the third bonding conductor, and the second bonding dielectric layer and the third bonding dielectric layer are bonded to multiple portions of the first bonding dielectric layer. In some embodiments, second semiconductor dies are arranged side-by-side on the first semiconductor dies, and bridging dies are disposed between the second semiconductor dies.In some embodiments, the aforementioned chip stack structure further includes a support substrate, wherein the gap-filling material, the second semiconductor die, and the bridging die are disposed between the support substrate and the first semiconductor die. In some embodiments, the first semiconductor die further includes a dummy region, and the integrated circuit regions are separated by the dummy region.

[0064] According to some alternative embodiments of this disclosure, a chip stack structure is provided, comprising a first semiconductor die, a second semiconductor die, and a bridging die. The first semiconductor die includes a first integrated circuit region and a second integrated circuit region spaced apart from the first integrated circuit region. The second semiconductor die is disposed above and electrically connected to the first and second integrated circuit regions. The bridging die is disposed above and electrically connected to the first and second integrated circuit regions. In some embodiments, the aforementioned chip stack structure further includes a gap-filling material, which laterally covers the bridging die and the second semiconductor die. In some embodiments, the aforementioned chip stack structure further includes an adhesive layer and a support substrate, wherein the support substrate is adhered to the gap-filling material, the second semiconductor die, and the bridging die through the adhesive layer. In some embodiments, the sidewalls of the support substrate are substantially aligned with the sidewalls of the gap-filling material and the sidewalls of the first semiconductor die. In some embodiments, the lateral dimensions of the support substrate are substantially the same as the lateral dimensions of the first semiconductor die. In some embodiments, the thickness of the second semiconductor die is substantially the same as the thickness of the bridging die.

[0065] According to some alternative embodiments of this disclosure, a chip stack structure is provided, comprising a first semiconductor die, a second semiconductor die, and a bridging die. The first semiconductor die includes an integrated circuit region and a bonding structure, wherein the bonding structure covers the integrated circuit region, and the integrated circuit regions are laterally spaced apart from each other. The second semiconductor die is thus disposed on the integrated circuit region and electrically connected to the integrated circuit region through the bonding structure. The bridging die is disposed on the bonding structure and electrically connected to the integrated circuit region through the bonding structure. In some embodiments, the aforementioned chip stack structure further includes a gap-filling material laterally covering the bridging die and the second semiconductor die, wherein the gap-filling material, the second semiconductor die, and the bridging die are substantially uniform in thickness. In some embodiments, the aforementioned chip stack structure further includes a support substrate, wherein the support substrate is adhered to the gap-filling material, the second semiconductor die, and the bridging die. In some embodiments, the sidewalls of the support substrate are substantially aligned with the sidewalls of the first semiconductor die and the sidewalls of the gap-filling material. In some embodiments, the first semiconductor die further includes a dummy region located between integrated circuit regions, a bridging die disposed on and covering the dummy region, and the integrated circuit regions being spaced apart from each other through the dummy region.

[0066] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this invention. Those skilled in the art should understand that they can readily use this invention as the basis for designing or modifying other processes and structures to achieve the same objectives and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that various changes, substitutions, and modifications can be made to such equivalent constructions without departing from the spirit and scope of this invention.

Claims

1. A chip stack structure, characterized in that, include: The first semiconductor die includes multiple integrated circuit regions; A plurality of second semiconductor dies are disposed on the first semiconductor die and electrically connected to the first semiconductor die; A bridging die is disposed on the first semiconductor die and electrically connected to the first semiconductor die, and the plurality of integrated circuit regions are electrically connected to each other through the bridging die; as well as A gap-filling layer is disposed on the first semiconductor die to laterally cover the bridging die and the plurality of second semiconductor dies.

2. The chip stack structure according to claim 1, characterized in that, The first semiconductor die includes a first bonding structure, each of the plurality of second semiconductor dies includes a second bonding structure, the bridging die includes a third bonding structure, the second bonding structure of each of the plurality of second semiconductor dies is in contact with and electrically connected to the first bonding structure, and the third bonding structure is in contact with and electrically connected to the first bonding structure.

3. The chip stack structure according to claim 1, characterized in that, in The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first bonding structure disposed on and electrically connected to the first interconnect structure. Each of the plurality of second semiconductor grains includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second bonding structure disposed on and electrically connected to the second interconnect structure. The bridging die includes a third semiconductor substrate, a third interconnect structure disposed on the third semiconductor substrate, and a third bonding structure disposed on and electrically connected to the third interconnect structure. The second bonding structure of each of the plurality of second semiconductor grains is in contact with and electrically connected to the first bonding structure, and The third bonding structure is in contact with the first bonding structure and is electrically connected to the first bonding structure.

4. The chip stack structure according to claim 2, characterized in that, The first bonding structure includes a first bonding dielectric layer and a first bonding conductor embedded in the first bonding dielectric layer; the second bonding structure includes a second bonding dielectric layer and a second bonding conductor embedded in the second bonding dielectric layer; the third bonding structure includes a third bonding dielectric layer and a third bonding conductor embedded in the third bonding dielectric layer; the first bonding conductor is bonded to the second bonding conductor and the third bonding conductor; and the second bonding dielectric layer and the third bonding dielectric layer are bonded to multiple portions of the first bonding dielectric layer.

5. The chip stack structure according to claim 1, characterized in that, The plurality of second semiconductor dies are arranged side-by-side on the first semiconductor die, and the bridging die is disposed between the plurality of second semiconductor dies.

6. The chip stack structure according to claim 1, characterized in that, Including: A support substrate, wherein the gap filling layer, the plurality of second semiconductor grains, and the bridging grains are disposed between the support substrate and the first semiconductor grains.

7. The chip stack structure according to claim 1, characterized in that, The first semiconductor die further includes a dummy region, and the plurality of integrated circuit regions are spaced apart from each other through the dummy region.

8. A chip stack structure, characterized in that, include: The first semiconductor die includes a first integrated circuit region and a second integrated circuit region spaced apart from the first integrated circuit region; The second semiconductor die is disposed on the first integrated circuit region and the second integrated circuit region, and is electrically connected to the first integrated circuit region and the second integrated circuit region; as well as A bridging die is disposed on the first integrated circuit region and the second integrated circuit region, and is electrically connected to the first integrated circuit region and the second integrated circuit region.

9. A chip stack structure, characterized in that, include: A first semiconductor die includes a plurality of integrated circuit regions and a bonding structure, wherein the bonding structure covers the plurality of integrated circuit regions and the plurality of integrated circuit regions are laterally spaced apart from each other. A second semiconductor die is disposed on the plurality of integrated circuit regions and is electrically connected to the plurality of integrated circuit regions through the bonding structure; as well as A bridging die is disposed on the bonding structure and electrically connected to the plurality of integrated circuit regions through the bonding structure.

10. The chip stack structure according to claim 9, characterized in that, Including: The gap-filling layer laterally covers the bridging die and the second semiconductor die; and A support substrate, wherein the support substrate is adhered to the gap filling layer, the second semiconductor die, and the bridging die.

Images