Display panel and near-to-eye display device
By stacking transistors and adding a hydrogen atom isolation layer in the thickness direction of the display panel, the problems of large transistor footprint and susceptibility of oxides to hydrogen atoms are solved, thus achieving integration and improved stability of the display panel.
Patent Information
- Application Number
- CN202520346722.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-02-28
AI Technical Summary
Existing display panels have large transistors of different types that occupy a large area and have low integration density. Furthermore, the oxide active layer is prone to reacting with hydrogen atoms, affecting electrical performance and leading to stability and reliability issues.
The first transistor and the second transistor are stacked together, and a hydrogen atom isolation layer is set in the thickness direction of the display panel to prevent hydrogen atoms from reacting with oxides. The oxide transistor and the metal-oxide-semiconductor transistor are combined to improve the electrical performance.
This achieves an integrated and compact structure for the display panel, improving stability and reliability, reducing the transistor footprint, and preventing performance degradation of oxide transistors.
Smart Images
Figure CN223844147U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to a display panel and a near-eye display device. Background Technology
[0002] With the continuous development of information technology, the application fields of display panels are rapidly expanding, covering multiple fields such as consumer electronics, intelligent transportation, smart homes, medical care, and industrial control.
[0003] Currently, different types of transistors in display panels are arranged on the same horizontal plane. As a result, the transistors occupy a large area of the display panel and have a low integration density. In addition, when the active layer of the transistor includes oxide, the hydrogen atoms in the display panel are prone to react with the oxide, which will affect the electrical performance of the transistor and thus affect the stability and reliability of the display panel. Utility Model Content
[0004] This utility model provides a display panel and a near-eye display device to reduce the area of the display panel, achieve integrated display panel setup, prevent hydrogen atoms from affecting the performance of the first active layer, and improve the stability and reliability of the display panel.
[0005] In a first aspect, the present invention provides a display panel; the display panel includes: a substrate, a first transistor and a second transistor stacked together, the first transistor being located on the side of the second transistor away from the substrate, and the first transistor being electrically connected to the second transistor;
[0006] The first transistor includes a first active layer, which includes an oxide layer.
[0007] The display panel further includes at least one hydrogen atom isolation layer, which is located on at least one side of the first active layer along the thickness direction of the display panel.
[0008] Optionally, the first transistor further includes a first gate and a second gate; the first gate is located on the side of the first active layer away from the substrate, and the second gate is located on the side of the first active layer close to the substrate;
[0009] The second transistor includes a third gate; the third gate is located on the side of the substrate closer to the first transistor;
[0010] At least one hydrogen atom isolation layer includes a first hydrogen atom isolation layer and a second hydrogen atom isolation layer;
[0011] The first hydrogen atom isolation layer is located between the first active layer and the first gate; the second hydrogen atom isolation layer is located between the second gate and the third gate.
[0012] Optionally, the first transistor further includes a first gate insulating layer and a second gate insulating layer;
[0013] The first gate insulating layer is located between the first gate and the first hydrogen atom isolation layer; the second gate insulating layer is located between the second gate and the first active layer.
[0014] The second transistor further includes a third gate insulating layer; the third gate insulating layer is located between the substrate and the third gate.
[0015] Optionally, the hydrogen atom isolation layer covers the first active layer along the thickness direction of the display panel.
[0016] Optionally, the thickness H1 of the hydrogen atom isolation layer satisfies: 5nm ≤ H1 ≤ 10nm.
[0017] Optionally, the first transistor includes a first electrode and a second electrode, and the second transistor includes a third electrode and a fourth electrode;
[0018] The first electrode is electrically connected to the third electrode, and the second electrode is electrically connected to the fourth electrode;
[0019] The display panel also includes light-emitting elements;
[0020] The first electrode is electrically connected to the anode of the light-emitting element.
[0021] Optionally, the first transistor further includes a second gate; the second gate is located on the side of the first active layer near the substrate;
[0022] The display panel further includes a first connection structure and a second connection structure;
[0023] The first connection structure is electrically connected to the first electrode and the third electrode respectively, and the second connection structure is electrically connected to the second electrode and the fourth electrode respectively;
[0024] Both the first connection structure and the second connection structure are disposed on the same layer as the second gate.
[0025] Optionally, the first transistor includes an N-type transistor;
[0026] The second transistor includes a P-type transistor or an N-type transistor.
[0027] Optionally, the second transistor further includes a second active layer;
[0028] The substrate includes a silicon substrate, which is reused as the second active layer;
[0029] The second transistor includes a P-type transistor, and the silicon substrate includes an N-type doped well; or, the second transistor includes an N-type transistor, and the silicon substrate includes a P-type doped well.
[0030] Secondly, embodiments of the present invention also provide a near-eye display device, including the display panel described in any of the first aspects.
[0031] The technical solution provided by this utility model embodiment includes a display panel comprising a substrate, a first transistor and a second transistor stacked together. By stacking the first transistor and the second transistor instead of placing them on the same horizontal plane, the area occupied by the transistors on the display panel can be reduced, thereby enabling the integrated arrangement of the devices and a compact structure. In addition, along the thickness direction of the display panel, a hydrogen atom isolation layer is located on at least one side of the first active layer. Since the first active layer includes an oxide, the oxide is prone to react with hydrogen atoms, thereby affecting the electrical characteristics of the first transistor. Thus, by setting a hydrogen atom isolation layer, the electrical performance of the first transistor can be guaranteed, which is beneficial to ensuring the stability and reliability of the display panel. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the structure of a first type of display panel provided in an embodiment of the present utility model;
[0033] Figure 2 This is a schematic diagram of the structure of a second type of display panel provided in an embodiment of the present utility model;
[0034] Figure 3 This is a schematic diagram of the structure of a third type of display panel provided in an embodiment of the present utility model;
[0035] Figure 4 This is a schematic diagram of the structure of a near-eye display device provided in an embodiment of the present invention. Detailed Implementation
[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, not the entire structure.
[0037] Figure 1 This is a schematic diagram of the structure of a first type of display panel provided in an embodiment of the present utility model, as shown below. Figure 1As shown, the display panel 100 includes a substrate 10, a first transistor 20 and a second transistor 30 stacked together. The first transistor 20 is located on the side of the second transistor 30 away from the substrate 10, and the first transistor 20 and the second transistor 30 are electrically connected. The first transistor 20 includes a first active layer 201, which includes an oxide layer. The display panel 100 also includes at least one hydrogen atom isolation layer 40, which is located on at least one side of the first active layer 201 along the thickness direction of the display panel (Z direction as shown in the figure).
[0038] Specifically, the first transistor 20 and the second transistor 30 are stacked, with the first transistor 20 located on the side of the second transistor 30 away from the substrate 10. In other words, the first transistor 20 and the second transistor 30 are stacked vertically, with the first transistor 20 positioned above the second transistor 30. Compared to existing technologies that place multiple transistors of different types along the same horizontal plane, vertically stacking two transistors reduces the area of the display panel, increases integration density, and helps ensure a compact display panel structure.
[0039] Specifically, the first transistor 20 and the second transistor 30 are electrically connected, so that the electrical signal can be transmitted to the light-emitting element sequentially through the second transistor 30 and the first transistor 20 to realize the display function of the display panel. The first transistor 20 includes a first active layer 201. When a voltage is applied to the gate, a conductive channel is formed in the first active layer 201, allowing current to pass through the first active layer 201. Specifically, the first active layer 201 includes oxide, that is, the first transistor 20 is an oxide transistor. Oxide transistors have low leakage current, which can achieve more stable signal transmission. In addition, oxide transistors have extremely low turn-off current and high on / off ratio, which can significantly reduce static power consumption. For example, the first transistor 20 can be an indium gallium zinc oxide thin film transistor, and the second transistor 30 can be a metal-oxide-semiconductor transistor. Metal-oxide-semiconductor transistors have low on-resistance and excellent thermal characteristics, which can effectively improve the stability of the display panel. Furthermore, the embodiments of the present invention combine metal-oxide-semiconductor transistors and oxide transistors, which is beneficial to realizing a display panel with good stability. Furthermore, by stacking two types of transistors, it is beneficial to reduce the size of the display panel and achieve miniaturization of the display panel.
[0040] It should be noted that the organic materials in display panels contain hydrogen atoms. For example, in some organic light-emitting diode (OLED) materials, hydrogen atoms participate as part of the organic molecule, forming stable chemical bonds and molecular structures. Furthermore, hydrogen atoms may also be introduced through chemical reactions during material synthesis; for instance, hydrogen atoms can function as part of certain organic groups.
[0041] Specifically, the display panel 100 further includes at least one hydrogen atom isolation layer 40, which serves to isolate hydrogen atoms. Since the first active layer 201 includes an oxide layer, meaning it is a hydrogen-sensitive layer, the oxide in the first active layer 201 readily reacts with hydrogen atoms, thus affecting its electrical performance. This embodiment of the invention, by providing a hydrogen atom isolation layer 40 along the thickness direction Z of the display panel and positioning it on at least one side of the first active layer 201, blocks hydrogen atoms from reacting with the oxide in the first active layer 201, thereby ensuring the stability of the first transistor and improving the performance of the display panel.
[0042] For example, the hydrogen atom isolation layer 201 can be an atomically deposited thin film such as aluminum oxide or hafnium oxide, capable of blocking hydrogen atoms. For example, the hydrogen atom isolation layer 40 can be prepared using atomic layer deposition (ALD), which helps ensure the density and surface smoothness of the hydrogen atom isolation layer 40, thereby ensuring its effective blocking of hydrogen atoms. Furthermore, the hydrogen atom isolation layer 40 prepared using ALD has good adhesion, preventing delamination and other phenomena in the film structure of the display panel, thus helping to ensure the stability of the film layer and improve the stability and reliability of the display panel.
[0043] like Figure 1 As shown, the hydrogen atom isolation layer 40 can be located on the side of the first active layer 201 away from the substrate 10. Figure 2 This is a schematic diagram of the structure of the second type of display panel provided in an embodiment of the present utility model, as shown below. Figure 2 As shown, the hydrogen atom isolation layer 40 can also be located on the side of the first active layer 201 close to the substrate 10. For example, the hydrogen atom isolation layer 40 can also be located on the upper and lower sides of the first active layer 201. This allows for diverse configurations of the display panel and further blocks hydrogen atoms on both sides of the first active layer 201, which helps to further improve the reliability and stability of the display panel.
[0044] The display panel provided in this embodiment of the present invention reduces the area occupied by the transistors on the display panel 100 by stacking the first transistor 20 and the second transistor 30 instead of placing them on the same horizontal plane, thereby enabling integrated device placement and a compact structure. In addition, along the thickness direction Z of the display panel, the hydrogen atom isolation layer 40 is located on at least one side of the first active layer 201. Since the first active layer 201 includes an oxide, the oxide is prone to react with hydrogen atoms, thereby affecting the electrical characteristics of the first transistor 20. Thus, by setting the hydrogen atom isolation layer 401, the electrical performance of the first transistor 20 can be guaranteed, which is beneficial to ensuring the stability and reliability of the display panel 100.
[0045] Optional, Figure 3 This is a schematic diagram of the structure of a third type of display panel provided in an embodiment of the present utility model, as shown below. Figure 3 As shown, the first transistor 20 further includes a first gate 202 and a second gate 203; the first gate 202 is located on the side of the first active layer 201 away from the substrate 10, and the second gate 203 is located on the side of the first active layer 201 close to the substrate 10; the second transistor 30 includes a third gate 301; the third gate 301 is located on the side of the substrate 10 close to the first transistor 20; at least one hydrogen atom isolation layer 40 includes a first hydrogen atom isolation layer 401 and a second hydrogen atom isolation layer 402; the first hydrogen atom isolation layer 401 is located between the first active layer 201 and the first gate 202; the second hydrogen atom isolation layer 402 is located between the second gate 203 and the third gate 301.
[0046] Specifically, the first transistor 20 also includes a first gate 202 and a second gate 203. The first gate 202 can be understood as the top gate of the first transistor 20, and the second gate 203 can be understood as the bottom gate of the first transistor 20. Through the synergistic effect of the two gates, the channel charge distribution can be controlled more precisely, thereby achieving higher switching speed, lower leakage current, and better device performance.
[0047] Specifically, the two hydrogen atom isolation layers 40 include a first hydrogen atom isolation layer 401 located between the first active layer 201 and the first gate 202, and a second hydrogen atom isolation layer 402 located between the second gate 203 and the third gate 301. In other words, the first hydrogen atom isolation layer 401 is located above the first active layer 201, and the second hydrogen atom isolation layer 402 is located below the first active layer 201. That is, the two hydrogen atom isolation layers 40 are located on the upper and lower sides of the first active layer, respectively. This can further prevent hydrogen atoms from contacting the first active layer 201 in both the upper and lower directions, prevent hydrogen atoms from reacting with oxides, enhance the stability of the first transistor 20, and help to further ensure the stability and reliability of the display panel.
[0048] For example, the number of hydrogen atom isolation layers 40 can be three or even more, in order to better block hydrogen atoms.
[0049] Optional, continue to refer to Figure 3 The first transistor 20 further includes a first gate insulating layer 204 and a second gate insulating layer 205; the first gate insulating layer 204 is located between the first gate 202 and the first hydrogen atom isolation layer 401; the second gate insulating layer 205 is located between the second gate 203 and the first active layer 201; the second transistor 30 further includes a third gate insulating layer 302; the third gate insulating layer 302 is located between the substrate 10 and the third gate 301.
[0050] Specifically, the first gate insulating layer 204 is located between the first gate 202 and the first hydrogen atom isolation layer 401. Since the preparation of the first hydrogen atom isolation layer 401 using atomic layer deposition requires a certain preparation time, and the greater the thickness of the first hydrogen atom isolation layer 401, the longer the preparation time. Therefore, with a shorter preparation time, the thickness of the prepared first hydrogen atom isolation layer 401 will not be too thick. Thus, by setting the first gate insulating layer 204, the thickness of the insulating layer between the first gate 202 and the first hydrogen atom isolation layer 401 can be increased, thereby improving the breakdown voltage performance of the first transistor 20. Furthermore, by setting the second gate insulating layer 205, the thickness of the insulating layer between the second gate 203 and the first active layer 201 can be increased, which is beneficial for further improving the breakdown voltage performance of the first transistor 20.
[0051] Specifically, by setting a third gate insulating layer 302, on the one hand, current leakage between the third gate 301 and the second active layer 305 can be prevented; on the other hand, the third gate insulating layer 302 can adjust the charge carrier concentration on the surface of the second active layer 305 by controlling the electric field distribution, thereby achieving precise control of the device conductivity and thus improving the performance of the second transistor 30.
[0052] Optional, continue to refer to Figure 1 Along the thickness direction Z of the display panel, the hydrogen atom isolation layer 40 covers the first active layer 201.
[0053] Specifically, along the thickness direction Z of the display panel, the hydrogen atom isolation layer 40 covers the first active layer 201. That is, the projected area of the hydrogen atom isolation layer 40 on the substrate 10 is greater than or equal to the projected area of the first active layer 201 on the substrate 10. This helps to ensure the blocking effect of the hydrogen atom isolation layer 40 on hydrogen atoms, further preventing hydrogen atoms from contacting and reacting with the first active layer 201, which can improve the performance of the first transistor 20, thereby improving the stability and reliability of the display panel.
[0054] Optional, continue to refer to Figure 1 The thickness H1 of the hydrogen atom isolation layer 40 satisfies: 5nm≤H1≤10nm.
[0055] For example, when H1 < 5 nm, the thickness of the hydrogen atom isolation layer 40 is relatively thin, which is not conducive to blocking hydrogen atoms. This means that hydrogen atoms will still react with the oxide in the first active layer 201, thus affecting the performance of the first transistor 20. For example, when H1 > 10 nm, the thickness of the hydrogen atom isolation layer 40 is relatively large. This results in a thicker display panel, making it impossible to achieve a thinner display panel, and also increases the deposition time of the hydrogen atom isolation layer 40, leading to low fabrication efficiency and high cost. This embodiment of the invention sets the thickness of the hydrogen atom isolation layer 40 to 5 nm ≤ H1 ≤ 10 nm, which is moderate. This ensures the blocking effect of the hydrogen atom isolation layer 40 on hydrogen atoms and is compatible with the atomic layer deposition process, resulting in a simple process and high fabrication efficiency.
[0056] Optional, continue to refer to Figure 1 The first transistor 20 includes a first electrode 206 and a second electrode 207, and the second transistor 30 includes a third electrode 303 and a fourth electrode 304; the first electrode 206 is electrically connected to the third electrode 303, and the second electrode 207 is electrically connected to the fourth electrode 304; the display panel also includes a light-emitting element 50; the first electrode 206 is electrically connected to the anode 501 of the light-emitting element 50.
[0057] Specifically, the first electrode 206 can be the signal output electrode of the first transistor 20, the second electrode 207 can be the signal input electrode of the first transistor 20, the third electrode 303 can be the signal output electrode of the second transistor 30, and the fourth electrode 304 can be the signal input electrode of the second transistor 30.
[0058] For example, electrical signals can flow sequentially from the second electrode 207 to the fourth electrode 304, the third electrode 303, the first electrode 206, and the anode 501 of the light-emitting element 50. At the same time, there are electrical signals from the second electrode 207 to the first electrode 206 and from the fourth electrode 304 to the third electrode 303 to ensure that the light-emitting element works and realizes the display function of the display panel.
[0059] Specifically, the first transistor 20 includes an N-type transistor, and the second transistor 30 includes either a P-type transistor or an N-type transistor. The first electrode 206 can be the source, and the second electrode 207 can be the drain. When the second transistor 30 includes an N-type transistor, the third electrode 303 can be the source, and the fourth electrode 304 can be the drain; when the second transistor 30 includes a P-type transistor, the third electrode 303 is the drain, and the fourth electrode 304 is the source, thus enabling diverse configurations for the display panel.
[0060] It should be noted that the display panel may also include a cathode 80 of the light-emitting element 50 and an encapsulation layer 90 located on the side of the cathode 80 away from the substrate 10. The encapsulation layer 90 can protect the light-emitting elements inside the display panel from corrosion by the external environment (such as moisture, oxygen, dust, etc.), thereby improving the reliability and lifespan of the display panel.
[0061] Optional, continue to refer to Figure 1 The first transistor 20 further includes a second gate 203; the second gate 203 is located on the side of the first active layer 201 close to the substrate 10; the display panel 100 further includes a first connection structure 60 and a second connection structure 70; the first connection structure 60 is electrically connected to the first electrode 206 and the third electrode 303 respectively, and the second connection structure 70 is electrically connected to the second electrode 207 and the fourth electrode 304 respectively; the first connection structure 60 and the second connection structure 70 are both disposed on the same layer as the second gate 203.
[0062] Specifically, the first connection structure 60 enables the electrical connection between the first electrode 206 and the third electrode 303, and the second connection structure 70 enables the electrical connection between the second electrode 207 and the fourth electrode 304. By setting the first connection structure 60 and the second connection structure 70, it is beneficial to ensure the stability of the connection between the electrodes, thereby improving the performance of the display panel.
[0063] Specifically, both the first connection structure 60 and the second connection structure 70 are disposed on the same layer as the second gate 203. This simple film layer arrangement is conducive to achieving a thinner display panel.
[0064] It is understandable that the first connection structure 60, the second connection structure 70, and the second gate 203 can be fabricated simultaneously, thus simplifying the fabrication of the two connection structures.
[0065] Optional, continue to refer to Figure 1 The second transistor 30 further includes a second active layer 305; the substrate 10 includes a silicon substrate 101, which is multiplexed as the second active layer 305; the second transistor 30 includes a P-type transistor, and the silicon substrate 101 includes an N-type doped well; or, the second transistor 30 includes an N-type transistor, and the silicon substrate 101 includes a P-type doped well.
[0066] Specifically, when a voltage is applied to the third gate 301, a conductive channel is formed in the second active layer 305, allowing current to pass through the second transistor 30. The silicon substrate 101 is reused as the second active layer 305, meaning there is no need to fabricate a separate second active layer on the substrate. This simplifies the fabrication of the second active layer 305 and facilitates the thinning of the display panel.
[0067] Specifically, P-type transistors are typically fabricated in N-type doped silicon substrates or N-type doped wells, while N-type transistors are fabricated in P-type substrates or P-type doped wells.
[0068] Based on the same inventive concept, this utility model embodiment also provides a near-eye display device. Figure 4 A schematic diagram of a near-eye display device provided for an embodiment of this utility model is shown below. Figure 4 As shown, the near-eye display device 1000 includes the display panel 100 in any of the above embodiments. Therefore, the near-eye display device 1000 provided by this utility model embodiment has the corresponding beneficial effects in the above embodiments, which will not be repeated here. For example, the near-eye display device can be an augmented reality (AR) display device, a virtual reality (VR) display device, an electronic view finder (EVF), a mobile phone, a computer, or a television, etc. This utility model embodiment does not limit it to these.
[0069] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A display panel, characterized in that, include: A substrate, a first transistor and a second transistor stacked together, wherein the first transistor is located on the side of the second transistor away from the substrate, and the first transistor and the second transistor are electrically connected; The first transistor includes a first active layer, which includes an oxide layer. The display panel further includes at least one hydrogen atom isolation layer, which is located on at least one side of the first active layer along the thickness direction of the display panel.
2. The display panel according to claim 1, characterized in that, The first transistor further includes a first gate and a second gate; the first gate is located on the side of the first active layer away from the substrate, and the second gate is located on the side of the first active layer close to the substrate; The second transistor includes a third gate; the third gate is located on the side of the substrate closer to the first transistor; At least one hydrogen atom isolation layer includes a first hydrogen atom isolation layer and a second hydrogen atom isolation layer; The first hydrogen atom isolation layer is located between the first active layer and the first gate; the second hydrogen atom isolation layer is located between the second gate and the third gate.
3. The display panel according to claim 2, characterized in that, The first transistor further includes a first gate insulating layer and a second gate insulating layer; The first gate insulating layer is located between the first gate and the first hydrogen atom isolation layer; the second gate insulating layer is located between the second gate and the first active layer. The second transistor further includes a third gate insulating layer; the third gate insulating layer is located between the substrate and the third gate.
4. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the hydrogen atom isolation layer covers the first active layer.
5. The display panel according to claim 1, characterized in that, The thickness H1 of the hydrogen atom isolation layer satisfies: 5nm≤H1≤10nm.
6. The display panel according to claim 1, characterized in that, The first transistor includes a first electrode and a second electrode, and the second transistor includes a third electrode and a fourth electrode; The first electrode is electrically connected to the third electrode, and the second electrode is electrically connected to the fourth electrode; The display panel also includes light-emitting elements; The first electrode is electrically connected to the anode of the light-emitting element.
7. The display panel according to claim 6, characterized in that, The first transistor further includes a second gate; the second gate is located on the side of the first active layer closer to the substrate; The display panel further includes a first connection structure and a second connection structure; The first connection structure is electrically connected to the first electrode and the third electrode respectively, and the second connection structure is electrically connected to the second electrode and the fourth electrode respectively; Both the first connection structure and the second connection structure are disposed on the same layer as the second gate.
8. The display panel according to claim 1, characterized in that, The first transistor includes an N-type transistor; The second transistor includes a P-type transistor or an N-type transistor.
9. The display panel according to claim 8, characterized in that, The second transistor also includes a second active layer; The substrate includes a silicon substrate, which is reused as the second active layer; The second transistor includes a P-type transistor, and the silicon substrate includes an N-type doped well; or, the second transistor includes an N-type transistor, and the silicon substrate includes a P-type doped well.
10. A near-eye display device, characterized in that, Includes the display panel as described in any one of claims 1-9.