Array substrate, display substrate, display panel and display device
By setting a first via and a first isolation structure at the edge of the array substrate, water vapor is blocked from moving towards the transistor, thus solving the threshold voltage shift problem caused by water vapor and improving the reliability and display duration of the array substrate in high temperature and high humidity environments.
Patent Information
- Application Number
- CN202520015669.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-03
AI Technical Summary
In high temperature and high humidity environments, water vapor enters the active layer of the thin-film transistor (TFT) on the array substrate and combines with the metal oxide, causing a shift in the threshold voltage and affecting the functional characteristics of the transistor.
A first via is provided at the edge of the array substrate, and a first isolation structure is provided in the via to block water vapor from moving toward the transistor and reduce the bonding of water vapor with the active layer.
It effectively reduces the impact of water vapor on the functional characteristics of transistors, improves the reliability of the array substrate in high temperature and high humidity environments, and extends the normal display time.
Smart Images
Figure CN223844150U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to an array substrate, a display substrate, a display panel, and a display device. Background Technology
[0002] For array substrates, THO (Thermal Humidity Operation) and HTO (High Temperature Operation) are important evaluation criteria that can test the performance of the array substrate in high temperature and high humidity environments.
[0003] In one example, for a new screen product, the screen is operated in a harsh environment of high temperature and high humidity, and the duration of normal display is recorded. The longer the normal display duration, the better the evaluation score of the screen. Under normal circumstances, its normal display duration should be greater than or equal to 1000 hours.
[0004] In actual testing, it was found that when the screen ran for 1000 hours under different reliability conditions, the TFTs (Threshold Voltage) in the array substrate exhibited different Vth (Threshold Voltage) offsets.
[0005] The main reason for this phenomenon is that water vapor in the air can enter the interior of the array substrate and reach the active layer, combining with the metal oxides of the active layer, thus affecting the functional characteristics of the transistors. For example, the flexible layer of the array substrate can absorb water vapor from the air, allowing it to enter the internal structure of the display panel. Furthermore, within the internal structure of the array substrate, materials in other functional layers also absorb water vapor, which is then transferred to the active layer of the transistors, where it combines with the metal oxides, further affecting the transistor's functional characteristics. Utility Model Content
[0006] The purpose of this invention is to provide an array substrate, a display substrate, a display panel, and a display device to reduce the impact of water vapor on the functional characteristics of transistors in the array substrate. The specific technical solution is as follows:
[0007] In a first aspect of this application, an array substrate is provided, the array substrate comprising a substrate, transistors, a first isolation structure, a wiring structure, a first insulating layer, an organic layer, a second insulating layer, a flexible layer, a sealing layer, and a cover plate.
[0008] The transistor and the wiring structure are disposed on the substrate;
[0009] The first insulating layer is located on the side of the transistor and the wiring structure away from the substrate, and is in contact with the wiring structure and the substrate;
[0010] The organic layer is located on the side of the first insulating layer away from the substrate;
[0011] A first via is provided in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor, and the first isolation structure is disposed in the first via.
[0012] The second insulating layer is located on the side of the organic layer away from the substrate;
[0013] The flexible layer is located on the side of the second insulating layer away from the substrate;
[0014] The sealing layer is located on the side of the flexible layer away from the substrate;
[0015] The cover plate is located on the side of the sealing layer away from the substrate.
[0016] In one possible implementation,
[0017] The first isolation structure and the second insulating layer are an integrated structure made of the same material.
[0018] In one possible implementation,
[0019] The first insulating layer has a second via, and the second insulating layer has a third via.
[0020] The second via, the third via, and the first via have overlapping orthographic projection positions on the substrate; the first isolation structure is disposed in the second via, the third via, and the first via.
[0021] In one possible implementation,
[0022] The second via and the first via are projected at the same position on the substrate, and the area of the third via projected on the substrate is larger than the area of the first via projected on the substrate.
[0023] In one possible implementation,
[0024] The array substrate further includes a second isolation structure and a first gap;
[0025] Along the plane of the array substrate, there exists a first gap between the flexible layer and the first insulating layer and the second insulating layer;
[0026] The second isolation structure is disposed on the first interval.
[0027] In one possible implementation,
[0028] The array substrate further includes a second spacer;
[0029] In the direction perpendicular to the array substrate, there exists a second gap between the flexible layer and the second insulating layer;
[0030] The second isolation structure is disposed within the first interval and the second interval.
[0031] In one possible implementation,
[0032] The substrate is a glass substrate; the cover plate is a glass cover plate.
[0033] A second aspect of this application provides a display substrate, the display substrate including any of the array substrates described in the first aspect of this application.
[0034] A third aspect of this application provides a display panel, the display panel including the display substrate described in the second aspect of this application.
[0035] A fourth aspect of this application provides a display device, the display device including the display panel described in the third aspect of this application.
[0036] This invention provides an array substrate, display substrate, display panel, and display device. A first via is provided in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor, and a first isolation structure is provided in the first via. Therefore, during the propagation of water vapor in the array substrate, the first isolation structure in the first via can prevent water vapor from continuing to move along the organic layer towards the transistor, thereby reducing the impact of water vapor on the functional characteristics of the transistors in the array substrate. Of course, any product implementing this invention does not necessarily need to achieve all the advantages described above simultaneously. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.
[0038] Figure 1 This is a schematic diagram of the first type of hierarchical structure at the edge of an array substrate in related technologies.
[0039] Figure 2 This is a schematic diagram of a second type of hierarchical structure at the edge of an array substrate in related technologies.
[0040] Figure 3 This is a schematic diagram of the third layered structure at the edge of an array substrate in related technologies.
[0041] Figure 4 This is a schematic diagram of the first type of layered structure at the edge of the array substrate provided in an embodiment of this application;
[0042] Figure 5 This is a schematic diagram of a second layered structure at the edge of an array substrate provided in an embodiment of this application;
[0043] Figure 6 This is a schematic diagram of a third layered structure at the edge of an array substrate provided in an embodiment of this application;
[0044] Figure 7 This is a schematic diagram of the fourth layer structure at the edge of the array substrate provided in an embodiment of this application;
[0045] Figure 8 This is a schematic diagram of the fifth layer structure at the edge of the array substrate provided in an embodiment of this application;
[0046] Figure 9 This is a schematic diagram of the sixth layer structure of the edge of the array substrate provided in the embodiments of this application. Detailed Implementation
[0047] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art based on this application are within the protection scope of the present utility model.
[0048] Reliability testing of array substrates typically involves testing their sealing performance, transistor functional characteristics, solder joint bonding strength, and normal display duration under harsh environments such as high temperature and humidity or high temperature and high pressure. For example, a new screen product is operated in a harsh environment with high temperature and humidity, and the duration of normal display is recorded. The longer the normal display duration, the better the screen's evaluation score. In related technologies, the normal display duration of a screen under harsh environments with high temperature and humidity should be greater than or equal to 1000 hours. In actual testing, it was found that under different reliability conditions, even after 1000 hours of screen operation, the TFTs (Threshold Voltages) within the array substrate exhibit different Vth (Threshold Voltage) shifts. Under HTO conditions, such as a temperature of 60°C and indoor humidity, the TFT threshold voltage shows a positive shift above 0V. Under THO conditions, such as a high temperature and high humidity environment of 60°C and 90% humidity, the TFT threshold voltage shows a negative shift of -3V to -1V.
[0049] Investigation revealed that the main cause of the above phenomenon was that water vapor in the air could enter the array substrate and reach the active layer of the transistors, thus affecting the functional characteristics of the transistors. Figure 1 The diagram shows a layered structure of an array substrate in the related art. The array substrate includes a glass substrate 101, a GI layer (gate insulating layer) 102, a wiring structure 103, a transistor 104, a first insulating layer 105, an organic layer 106, a second insulating layer 107, a flexible layer 108, a sealing layer 109, and a glass cover plate 110. Water vapor (H2O) in the air enters the internal structure of the array substrate through the first insulating layer, organic layer, second insulating layer, flexible layer, and GI layer, and propagates from the edges towards the interior of the array substrate at these layers. When the water vapor propagates to the active layer 1041 of the transistor, it combines with the oxide semiconductor of the active layer, thereby affecting the functional characteristics of the transistor.
[0050] To address this issue, some functional layers can be removed from the edges of the array substrate, thereby reducing the amount of water vapor absorbed by each functional layer in the array substrate. For example... Figure 2As shown in the dashed box, the organic and GI layers are removed from the edge region of the array substrate. This allows water vapor (H2O) to enter the array substrate only through the flexible layer at the edge, reducing the pathways for water vapor to enter. After passing through the flexible layer to the first and second insulating layers, the water vapor disperses onto the GI and organic layers as it propagates into the array substrate, reducing its likelihood of reaching the active layers. This, in turn, reduces the probability of water vapor combining with the metal oxides of the active layers, thus improving the impact of water vapor on the functional characteristics of the transistors in the array substrate.
[0051] However, the above structure is only applicable to BCE (Back Channel Etch) array substrates. When applied to TGBC (Top Gate Bottom Contact) or TGSA (Top Gate Self-Align) structures, its effectiveness in preventing water vapor from reaching the active layer is significantly reduced. Figure 3 As shown, Figure 3 This is a schematic diagram of the edge structure of the array substrate when the above method is applied to the TGBC structure. In the TGBC structure, except for the lower part of the Gate layer (gate metal layer) 301, the GI layer is removed. This reduces the amount of water vapor that can be dispersed by the GI layer, and increases the probability that water vapor will reach the active layer through the first insulating layer and / or the second insulating layer, thereby affecting the functional characteristics of the transistor.
[0052] To address at least one of the aforementioned problems, a first aspect of this application provides a schematic diagram of the edge structure of an array substrate, as shown below. Figure 4 As shown, the array substrate includes a substrate 401, a transistor 104, a first isolation structure 402, a wiring structure 103, a first insulating layer 105, an organic layer 106, a second insulating layer 107, a flexible layer 108, a sealing layer 109, and a cover plate 403.
[0053] The transistor and the wiring structure are disposed on the substrate.
[0054] The transistor includes a source / drain metal layer 4041, an inorganic buffer layer 4042, an active layer 1041, a gate insulating layer 102, and a gate metal layer 301. The source / drain metal layer is located on the first side of the glass substrate; the inorganic buffer layer is located on the side of the source / drain metal layer away from the glass substrate; the active layer is located on the side of the inorganic buffer layer away from the glass substrate; the gate insulating layer is located on the side of the active layer away from the glass substrate; and the gate metal layer is located on the side of the gate insulating layer away from the glass substrate. In the wiring structure, the gate metal layer penetrates the gate insulating layer and the inorganic buffer layer to make contact with the source / drain metal layer.
[0055] In this context, the active layer is often made of metal oxide semiconductor materials. Therefore, when water vapor reaches the active layer, it combines with the metal oxide, altering its functional properties. For example, this metal oxide semiconductor material can be an n-type semiconductor such as zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), and tin oxide (SnO2), as well as a p-type semiconductor such as tin suboxide (SnO) and cuprous suboxide (Cu2O).
[0056] The first insulating layer is located on the side of the transistor and the wiring structure away from the substrate, and is in contact with the wiring structure and the substrate.
[0057] like Figure 4 As shown, the first insulating layer is located above the transistors and wiring structures and wraps around each transistor and wiring structure, thereby dispersing water vapor in the organic film and preventing water vapor from propagating directly from the organic layer to the active layer of the transistor.
[0058] The organic layer is located on the side of the first insulating layer away from the substrate;
[0059] A first via is provided in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor, and the first isolation structure is disposed in the first via.
[0060] The second insulating layer is located on the side of the organic layer away from the substrate.
[0061] An organic layer is located between the first and second insulating layers and can disperse water vapor propagating in the second insulating layer towards the active layer. There can be one or more first vias, disposed in the organic layer between two trace structures near the edge of the array substrate and / or between a trace structure near the edge of the array substrate and a transistor. In the embodiments of this application, the first via can be circular, square, rectangular, etc., and there is no limitation on its shape. In one example, a square first via is obtained by hollowing out the organic layer between two trace structures and / or between a trace structure and a transistor.
[0062] In this design, the projection position of the first via on the substrate does not overlap with the projection positions of the trace structure and the transistor on the substrate. The first isolation structure is a waterproof structure used to block the propagation of water vapor. In one example, the first isolation structure is a waterproof layer composed of a waterproof material. For example, after obtaining the first via by hollowing out the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure near the edge of the array substrate and the transistor, a waterproof material is deposited on the surface of the first via to form a waterproof layer, which is the first isolation structure. In another example, during the vapor deposition process of preparing the array substrate, the relevant waterproof material is directly vapor deposited onto the first via to fill it, thus obtaining the first isolation structure.
[0063] like Figure 4 As shown, the left side represents the direction near the edge of the array substrate, and the right side represents the direction near the internal structure of the array substrate. Water vapor in the air enters the array substrate through the flexible layer and propagates. One propagation path is from the flexible layer to the second insulating layer, then propagates from left to right and from top to bottom on the second insulating layer to the organic layer. On the organic layer, it also propagates from left to right and from top to bottom. When water vapor propagates from left to right on the organic layer, that is, from the edge of the array substrate to the interior of the array substrate, the first isolation structure blocks part of the water vapor's propagation when it reaches the first via, thereby reducing the probability of water vapor reaching the active layer of the transistor.
[0064] The more vias there are, the greater the probability of water vapor reaching the active layer of the transistor. Figure 4 In this design, first vias are provided in the organic layers between two trace structures near the edge of the array substrate and / or between a trace structure near the edge of the array substrate and a transistor. When water vapor propagates from left to right, the first isolation structures of the first and second vias intercept some of the water vapor, thereby reducing the probability of water vapor reaching the active layer of the transistor.
[0065] The flexible layer is located on the side of the second insulating layer away from the substrate;
[0066] The sealing layer is located on the side of the flexible layer away from the substrate;
[0067] The cover plate is located on the side of the sealing layer away from the substrate.
[0068] In this embodiment, the substrate and cover plate can be formed of rigid or flexible materials. For example, rigid materials include rigid glass and silicon wafers. Flexible materials include polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass. In one example, the substrate in this embodiment is a glass substrate, and the cover plate is a glass cover plate.
[0069] The first and second insulating layers can be made of the same or different materials. In one example, the materials of the first and second insulating layers include one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide. The flexible layer can be a PI film (polyimide film).
[0070] The array substrate using the embodiments of this application has a first via in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor, and a first isolation structure is disposed in the first via. When water vapor propagates from the edge of the array substrate inward, the first isolation structure in the first via can block part of the movement of water vapor, thereby reducing the probability of water vapor reaching the active layer of the transistor and reducing the impact of water vapor on the functional characteristics of the transistor in the array substrate.
[0071] In one possible implementation, the first isolation structure and the second insulating layer are an integrated structure made of the same material.
[0072] In practical applications, the first isolation structure and the second insulating layer can be deposited using the same material during the evaporation process of fabricating the array substrate, forming an integrated structure. In another example, the first isolation structure and the second insulating layer are two structures made of different materials. For example, ITO (indium tin oxide) or IZO (indium zinc oxide) can be used as the material for the first isolation structure, and silicon nitride (SiN) can be used as the material for the second insulating layer.
[0073] The array substrate using the embodiments of this application has an integrated structure in which the first isolation structure and the second insulating layer are made of the same material. This makes it easier to manufacture the array substrate. For example, the integrated structure of the first isolation structure and the second insulating layer can be obtained by directly vapor depositing a single material, thereby reducing the manufacturing difficulty of the array substrate and improving its manufacturing efficiency.
[0074] In one possible implementation, the first isolation structure can penetrate not only the organic layer but also the first and second insulating layers. In this embodiment, the first insulating layer has a second via, and the second insulating layer has a third via.
[0075] The second via, the third via, and the first via have overlapping orthographic projection positions on the substrate; the first isolation structure is disposed in the second via, the third via, and the first via.
[0076] Since the first isolation structure needs to be set in the first, second, and third vias, the orthographic projections of the first, second, and third vias on the substrate need to overlap to ensure that the first isolation structure can reach the second via through the first and third vias. For example, if the first, second, and third vias are all circular vias, and their projections on the substrate are concentric circles, then the first isolation structure can pass through the first, second, and third vias relatively easily.
[0077] like Figure 5 As shown, the first isolation structure penetrates the first insulating layer, the organic layer, and the second insulating layer. In the water vapor propagation path, the first isolation structure can not only block water vapor moving from the edge of the substrate to the interior of the substrate on the organic layer, but also block water vapor moving from the edge of the substrate to the interior of the substrate on the first and second insulating layers.
[0078] In practical applications, water vapor also has another propagation path: propagation through the first insulating layer, such as... Figure 5 As shown, water vapor enters the array substrate through the flexible layer and diffuses onto the first insulating layer. On the first insulating layer, the water vapor can propagate from left to right and from bottom to top to reach the active layer of the transistor, thereby combining with the metal oxide of the active layer and affecting the functional characteristics of the transistor. When the first isolation structure penetrates the first insulating layer, as water vapor propagates from the edge region of the first insulating layer into the array substrate, the first isolation structure can prevent that portion of the water vapor from continuing to propagate into the array substrate.
[0079] In the array substrate of this application embodiment, a second via is provided on the first insulating layer and a third via is provided on the second insulating layer. This allows the first isolation structure to penetrate the first insulating layer, the organic layer and the second insulating layer, thereby isolating the propagation path of water vapor from the edge of the array substrate to the interior of the array substrate on the first insulating layer, the organic layer and the second insulating layer. This reduces the probability of water vapor reaching the active layer of the transistor and reduces the impact of water vapor on the functional characteristics of the transistors in the array substrate.
[0080] In this embodiment, the projected positions of the first via, second via, and third via on the substrate only need to not overlap with the projections of the wiring structure and transistor on the substrate; no other restrictions are placed on their size. The projected areas of the first via, second via, and third via on the substrate can be the same or different. In one possible implementation, the second via and the first via are projected at the same position on the substrate, and the area of the projected position of the third via on the substrate is larger than the area of the projected position of the first via on the substrate.
[0081] like Figure 5As shown, the projected positions and projected areas of the first and second vias on the substrate are the same, while the area of the projected position of the third via on the substrate is larger than the area of the projected position of the first via on the substrate. In practical applications, to facilitate the fabrication of the array substrate, the projected areas of the first, second, and third vias on the substrate can be set to be the same, such as... Figure 6 As shown. Of course, it can also be as follows: Figure 7 As shown, the areas of the projection positions of the first via, the second via, and the third via on the substrate are all different.
[0082] In the array substrate of this application embodiment, a second via is provided on the first insulating layer and a third via is provided on the second insulating layer. This allows the first isolation structure to penetrate the first insulating layer, the organic layer and the second insulating layer, thereby isolating the propagation path of water vapor from the edge of the array substrate to the interior of the array substrate on the first insulating layer, the organic layer and the second insulating layer. This reduces the probability of water vapor reaching the active layer of the transistor, and thus reduces the impact of water vapor on the functional characteristics of the transistors in the array substrate.
[0083] In one possible implementation, the array substrate further includes a second isolation structure and a first spacing;
[0084] Along the plane of the array substrate, there exists a first gap between the flexible layer and the first insulating layer and the second insulating layer;
[0085] The second isolation structure is disposed on the first interval.
[0086] In practical applications, since water vapor can enter the array substrate through the flexible layer, a second isolation structure can be provided between the flexible layer and the first and second insulating layers to enclose the first and second insulating layers, thereby reducing the amount of water vapor entering the array substrate. For example... Figure 8 As shown, a first gap exists in the contact portion between the flexible layer at the edge of the array substrate and the first insulating layer and the second insulating layer, and the second isolation structure 801 is disposed within the first gap.
[0087] When water vapor enters the array substrate through the flexible layer, the presence of the second isolation structure reduces the amount of water vapor that can diffuse to the first and second insulating layers. When the water vapor is transferred to the first isolation structure, the amount of water vapor that can pass through the first isolation structure is reduced again, thereby further reducing the probability of water vapor reaching the active layer.
[0088] In the array substrate of this application embodiment, there is a first gap between the flexible layer and the first insulating layer and the second insulating layer along the plane direction of the array substrate; the second isolation structure is disposed in the first gap, which can block some water vapor from entering the first insulating layer and the second insulating layer through the flexible layer, thereby reducing the probability of water vapor reaching the active layer and reducing the impact of water vapor on the functional characteristics of the transistors in the array substrate.
[0089] In practical applications, in order to further block the transmission of water vapor, a second gap can be provided along the vertical direction of the array substrate, and the second gap exists between the flexible layer and the second insulating layer; the second isolation structure is disposed within the first gap and the second gap.
[0090] The length of the second interval can be determined according to actual needs. It can be set only at the edge region of the array substrate, or it can be set along the entire length of the array substrate in the planar direction. For example... Figure 9 As shown, in the edge region of the array substrate, the second isolation structure is in contact with the flexible layer, which can block some water vapor from being transferred through the flexible layer to the first insulating layer or the second insulating layer.
[0091] The array substrate using the embodiments of this application has a second gap disposed along the vertical direction of the array substrate, and there is a second gap between the flexible layer and the second insulating layer; the second isolation structure is disposed within the first gap and the second gap, thereby reducing the probability of water vapor reaching the first insulating layer or the second insulating layer through the second gap, and further reducing the probability of water vapor reaching the active layer, thereby reducing the impact of water vapor on the functional characteristics of the transistors in the array substrate.
[0092] In another aspect of this application, a display substrate is also provided, which includes the array substrate in any of the above embodiments. Furthermore, the display substrate also includes structures such as a light-emitting layer and a pixel layer.
[0093] The display substrate using the embodiments of this application can have a first via provided in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor, with a first isolation structure disposed in the first via. When water vapor propagates from the edge of the array substrate inward, the first isolation structure in the first via can block part of the water vapor movement, thereby reducing the probability of water vapor reaching the active layer of the transistor, reducing the impact of water vapor on the functional characteristics of the transistor in the array substrate, and thus avoiding the display effect of the display substrate being affected by water vapor.
[0094] In another aspect of this application, a display panel is also provided, which includes the display substrate in any of the above embodiments. In practical applications, the display panel may also include structures such as a color filter substrate and a liquid crystal layer.
[0095] The display panel using the embodiments of this application has a first via in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor in the layer structure of the array substrate. A first isolation structure is disposed in the first via. When water vapor propagates from the edge of the array substrate inward, the first isolation structure in the first via can block part of the water vapor movement, thereby reducing the probability of water vapor reaching the active layer of the transistor. This reduces the impact of water vapor combining with the metal oxide of the active layer on the functional characteristics of the transistor in the array substrate, thereby avoiding the display effect of the display panel being affected by water vapor, and enabling the display panel to better adapt to the usage environment with high humidity.
[0096] In another aspect of the embodiments of this application, the embodiments of this application also provide a display device, which includes the display panel in any of the above embodiments. The display device may be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.
[0097] The display device using the embodiments of this application has a first via in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor in the display panel of the display device, and a first isolation structure is disposed in the first via. When water vapor propagates from the edge of the array substrate inward, the first isolation structure in the first via can block part of the water vapor movement, thereby reducing the probability of water vapor reaching the active layer of the transistor, reducing the impact of water vapor combining with the metal oxide of the active layer on the functional characteristics of the transistor in the array substrate, and thus avoiding the display effect of the display panel being affected by water vapor, so that the display panel can better adapt to the usage environment with high humidity.
[0098] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.
Claims
1. An array substrate, characterized in that, The array substrate includes a substrate, transistors, a first isolation structure, a wiring structure, a first insulating layer, an organic layer, a second insulating layer, a flexible layer, a sealing layer, and a cover plate. The transistor and the wiring structure are disposed on the substrate; The first insulating layer is located on the side of the transistor and the wiring structure away from the substrate, and is in contact with the wiring structure and the substrate; The organic layer is located on the side of the first insulating layer away from the substrate; A first via is provided in the organic layer between two trace structures near the edge of the array substrate and / or between the trace structure and the transistor, and the first isolation structure is disposed in the first via. The second insulating layer is located on the side of the organic layer away from the substrate; The flexible layer is located on the side of the second insulating layer away from the substrate; The sealing layer is located on the side of the flexible layer away from the substrate; The cover plate is located on the side of the sealing layer away from the substrate.
2. The array substrate according to claim 1, characterized in that, The first isolation structure and the second insulating layer are an integrated structure made of the same material.
3. The array substrate according to claim 1, characterized in that, The first insulating layer has a second via, and the second insulating layer has a third via. The second via, the third via, and the first via have overlapping orthographic projection positions on the substrate; the first isolation structure is disposed in the second via, the third via, and the first via.
4. The array substrate according to claim 3, characterized in that, The second via and the first via are projected at the same position on the substrate, and the area of the third via projected on the substrate is larger than the area of the first via projected on the substrate.
5. The array substrate according to claim 3, characterized in that, The array substrate further includes a second isolation structure and a first gap; Along the plane of the array substrate, there exists a first gap between the flexible layer and the first insulating layer and the second insulating layer; The second isolation structure is disposed within the first interval.
6. The array substrate according to claim 5, characterized in that, The array substrate further includes a second spacer; In the direction perpendicular to the array substrate, there exists a second gap between the flexible layer and the second insulating layer; The second isolation structure is disposed within the first interval and the second interval.
7. The array substrate according to claim 1, characterized in that, The substrate is a glass substrate; the cover plate is a glass cover plate.
8. A display substrate, characterized in that, The display substrate includes the array substrate according to any one of claims 1-7.
9. A display panel, characterized in that, The display panel includes the display substrate as described in claim 8.
10. A display device, characterized in that, The display device includes the display panel as described in claim 9.