Display panel and display device

Abstract

The utility model provides a display panel and a display device.The display panel comprises a substrate, the substrate is provided with a display area and a bending area located on one side of the display area, the display area comprises a plurality of conducting layers arranged on one side of the substrate in a stacked mode, at least one of the conducting layers is provided with a plurality of signal lines, and the signal lines are arranged on the bending area. The bending area comprises a plurality of connecting lines, one connecting line is connected with one signal line, the connecting lines comprise the first connecting line and the second connecting line which are arranged in a stacked mode in the direction away from the substrate, the first connecting line and one conducting layer in the multiple conducting layers are arranged on the same layer, and the second connecting line and the other conducting layer are arranged on the same layer. And the second connecting line and another conducting layer in the multiple conducting layers are arranged on the same layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology. More specifically, it relates to a display panel and a display device. Background Technology

[0002] With the continuous advancement of display technology, consumers are increasingly demanding higher standards for the appearance and performance of electronic display products. In particular, in the field of consumer electronics products such as smartphones, tablets, and smart TVs, the pursuit of narrower bezel designs has become a major trend.

[0003] In the process of achieving a narrower bezel design, how to effectively compress the bottom bezel space is a particularly critical issue. Traditional bezel designs often require reserving enough space within the bottom bezel to accommodate various electronic components and connecting wires, which limits further reduction in bezel size. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel and display device to achieve a narrow bezel in the display panel.

[0005] To achieve the above objectives, the present disclosure adopts the following technical solution:

[0006] The first aspect of this disclosure provides a display panel, the display panel including a substrate having a display area and a bent area located on one side of the display area;

[0007] The display area includes multiple conductive layers stacked on one side of the substrate. At least one of the multiple conductive layers is provided with multiple signal lines. The bending area includes multiple connecting lines, one connecting line being connected to one signal line. The connecting lines include a first connecting line and a second connecting line stacked along the direction away from the substrate. The first connecting line is disposed in the same layer as one of the multiple conductive layers, and the second connecting line is disposed in the same layer as another of the multiple conductive layers.

[0008] Optionally, the multilayer conductive layer includes at least a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer stacked sequentially along a direction away from the substrate, wherein the first connecting line is disposed in the same layer as the second source / drain metal layer, and the second connecting line is disposed in the same layer as the third source / drain metal layer.

[0009] Optionally, the surface of the first connecting line away from the substrate is in contact with the surface of the second connecting line near the substrate.

[0010] Optionally, the orthographic projection of the first connecting line on the substrate overlaps the orthographic projection of the second connecting line on the substrate.

[0011] Optionally, the edge of the orthographic projection of the first connecting line on the substrate does not overlap with the edge of the orthographic projection of the second connecting line on the substrate.

[0012] Optionally, the second connecting line includes at least two sub-connecting lines spaced apart along the length of the connecting line.

[0013] Optionally, the display area further includes a planarization layer disposed between the second source / drain metal layer and the third source / drain metal layer, and the bending area further includes a first organic layer disposed between the first connecting line and the second connecting line. The first organic layer and the planarization layer are disposed in the same layer, and the first connecting line and the second connecting line are electrically connected through vias in the first organic layer.

[0014] Optionally, the display area further includes a planarization layer disposed between the second source / drain metal layer and the third source / drain metal layer, and the bending area further includes a first organic layer disposed between the first connecting line and the second connecting line. The first organic layer and the planarization layer are disposed on the same layer. The connecting line further includes a third connecting line. The first connecting line and the second connecting line extend along a first direction and are arrayed along a second direction. The third connecting line extends along the second direction and is arrayed along the first direction. The third connecting line and the second connecting line are disposed on the same layer and intersect to form a mesh structure. The first connecting line is connected to the signal line, and there is no connection between the second connecting line and the third connecting line and the first connecting line.

[0015] Optionally, the bending area further includes an inorganic layer and a second organic layer disposed between the substrate and the connecting line and stacked sequentially in a direction away from the substrate. The inorganic layer has a groove on its surface away from the substrate. The second organic layer covers the inorganic layer and fills the groove. The bottom of the groove is located on the substrate.

[0016] Optionally, the display panel further includes a first fan-out area disposed between the display area and the bending area. The first fan-out area includes multiple fan-out lines. A first end of each fan-out line is connected to a signal line, and a second end of each fan-out line is connected to a connecting line. The fan-out lines are disposed in the same layer as at least one of the multilayer conductive layers, and the fan-out lines and the connecting lines are located in different conductive layers.

[0017] Optionally, the multilayer conductive layer includes at least a gate layer disposed along a direction away from the substrate, and the fan-out line is disposed in the same layer as the gate layer.

[0018] Optionally, the display panel further includes a second fan-out area, an electrostatic protection area, a circuit test area, a third fan-out area, a chip mounting area, an internal pin bonding area, and a flexible circuit board, which are disposed on the side of the bending area away from the display area and arranged sequentially along the direction away from the display area.

[0019] Optionally, the signal line includes a data trace, which extends along a first direction and is arranged in an array along a second direction.

[0020] A second aspect of this disclosure provides a display device including a display panel as described above.

[0021] The beneficial effects of this disclosure are as follows:

[0022] The display panel of this disclosure embodiment includes a first connecting line and a second connecting line stacked along the direction away from the substrate in the bending area. The first connecting line is disposed in the same layer as one of the conductive layers in the multilayer conductive layers of the display area, and the second connecting line is disposed in the same layer as the other conductive layer in the multilayer conductive layers. That is, the connecting lines in the bending area adopt a stacked double-layer routing design. The double-layer routing can significantly improve the strength of the connecting lines. Therefore, the bending area can use a smaller bending radius, and the size of the bending area in the direction away from the display area is reduced, thereby reducing the bezel size. Attached Figure Description

[0023] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the structure of the lower bezel of a display panel in related technologies;

[0025] Figure 2 A plan view of the display panel provided in an embodiment of this disclosure;

[0026] Figure 3 for Figure 2 A structural diagram of the central QQ area;

[0027] Figure 4 for Figure 2 A schematic diagram of the film structure of the central display area AA along the cross-sectional line C-C'.

[0028] Figure 5 A schematic diagram of a membrane structure along the cross-sectional line C-C' of the bending region BB provided in an embodiment of this disclosure;

[0029] Figure 6 A schematic diagram illustrating the principle of reducing the width of the wiring in the bending area for double-layer cabling design;

[0030] Figure 7 A schematic diagram of another membrane structure along the cross-sectional line C-C' of the bending region BB provided in this embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of another membrane structure along the cross-sectional line C-C' of the bending region BB provided in this embodiment of the present disclosure;

[0032] Figure 9 A schematic diagram of another membrane structure along the cross-sectional line C-C' of the bending region BB provided in this embodiment of the present disclosure;

[0033] Figure 10 This is a schematic diagram of another membrane structure along the cross-sectional line C-C' of the bending region BB provided in an embodiment of this disclosure. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0036] In related technologies, a display panel includes a display area, a bending area, and a bonding area. The display panel also includes a light-emitting side and a backlight side. The bending area is mainly used to lead the signal lines from the light-emitting side of the display area to the bonding area on the backlight side for electrical connection with the driver chip on the backlight side. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the lower bezel of a display panel in related technologies. Figure 1 In the middle, BB represents the bend region, and R represents the radius of curvature of the bend region BB. Figure 1 The direction of the middle arrow indicates the light-emitting side of the display panel. In related technologies, the bending area BB typically uses a single-layer metal trace design. In order to reduce the risk of breakage of the metal traces within the bending area BB, the bending area BB usually needs to maintain a certain radius of curvature. Therefore, the size of the bottom bezel is limited by the bending area BB and cannot be further reduced.

[0037] To achieve a narrow bottom bezel design, this disclosure improves the design of the metal traces within the bending area, thereby compressing the bottom bezel in the bending area. Specifically, this disclosure provides a display panel and a display device; please refer to... Figures 2 to 5 , Figure 2 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of this disclosure. Figure 3 for Figure 2 A structural diagram of the central QQ area. Figure 4 for Figure 2 A schematic diagram of the film structure in the central display area AA along the cross-sectional line C-C'. Figure 5 This is a schematic diagram of the membrane structure along the cross-sectional line C-C' in the bending region BB, as shown below. Figures 2 to 5 As shown, the display panel includes a substrate 10, which has a display area AA and a bending area BB located on one side of the display area AA. The display area AA includes multiple conductive layers 11 stacked on one side of the substrate 10. At least one of the multiple conductive layers 11 is provided with multiple signal lines 12. The bending area BB includes multiple connecting lines 21, one connecting line 21 being connected to one signal line 12. The connecting line 21 includes a first connecting line 210 and a second connecting line 211 stacked in a direction away from the substrate 10. The first connecting line 210 is disposed in the same layer as one of the conductive layers 11, and the second connecting line 211 is disposed in the same layer as another conductive layer of the multiple conductive layers.

[0038] Optional, such as Figures 2 to 3 As shown, the display panel includes a display area AA and a border area surrounding the display area AA. The border area includes a top border area and a bottom border area located on both sides of the display area AA in the first direction Y, and a left border area and a right border area located on both sides of the display area AA in the second direction X. The curved area BB is located on one side of the display area AA, which can be understood as the curved area BB being located within one of the top border area, bottom border area, left border area, and right border area. In some implementations, such as... Figures 2 to 3 As shown, the bending area BB is located on one side of the display area AA along the second direction Y. Optionally, the bending area BB is adjacent to the lower edge of the display area AA, that is, the bending area BB is located below the display area AA along the second direction Y, that is, within the lower border area.

[0039] Optionally, the signal line 12 includes a data trace 121, which extends along the first direction Y and is arranged in an array along the second direction X within the display area AA. The data trace 121 is used to provide data signals to each column of pixels. Furthermore, the signal line 12 may also include a drive line 122, which is used to provide control signals to the gate driver array (GOA) in the display panel. The drive line 122 includes, for example, a clock signal line CLK and a frame start signal line STV. Since the GOA units in the display panel are usually located within the left and right bezel areas of the display area AA, the drive lines are also usually located within the left and right bezel areas. Figure 2 Only the drive line 122 located within the left border is shown.

[0040] In order to realize the display function, the display panel needs to form a driving circuit layer, pixel definition layer, isolation pillar layer, light-emitting device layer and encapsulation layer in sequence on the substrate 10. Each film layer can be formed with different materials according to its function, such as metal materials, inorganic materials or organic materials.

[0041] For example, the substrate 10 can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate (PEN), or thermoplastic polyester (PET). The display panel may also include a barrier layer and a buffer layer located between the substrate 10 and the driving circuit layer. The barrier layer and buffer layer can be formed entirely on the substrate 10. For example, the barrier layer can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, which helps to prevent water and oxygen from entering the OLED from the bottom. The buffer layer can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, which improves the quality of subsequent material deposition. The barrier layer and buffer layer can be a single-layer structure or a multi-layer structure.

[0042] The driving circuit layer, also known as the thin-film transistor (TFT) layer, may include an active layer formed by a patterning process, a gate insulating layer (GI) formed on the active layer by deposition or other methods, the gate of the TFT formed on the gate insulating layer by a patterning process, a dielectric layer (ILD) formed on the gate by deposition or other methods, a source / drain metal layer formed on the dielectric layer, and a planarization layer (PLN) covering the source / drain metal layer and the exposed dielectric layer. The source / drain metal layer forms the source and drain of the TFT. For example, the source is electrically connected to the active layer through a via in the dielectric layer. The active layer may be made of polysilicon or metal oxides, the gate insulating layer may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, the dielectric layer may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, the gate material may include metals or alloys such as aluminum, titanium, or cobalt, and the planarization layer may be an organic material.

[0043] In this embodiment, the multilayer conductive layer 11 mainly refers to the conductive layer in the driving circuit layer, such as the gate layer, source / drain metal layer, etc. Insulating layers, such as gate insulating layers, dielectric layers, planarization layers, etc., can be disposed between the multilayer conductive layers 11. The insulating layers serve to electrically isolate adjacent conductive layers. The pixel driving circuit can be fabricated through the multilayer conductive layers 11 and the insulating layers between them.

[0044] In a specific example, such as Figure 4 As shown, the thin-film transistor in the driving circuit layer is a low-temperature polycrystalline oxide (LTPO) thin-film transistor, which adopts a three-layer source-drain metal layer structure.

[0045] The substrate 10 may include a first substrate PI1, a barrier layer Barrier1 stacked on the first substrate PI1, a second substrate PI2, a barrier layer Barrier2-1 stacked on the second substrate PI2, a metal light-shielding layer BSM disposed on the barrier layer Barrier2-1, a barrier layer Barrier2-2 covering the metal light-shielding layer BSM and the barrier layer Barrier2-1, and buffer layers Buffer1 and Buffer2 stacked on the barrier layer Barrier2-1.

[0046] The driving circuit layer may include the following components stacked sequentially along a direction away from the substrate 10:

[0047] (1) Active layer;

[0048] (2) A first gate insulating layer GI1 covering the active layer;

[0049] (3) A first gate Gate1 is formed on the first gate insulating layer GI1;

[0050] (4) Cover the first gate Gate1 with the second gate insulating layer GI2;

[0051] (5) A second gate Gate2 is formed on the second gate insulating layer GI2;

[0052] (6) The first interlayer dielectric layer ILD1 covers the second gate Gate2;

[0053] (7) A buffer layer Buffer2 is formed on the first interlayer dielectric layer ILD1;

[0054] (8) A metal oxide semiconductor layer IGZO is formed on the buffer layer Buffer2;

[0055] (9) The third gate insulating layer GI3 covers the buffer layer Buffer2 and the metal oxide semiconductor layer IGZO;

[0056] (10) A third gate Gate3 formed on the third gate insulating layer GI3;

[0057] (11) A second interlayer dielectric layer ILD2 covering the third gate Gate3 and the third gate insulating layer GI3. For example, the second interlayer dielectric layer ILD2 can be a double-layer structure, including ILD2-1 and ILD2-2.

[0058] (12) A first source / drain metal layer SD1 is formed on the second interlayer dielectric layer ILD2;

[0059] (13) A first passivation layer PVX1 covering the first source / drain metal layer SD1 and the second interlayer dielectric layer ILD2;

[0060] (14) A first planarization layer PLN1 covering the first passivation layer PVX1;

[0061] (15) A second source / drain metal layer SD2 is formed on the first planarization layer PLN1;

[0062] (16) A second planarization layer PLN2 covering the second source / drain metal layer SD2;

[0063] (17) A third source / drain metal layer SD3 is formed on the second planarization layer PLN2;

[0064] (18) The third planarization layer PLN3 covers the third source / drain metal layer SD3.

[0065] The pixel defining layer (PDL) is disposed on the third planarization layer (PLN3) and includes multiple pixel openings. The isolation pillar layer (PS) includes multiple isolation pillars located between adjacent pixel openings and on the side of the pixel defining layer (PDL) away from the substrate 10.

[0066] The light-emitting device layer is at least partially disposed within the pixel opening. The light-emitting device layer includes a first electrode layer, a light-emitting material layer, and a second electrode layer sequentially stacked along a direction away from the substrate. The first electrode layer is, for example, an anode layer, and the second electrode layer is, for example, a cathode. The first electrode layer, the anode, includes multiple anodes disposed within the pixel opening and can be electrically connected to the drain through vias formed in the planarization layer. The cathode is formed across the entire surface of the display panel, covering the light-emitting material layer, the pixel delimiting layer (PDL), and the isolation pillar layer (PS).

[0067] Optionally, the multilayer conductive layer 11 includes at least a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3 stacked sequentially along a direction away from the substrate 10. The first connecting line 210 is disposed in the same layer as the second source / drain metal layer SD2, and the second connecting line 211 is disposed in the same layer as the third source / drain metal layer SD3.

[0068] exist Figure 4 In the illustrated embodiment, the multilayer conductive layer 11 includes, in addition to the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3, a first gate Gate1, a second gate Gate2, and a third gate Gate3. It is understood that the driving circuit layer of the display panel in this embodiment is not limited to... Figure 4 The LTPO thin-film transistor with three source-drain metal layers shown can also be applied to other types of thin-film transistors, such as LTPS. In addition, the number of source-drain metal layers can also be two. In this case, the multilayer conductive layer 11 includes at least a first source-drain metal layer SD1 and a second source-drain metal layer SD2. The first connecting line 210 can be disposed in the same layer as the first source-drain metal layer SD1, and the second connecting line 211 can be disposed in the same layer as the second source-drain metal layer SD2.

[0069] Compared with related technologies, the display panel of this disclosure embodiment includes a first connecting line and a second connecting line stacked along the direction away from the substrate in the bending area. The first connecting line is disposed in the same layer as one of the conductive layers in the multilayer conductive layers of the display area, and the second connecting line is disposed in the same layer as the other conductive layer in the multilayer conductive layers. That is, the connecting lines in the bending area adopt a stacked double-layer routing design. The double-layer routing can significantly improve the strength of the connecting lines. Therefore, the bending area can use a smaller bending radius, and the size of the bending area in the direction away from the display area is reduced, thereby reducing the bezel size.

[0070] In one possible implementation, the surface of the first connecting line 210 away from the substrate 10 is in contact with the surface of the second connecting line 211 near the substrate 10.

[0071] The surface contact connection between the first connecting line 210 and the second connecting line 211 indicates that the first connecting line 210 and the second connecting line 211 are directly adjacent, and there is no intermediate film layer or medium between them. For example, as shown... Figure 5 As shown, the first connecting line 210 and the second connecting line 211 are in direct contact without any additional material layer or film separating them. This direct adjacent configuration ensures good contact and electrical connection between the first connecting line 210 and the second connecting line 211 without the need for interlayer vias. The connecting lines in this embodiment are metal traces, employing a double-layer metal trace design. This design improves the strength of the connecting lines, making them less prone to breakage when bent. Furthermore, the resistance of the metal traces decreases as the width increases. In a double-layer trace stack design, the resistances of the two metal traces are effectively in parallel. If the overall resistance of the connecting line remains constant, the width of the connecting line can be reduced. This design can reduce the width of multiple connecting lines in the second direction X.

[0072] Please refer to Figure 6 , Figure 6 A schematic diagram illustrating the principle of reducing the width of the wiring in the bend area for double-layer cabling design, as shown below. Figure 6 As shown, assuming the connection line adopts a single-layer routing design, the width of each connection line in the bending area BB is W0, and the spacing between two adjacent connection lines is also W0. The routing width of multiple connection lines in the X direction is denoted as W. In the double-layer routing design, if the resistance of the connection line remains unchanged, the width of each layer of metal routing can be reduced to half of the original, that is, reduced to (1 / 2)*W0. With the spacing between adjacent connection lines unchanged, the overall routing width can be reduced by 1 / 4, that is, the overall routing width can be reduced to (3 / 4)*W.

[0073] Optionally, the orthographic projection of the first connecting line 210 on the substrate 10 overlaps the orthographic projection of the second connecting line 211 on the substrate 10.

[0074] Wherein, the orthographic projection of the first connecting line 210 on the substrate 10 covers the orthographic projection of the second connecting line 211 on the substrate 10 in two cases:

[0075] (1) The orthographic projection of the first connecting line 210 on the substrate 10 completely overlaps with the orthographic projection of the second connecting line 211 on the substrate 10, that is, the first connecting line 210 and the second connecting line 211 are exactly the same size and their positions correspond completely. For example, please refer to Figure 5 , Figure 5 This is a schematic diagram showing the complete overlap of the orthographic projections of the first connecting line and the second connecting line.

[0076] (2) The orthographic projection of the first connecting line 210 on the substrate 10 is larger than the orthographic projection of the second connecting line 211 on the substrate 10, and the orthographic projection of the second connecting line 211 falls within the orthographic projection of the first connecting line 210, that is, the size of the second connecting line 211 is slightly smaller than the size of the first connecting line 210. In this case, it can also be understood that the edge of the orthographic projection of the first connecting line 210 on the substrate 10 does not overlap with the edge of the orthographic projection of the second connecting line 211 on the substrate 10. For example, please refer to... Figure 7 , Figure 7 This is a schematic diagram showing that the edges of the orthographic projections of the first connecting line and the second connecting line do not overlap.

[0077] In this embodiment of the present disclosure, a second connecting line 211 is directly superimposed on the first connecting line 210. On the one hand, the double-layer metal trace design can disperse the stress generated by a single metal layer when it is bent or subjected to force, thereby reducing stress concentration, improving the overall strength of the connecting line, and better resisting the stress generated by bending in the bending area BB, reducing the risk of cracks and breakage.

[0078] In one possible implementation, the second connecting line includes at least two sub-connecting lines spaced apart along the length of the connecting line.

[0079] For example, please refer to Figure 8 , Figure 8 This is a schematic diagram showing that the second connecting line includes two sub-connecting lines, where the length direction of the connecting line is... Figure 8 As shown in the first direction Y, the second connecting line 211 includes two sub-connecting lines 2110 in the first direction Y. It is understood that, depending on the length and width of the second connecting line 211, the second connecting line 211 may also include more sub-connecting lines 2110, and this embodiment of the present disclosure does not limit this.

[0080] In this embodiment, the second connecting line 211 is designed as a multi-segment structure with intervals. That is, the second connecting line 211 is no longer a continuous whole, but is composed of multiple independent segments (i.e., sub-connecting lines 2110). With this design, the second connecting line 211 can provide better protection for the first connecting line 210. Specifically, on the one hand, in continuous metal traces, bends or connection points often become areas of stress concentration. By designing the second connecting line 211 as a multi-segment structure, these potential stress concentration points can be eliminated, making the stress distribution more uniform. This stress dispersion mechanism not only helps to improve the overall structural strength of the connecting line 21, but also reduces the stress level borne by the first connecting line 210, thereby playing a role in physical protection. On the other hand, the multi-segment structure of the second connecting line 211 has higher overall flexibility, which helps the connecting line 21 to better adapt to various complex bending and connection requirements. At the same time, this design also enhances the stability of the overall structure, so that the first connecting line 210 can be better supported and protected when subjected to external forces.

[0081] In one possible implementation, the display area AA further includes a planarization layer disposed between the second source / drain metal layer SD2 and the third source / drain metal layer SD3, and the bending area BB further includes a first organic layer 212 disposed between the first connecting line 210 and the second connecting line 211. The first organic layer 212 is disposed in the same layer as the planarization layer, and the first connecting line 210 and the second connecting line 211 are electrically connected through vias in the first organic layer 212.

[0082] In this embodiment, the first connecting line 210 and the second connecting line 211 are not directly adjacent; a first organic layer 212 is disposed between them. Therefore, when the first connecting line 210 and the second connecting line 211 are electrically connected, it needs to be achieved through vias in the first organic layer 212. For example, please refer to... Figure 9 , Figure 9 The bending area shown is Figure 4 Taking the display panel shown as an example, the planarization layer between the second source / drain metal layer SD2 and the third source / drain metal layer SD3 is the second planarization layer PLN2, and the first organic layer 212 is set in the same layer as the planarization layer, that is, the first organic layer 212 and the second planarization layer PLN2 are set in the same layer.

[0083] In one possible implementation, such as Figure 10As shown, the display area further includes a planarization layer disposed between the second source / drain metal layer SD2 and the third source / drain metal layer SD3. The bending area BB further includes a first organic layer 212 disposed between the first connecting line 210 and the second connecting line 211. The first organic layer 212 and the planarization layer are disposed on the same layer. The connecting line 21 further includes a third connecting line 213. The first connecting line 210 and the second connecting line 211 extend along the first direction Y and are distributed in an array along the second direction X. The third connecting line 213 extends along the second direction X and is distributed in an array along the first direction Y. The third connecting line 213 and the second connecting line 211 are disposed on the same layer and the third connecting line 213 and the second connecting line 211 intersect to form a mesh structure. There is no connection between the second connecting line 211 and the third connecting line 213 and the first connecting line 210.

[0084] In this embodiment of the disclosure, the absence of connection between the second connecting line 211 and the third connecting line 213 and the first connecting line 210 means that the mesh structure formed by the second connecting line 211 and the third connecting line 213 has no direct or indirect electrical connection with the first connecting line 210. In this case, the first connecting line 211 is used for signal transmission, that is, the first connecting line 210 is connected to the signal line 12, while the mesh structure formed by the intersection of the second connecting line 211 and the third connecting line 213 is not connected to the signal line 12. It is only used to provide physical protection for the first connecting line 210 and improve the strength of the first connecting line 210.

[0085] In one possible implementation, the bending region BB further includes an inorganic layer 22 and a second organic layer 23 disposed between the substrate 10 and the connecting line 21 and stacked sequentially in a direction away from the substrate 10. The inorganic layer 22 has a groove 22a formed on its surface away from the substrate 10. The second organic layer 23 covers the inorganic layer 22 and fills the groove 22a. The bottom of the groove 22a is located on the substrate 10.

[0086] Among them, the inorganic layer 22 is a multi-layer structure, and each layer in the multi-layer structure is set on the same layer as a certain inorganic layer in the display area AA, and the second organic layer 23 is set on the same layer as the organic layer in the display panel.

[0087] For example, with Figure 4Taking the display panel shown as an example, the second organic layer 23 is disposed on the same layer as the first planarization layer PLN1 of the display area AA. In the display area AA, there are multiple inorganic layers between the substrate 10 and the first planarization layer PLN1, such as the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate insulating layer GI3, the first interlayer dielectric layer ILD1, the second interlayer dielectric layers ILD2-1 and ILD-2, the passivation layer PVX, the buffer layer Buffer3, etc. In addition, there are multiple barrier layers and buffer layers disposed between the substrate 10 and the driving circuit layer, such as barrier layers Barrier1, Barrier2-1, Barrier2-2, buffer layers Buffer1 and Buffer2, etc. In this embodiment, the inorganic layer 22 in the bending area BB may include multiple inorganic thin film layers disposed on the same layer as each inorganic layer in the display area AA.

[0088] In this embodiment of the disclosure, the groove 22a is an opening that penetrates each layer of the inorganic layer 22, that is, the groove 22a extends from the upper surface of the inorganic layer 22 away from the substrate 10 to the lower surface of the inorganic layer 22 near the substrate 10.

[0089] In practice, the groove 22a can be fabricated through two etching processes. Specifically, the two etching processes are the first etching (EBI, edge bending step A + ILD etch) and the second etching (EBB, edge bending step B). In the EBI process, the interlayer dielectric layer (ILD) within the bending region BB and the film layer below the interlayer dielectric layer (i.e., the side of the interlayer dielectric layer ILD closest to the substrate 10) can be patterned to form an opening. In the EBB process, the bending region BB is further etched to further thin or remove the inorganic layer of the bending region BB.

[0090] Optionally, the bending region BB further includes a third organic layer 24 and a fourth organic layer 25 disposed on the side of the connecting line 21 away from the substrate 10. For example, continuing with... Figure 4 Taking the display panel shown as an example, the third organic base layer 24 and the third planarization layer PLN3 are set on the same layer, and the fourth organic layer 25 and the isolation column layer PS are set on the same layer.

[0091] In one possible implementation, such as Figure 3As shown, the display panel also includes a first fanout area FF-1 disposed between the display area AA and the bending area BB. The first fanout area FF-1 includes multiple fanout lines. The first end of the fanout line is connected to a signal line 12, and the second end of the fanout line is connected to a connecting line 21. The fanout line is disposed in the same layer as at least one of the multilayer conductive layers 11, and the fanout line and the connecting line 21 are located in different conductive layers.

[0092] In this embodiment of the disclosure, the fan-out line in the first fan-out area FF-1 corresponds one-to-one with the signal line 12 in the display area AA, and also corresponds one-to-one with the connecting line 21 in the bending area BB. That is, a signal line 12 in the display area AA is electrically connected to a connecting line 21 in the bending area BB through a fan-out line in the first fan-out area FF-1.

[0093] Optionally, the multilayer conductive layer 11 includes at least a gate layer disposed along a direction away from the substrate 10, and the fan-out line is disposed in the same layer as the gate layer.

[0094] For example, the fan-out line and the gate layer can be configured to be on the same layer: the fan-out line and the gate layer. Figure 4 The first gate Gate1 shown is disposed on the same layer as, or with Figure 4 The second gate Gate2 shown is disposed on the same layer as, or with Figure 4 The third gate (Gate3) is disposed on the same layer as the third source / drain metal layer (SD3). Connector 21 is disposed on the second source / drain metal layer (SD2) and the third source / drain metal layer (SD3). Since the fan-out line and connector 21 are disposed on different layers, they can be electrically connected via interlayer vias. Similarly, the fan-out line and signal line 12 can also be electrically connected via interlayer vias.

[0095] In one possible implementation, such as Figure 3 As shown, the display panel also includes a second fan-out area FF-2, an electrostatic discharge protection zone (ESD), a cell test area (CT), a third fan-out area FF-2, a chip on panel (COP), an inner lead bonding area (ILB), and a flexible circuit board (FPC), which are disposed on the side of the bending area BB away from the display area AA and arranged sequentially along the direction away from the display area AA.

[0096] The ESD protection zone contains electrostatic discharge (ESD) protection circuits, such as ESD ring circuits, which provide ESD protection for data trace 121. The circuit test area (CT) contains test leads for testing the display panel. The chip mounting area (COP) is used to mount the driver IC; some pins of the driver IC can be electrically connected to the flexible printed circuit board (FPC) via traces in the ILB area.

[0097] Among them, the second fan-out area FF-2, the ESD protection zone, the Cell Test area CT, the third fan-out area FF-2, the Chip On Panel (COP), the Inner Lead Bonding (ILB), and the bending area BB are bent together from the light-emitting side of the substrate 10 to the back-light side of the substrate 10. It is understandable that... Figure 3 This diagram only illustrates the location and distribution of the following areas: First Fan-out Area FF-1, Bending Area BB, Second Fan-out Area FF-2, Electrostatic Discharge Protection Area (ESD), Circuit Test Area CT, Third Fan-out Area FF-2, Chip Mounting Area (COP), and Internal Pin Bonding Area (ILB). It does not represent the actual size of the areas.

[0098] Understandable Figure 3 The diagram only schematically shows some signal lines in the display area, as well as traces in areas such as fan-out areas and bend areas. It does not represent the actual number of traces or the spacing between traces, but is only used to illustrate the trace distribution in each area.

[0099] The display panel in this disclosure can be an organic light-emitting diode (OLED) display panel. It is understood that the display panel can also be of other types depending on actual needs; for example, it can also be a quantum dot light-emitting diode (QLED) display panel or a micro light-emitting diode (Micro LED) display panel, etc.

[0100] Based on the same inventive concept, a third aspect of this disclosure provides a display device, including the display panel described above. Exemplarily, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment does not limit this to any particular type.

[0101] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display panel, characterized in that, The display panel includes a substrate having a display area and a bent area located on one side of the display area; The display area includes multiple conductive layers stacked on one side of the substrate. At least one of the multiple conductive layers is provided with multiple signal lines. The bending area includes multiple connecting lines, one connecting line being connected to one signal line. The connecting lines include a first connecting line and a second connecting line stacked along the direction away from the substrate. The first connecting line is disposed in the same layer as one of the multiple conductive layers, and the second connecting line is disposed in the same layer as another of the multiple conductive layers.

2. The display panel according to claim 1, characterized in that, The multilayer conductive layer includes at least a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer stacked sequentially along a direction away from the substrate. The first connecting line is disposed in the same layer as the second source / drain metal layer, and the second connecting line is disposed in the same layer as the third source / drain metal layer.

3. The display panel according to claim 2, characterized in that, The surface of the first connecting line away from the substrate is in contact with the surface of the second connecting line close to the substrate.

4. The display panel according to claim 3, characterized in that, The orthographic projection of the first connecting line on the substrate covers the orthographic projection of the second connecting line on the substrate.

5. The display panel according to claim 4, characterized in that, The edge of the orthographic projection of the first connecting line on the substrate does not overlap with the edge of the orthographic projection of the second connecting line on the substrate.

6. The display panel according to claim 4, characterized in that, The second connecting line includes at least two sub-connecting lines spaced apart along the length of the connecting line.

7. The display panel according to claim 2, characterized in that, The display area further includes a planarization layer disposed between the second source / drain metal layer and the third source / drain metal layer, and the bending area further includes a first organic layer disposed between the first connecting line and the second connecting line. The first organic layer and the planarization layer are disposed in the same layer, and the first connecting line and the second connecting line are electrically connected through vias in the first organic layer.

8. The display panel according to claim 2, characterized in that, The display area further includes a planarization layer disposed between the second source / drain metal layer and the third source / drain metal layer. The bending area further includes a first organic layer disposed between the first connecting line and the second connecting line. The first organic layer and the planarization layer are disposed on the same layer. The connecting line further includes a third connecting line. The first connecting line and the second connecting line extend along a first direction and are arrayed along a second direction. The third connecting line extends along the second direction and is arrayed along the first direction. The third connecting line and the second connecting line are disposed on the same layer and intersect to form a mesh structure. The first connecting line is connected to the signal line. There is no connection between the second connecting line and the third connecting line and the first connecting line.

9. The display panel according to claim 2, characterized in that, The bending area further includes an inorganic layer and a second organic layer disposed between the substrate and the connecting line and stacked sequentially in a direction away from the substrate. The inorganic layer has a groove on its surface away from the substrate. The second organic layer covers the inorganic layer and fills the groove. The bottom of the groove is located on the substrate.

10. The display panel according to claim 1, characterized in that, The display panel further includes a first fan-out area disposed between the display area and the bending area. The first fan-out area includes multiple fan-out lines. The first end of each fan-out line is connected to a signal line, and the second end of each fan-out line is connected to a connecting line. The fan-out lines are disposed in the same layer as at least one of the multilayer conductive layers, and the fan-out lines and the connecting lines are located in different conductive layers.

11. The display panel according to claim 10, characterized in that, The multilayer conductive layer includes at least a gate layer disposed along a direction away from the substrate, and the fan-out line is disposed in the same layer as the gate layer.

12. The display panel according to claim 1, characterized in that, The display panel also includes a second fan-out area, an electrostatic protection area, a circuit test area, a third fan-out area, a chip mounting area, an internal pin bonding area, and a flexible circuit board, which are disposed on the side of the bending area away from the display area and arranged sequentially along the direction away from the display area.

13. The display panel according to claim 1, characterized in that, The signal line includes a data trace, which extends along a first direction and is arranged in an array along a second direction.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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