Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises an output signal line, a grid signal line and a transparent electrode layer. The output signal line is arranged in a first direction; the grid signal lines are arranged in a second direction, and the first direction and the second direction are perpendicular and intersect; the transparent electrode layer and the grid signal line are arranged in the same direction, and the transparent electrode layer is stacked on the grid signal line; wherein the transparent electrode layer is provided with an avoiding area in the first direction, and the intersecting portion of the output signal line and the grid signal line is located in the avoiding area. The intersection part of the output signal line and the grid signal line is located in the avoiding area, so that static electricity can be prevented from being generated at the intersection part of the transparent electrode, the output signal line and the grid signal line, the phenomenon of abnormal grid driving caused by electrostatic discharge is avoided, and the display quality of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a display panel and display device. Background Technology

[0002] Display panels are components in electronic devices used to display images and text, typically consisting of three main parts: display units, a glass substrate, and driving circuitry. Display panels are widely used in televisions, computer monitors, mobile phones, tablets, e-readers, automotive displays, and other fields. They are crucial infrastructure for daily life and the modern electronic information industry. With technological advancements, display panels are also being applied to emerging fields such as wearable devices, smart homes, and medical devices, driving the development of related industries.

[0003] The existing display panel structure is prone to static electricity during the manufacturing process. Reducing the damage caused by static electricity to the display panel is of great importance to improving the yield of the display panel. The output stability of the existing gate output unit is often affected by static electricity.

[0004] Therefore, providing a display panel and display device that can reduce static electricity has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] This application provides a display panel and a display device.

[0006] This application provides a display panel including an output signal line, a gate signal line, and a transparent electrode layer. The output signal line is disposed in a first direction; the gate signal line is disposed in a second direction, the first direction being perpendicular to and intersecting the second direction; the transparent electrode layer is disposed in the same direction as the gate signal line and is superimposed on the gate signal line; wherein, the transparent electrode layer is provided with a clearance region along the first direction, and the portion where the output signal line intersects the gate signal line is located within the clearance region.

[0007] In some embodiments, the pixel electrode layer is connected to the gate signal line via a via.

[0008] In some embodiments, the first direction is horizontal, the second direction is vertical, and the gate signal line is connected to the pixel unit.

[0009] In some embodiments, the vias include a plurality of vias, which are symmetrically arranged along the output signal lines.

[0010] In some embodiments, the first direction is a vertical direction, the second direction is a horizontal direction, and the gate signal line is connected to the pixel unit.

[0011] In some embodiments, the transparent electrode layer is a common electrode.

[0012] In some embodiments, a shielding layer is provided around the via.

[0013] In some embodiments, the transparent conductive layer at the edge of the avoidance area is wavy or serrated.

[0014] In some embodiments, an insulating layer is provided between the gate signal line and the transparent conductive layer.

[0015] Another embodiment of this application provides a display device, including the display panel described in the above embodiments.

[0016] This application provides a display panel including output signal lines, gate signal lines, and a transparent electrode layer. The output signal lines are arranged in a first direction; the gate signal lines are arranged in a second direction, the first direction being perpendicular to and intersecting the second direction; the transparent electrode layer is arranged in the same direction as the gate signal lines and is stacked on top of the gate signal lines; wherein, the transparent electrode layer has a clearance region along the first direction, and the portion where the output signal lines intersect with the gate signal lines is located within the clearance region. Because the portion where the output signal lines intersect with the gate signal lines is located within the clearance region, static electricity can be avoided at the intersection of the transparent electrode and the output and gate signal lines, thereby preventing electrostatic discharge that could cause abnormal gate driving and improving the display quality of the display panel. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0019] Figure 2 This is another structural schematic diagram of the display panel provided in an embodiment of this application.

[0020] Figure 3 This is another structural schematic diagram of the display panel provided in an embodiment of this application.

[0021] Figure 4 This is another structural schematic diagram of the display panel provided in an embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the display device structure provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0024] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0026] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0027] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0028] This application provides a display panel and a display device.

[0029] Please see Figure 1 and Figure 2 This application provides a display panel 100, including an output signal line 10, a gate signal line 20, and a transparent electrode layer 30. The output signal line 10 is disposed in a first direction, and the gate signal line 20 is disposed in a second direction, the first direction being perpendicular to and intersecting the second direction. The transparent electrode layer 30 is disposed in the same direction as the gate signal line 20 and is stacked on the gate signal line 20. The transparent electrode layer 30 is provided with a clearance region 31 along the first direction, and the portion where the output signal line 10 intersects the gate signal line 20 is located within the clearance region 31.

[0030] Static electricity (ESO) has always been a major challenge in the manufacturing process of the display panel 100. The accumulation and release of ESO can damage the gate output unit of the display panel 100, affecting its output stability. To reduce the impact of ESO on the display panel 100, this application provides a clearance region 31 on the transparent electrode layer 30, ensuring that the portion where the output signal line 10 intersects with the gate signal line 20 is located within the clearance region 31. This reduces the accumulation and release of ESO and improves the yield of the display panel 100.

[0031] The transparent electrode layer 30 is a transparent conductive material, typically used in the display panel 100 to transmit electrical signals. The gate signal line 20 is a wire used to control the switching state of the display unit. In this application, the transparent electrode layer 30 and the gate signal line 20 are disposed in the same direction and stacked on the gate signal line 20. The clearance area 31 refers to the portion of the transparent electrode layer 30 without conductive material, such that the portion where the output signal line 10 intersects with the gate signal line 20 is located within this area, thereby reducing the influence of static electricity.

[0032] Specifically, the output signal line 10 is arranged in a first direction, and the gate signal line 20 is arranged in a second direction, with the first and second directions perpendicular to and intersecting each other. The transparent electrode layer 30 is arranged in the same direction as the gate signal line 20 and is stacked on top of the gate signal line 20. The transparent electrode layer 30 has a clearance region 31 along the first direction, and the portion where the output signal line 10 intersects with the gate signal line 20 is located within the clearance region 31. This design effectively reduces the impact of static electricity on the gate signal line 20, thereby improving the output stability of the display panel 100.

[0033] In existing technologies, static electricity is easily generated during the manufacturing process of the display panel 100, affecting the stability of the gate output unit. This application addresses this issue by providing a clearance region 31 on the transparent electrode layer 30, ensuring that the portion where the output signal line 10 intersects with the gate signal line 20 is located within the clearance region 31. This reduces the accumulation and release of static electricity, improving the yield of the display panel 100. This design not only solves the static electricity problem in existing technologies but also enhances the output stability of the display panel 100, demonstrating significant technical advantages.

[0034] This application reduces the accumulation and release of static electricity and improves the yield of the display panel 100 by providing a clearance region 31 on the transparent electrode layer 30, so that the portion where the output signal line 10 intersects with the gate signal line 20 is located within the clearance region 31. The transparent electrode layer 30 and the gate signal line 20 are disposed in the same direction and stacked on the gate signal line 20, while the clearance region 31 is the portion of the transparent electrode layer 30 without conductive material. This design effectively reduces the impact of static electricity on the gate signal line 20, thereby improving the output stability of the display panel 100.

[0035] The transparent electrode layer 30 is disposed in the same direction as the gate signal line 20 and is stacked on top of the gate signal line 20. The transparent electrode layer 30 has a clearance region 31 along the first direction, and the portion where the output signal line 10 intersects with the gate signal line 20 is located within the clearance region 31. This design effectively reduces the impact of static electricity on the gate signal line 20, thereby improving the output stability of the display panel 100. Furthermore, the transparent electrode layer 30 can be a common electrode, and the transparent electrode layer 30 at the edge of the clearance region 31 can be wavy or serrated to further reduce the generation and accumulation of static electricity.

[0036] Furthermore, this application also proposes that the pixel electrode layer and the gate signal line 20 are connected through a via 101.

[0037] In the background art of this application, existing display panels 100 are prone to static electricity generation during manufacturing. Reducing the damage caused by static electricity to the display panel 100 is crucial for improving its yield. Existing gate output units are frequently affected by static electricity, impacting their output stability. The display panel 100 proposed in this application, by connecting the pixel electrode layer and the gate signal line 20 through vias 101, effectively reduces the impact of static electricity on the display panel 100, thereby improving its stability and reliability.

[0038] In the technical solution of this application, the pixel electrode layer and the gate signal line 20 are connected through vias 101. This connection can be implemented in various ways. For example, during the manufacturing process of the display panel 100, a plurality of vias 101 can be formed on the gate signal line 20 using a high-precision etching technique. Then, the pixel electrode layer is filled with these vias 101 using a conductive material to achieve the connection. Furthermore, a shielding layer 40 can be provided around the vias 101 to further reduce electrostatic interference. As a preferred embodiment, the vias 101 can be symmetrically arranged along the output signal line 10 to ensure the stability and uniformity of the connection.

[0039] Through the above technical solution, the display panel 100 of this application can effectively reduce the impact of static electricity on the display panel 100, thereby improving the yield and stability of the display panel 100. Compared with the prior art, the technical solution of this application provides a more effective method to reduce electrostatic interference, thus solving the electrostatic interference problem existing in the prior art. Specifically, by connecting the pixel electrode layer and the gate signal line 20 through vias 101, the stability of the display panel 100 during operation can be ensured, avoiding output instability caused by electrostatic interference. Therefore, the technical solution of this application has significant advantages in improving the performance of the display panel 100.

[0040] Furthermore, this application also proposes that the via 101 includes multiple vias, and the vias 101 are symmetrically arranged along the output signal line 10.

[0041] In this application, the symmetrical arrangement of vias 101 effectively improves the electrical performance of the display panel 100. By symmetrically arranging multiple vias 101 on both sides of the output signal line 10, the potential difference caused by static electricity can be reduced, thereby improving the stability of signal transmission. Specifically, these vias 101 can be evenly distributed on both sides of the output signal line 10, allowing the current to be distributed more evenly and reducing local overheating. At the same time, the symmetrical arrangement of vias 101 can also reduce the influence of parasitic capacitance, further improving the display effect of the display panel 100.

[0042] For example, via 101 can be processed using laser drilling technology, which ensures the precision and consistency of via 101, thereby guaranteeing its electrical performance. Furthermore, the size and spacing of via 101 can be adjusted according to actual needs to achieve optimal electrical performance.

[0043] Therefore, by symmetrically arranging multiple vias 101 on both sides of the output signal line 10, this application provides a technical solution for a display panel 100 that can effectively reduce the influence of electrostatic discharge and improve signal transmission stability. Compared with the prior art, the technical solution of this application can significantly improve the yield and reliability of the display panel 100.

[0044] Furthermore, this application also proposes that the first direction is vertical, the second direction is horizontal, and the gate signal line 20 is connected to the pixel unit 60.

[0045] It is understood that the technical solution of this application involves setting the first direction as vertical and the second direction as horizontal to achieve the connection between the gate signal line 20 and the pixel unit 60. This design can effectively reduce the impact of static electricity on the display panel 100 and improve the yield and output stability of the display panel 100.

[0046] Furthermore, this application also proposes that the transparent electrode layer 30 is a common electrode.

[0047] In the technical solution of this application, the transparent electrode layer 30 is disposed in the same direction as the gate signal line 20 and is stacked on the gate signal line 20. The transparent electrode layer 30 is provided with a clearance region 31 along the first direction, and the portion where the output signal line 10 intersects with the gate signal line 20 is located within the clearance region 31. Through this design, the transparent electrode layer 30 can effectively avoid direct contact with the output signal line 10, thereby reducing the generation and accumulation of static electricity.

[0048] The transparent electrode layer 30, serving as a common electrode, can be made from various materials, such as indium tin oxide (ITO) and indium zinc oxide (IZO), which are transparent conductive materials. These materials possess excellent conductivity and transparency, effectively fulfilling the electrode function without affecting the display effect of the display panel 100. Furthermore, the transparent electrode layer 30 can be fabricated using conventional processes such as sputtering and vapor deposition, ensuring its stability and reliability.

[0049] By employing a transparent electrode layer 30 as a common electrode, the display panel 100 of this application can effectively reduce the generation and accumulation of static electricity, thereby improving the yield and stability of the display panel 100. Compared with the prior art, the technical solution of this application has significant advantages in reducing the impact of static electricity on the display panel 100, solving the problem that the gate output unit is often affected by static electricity in the prior art in terms of output stability. Therefore, the technical solution of this application is of great significance in improving the performance and reliability of the display panel 100.

[0050] Please see Figure 3 Furthermore, this application also proposes that a shielding layer 40 be provided around the via 101.

[0051] The purpose of providing a shielding layer 40 around the via 101 in the display panel 100 is to reduce the impact of static electricity on the display panel 100 and improve the stability and reliability of the display panel 100. The shielding layer 40 can effectively isolate static electricity and prevent it from entering other parts of the display panel 100 through the via 101, thereby protecting the normal operation of the display panel 100.

[0052] Specifically, the shielding layer 40 can be made of various materials and structures, such as metal films and conductive polymers. The shielding layer 40 can be achieved by depositing a conductive material around the via 101, or by forming a conductive pattern around the via 101 during manufacturing. The thickness and material selection of the shielding layer 40 can be adjusted according to specific application requirements to ensure effective electrostatic shielding.

[0053] Therefore, by providing a shielding layer 40 around the via 101, the impact of static electricity on the display panel 100 can be significantly reduced, improving the anti-static capability of the display panel 100, thereby increasing the yield and lifespan of the display panel 100. Compared with the prior art, the solution of this application can more effectively solve the problem of damage to the display panel 100 caused by static electricity, providing a more reliable display panel 100 design.

[0054] Furthermore, this application also proposes that the transparent electrode layer 30 at the edge of the avoidance area 31 is wavy or serrated.

[0055] Understandably, the transparent electrode layer 30 at the edge of the avoidance area 31 is designed in a wavy or sawtooth shape, which can effectively reduce the accumulation and release of static electricity, thereby improving the antistatic performance of the display panel 100 and enhancing the stability and service life of the display panel 100.

[0056] The transparent electrode layer 30 at the edge of the avoidance area 31 can adopt various wavy or sawtooth designs. For example, the wavy design can be a sine wave, square wave, or triangular wave, while the sawtooth design can be equilateral sawtooth, non-equilateral sawtooth, etc. These designs can increase the edge length of the conductive layer, increase the discharge path of static electricity, and thus reduce the impact of static electricity on the display panel 100. Specifically, the wavy or sawtooth transparent electrode layer 30 can be achieved through precise photolithography or laser etching processes to ensure the accuracy of its shape and size.

[0057] This application effectively reduces the impact of static electricity on the display panel 100 by using a wavy or serrated transparent electrode layer 30 at the edge of the avoidance area 31, thereby improving the anti-static performance and stability of the display panel 100. Compared with the prior art, this application provides a more effective technical means to solve the static electricity problem, improving the yield and lifespan of the display panel 100.

[0058] Please see Figure 4 Furthermore, this application also proposes that an insulating layer 50 is provided between the gate signal line 20 and the transparent electrode layer 30.

[0059] The technical understanding of this solution is that by providing an insulating layer 50 between the gate signal line 20 and the transparent electrode layer 30, the impact of static electricity on the display panel 100 can be effectively reduced, thereby improving the stability and reliability of the display panel 100. The presence of the insulating layer 50 avoids direct contact between the gate signal line 20 and the transparent electrode layer 30, thus reducing the possibility of static electricity accumulation and release.

[0060] Specifically, the insulating layer 50 can be made of a high dielectric constant material, such as silicon dioxide or silicon nitride. These materials have good insulation properties and chemical stability, effectively isolating the gate signal line 20 from the transparent electrode layer 30. Furthermore, the thickness of the insulating layer 50 can be adjusted according to actual needs to ensure that electrostatic interference is minimized without affecting the performance of the display panel 100.

[0061] Therefore, the technical solution of setting the insulating layer 50 not only solves the problem that the gate output unit is easily affected by static electricity in the prior art, but also improves the yield and service life of the display panel 100. Compared with the prior art, the technical solution of this application effectively avoids damage to the display panel 100 by adding the insulating layer 50, thereby improving the overall performance of the display panel 100.

[0062] Please see Figure 5Another embodiment of this application also provides a display device 1000, including the display panel 100 described in the above embodiments. Since the display panel 100 has been described in detail in the above embodiments, the display panel 100 in this application will not be described in detail again.

[0063] The thin-film transistor, display panel, and display device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. At the same time, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: The output signal line is configured in the first direction; The gate signal line is arranged in a second direction, and the first direction is perpendicular to and intersects the second direction; A transparent electrode layer is disposed in the same direction as the gate signal line and is stacked on the gate signal line; The transparent electrode layer is provided with a clearance area along a first direction, and the portion where the output signal line intersects with the gate signal line is located within the clearance area.

2. The display panel according to claim 1, characterized in that, The gate signal line is connected to the pixel electrode layer through a via.

3. The display panel according to claim 2, characterized in that, The first direction is horizontal, the second direction is vertical, and the gate signal line is connected to the pixel unit.

4. The display panel according to claim 2, characterized in that, The vias include multiple vias, which are symmetrically arranged along the output signal line.

5. The display panel according to claim 3, characterized in that, The first direction is vertical, the second direction is horizontal, and the gate signal line is connected to the pixel unit.

6. The display panel according to claim 1, characterized in that, The transparent electrode layer is a common electrode.

7. The display panel according to claim 2, characterized in that, A shielding layer is provided around the via.

8. The display panel according to claim 1, characterized in that, The transparent conductive layer at the edge of the avoidance area is wavy or serrated.

9. The display panel according to claim 8, characterized in that, An insulating layer is provided between the gate signal line and the transparent conductive layer.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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