Micro-LED micro display chip

Abstract

The utility model discloses a Micro-LED micro display chip, relates to the technical field of semiconductor electronic devices, and mainly aims to solve the problem of high manufacturing cost of an ID (Identity) identifier of a conventional chip. Comprising a driving back plate, a chip functional area and a chip pin area which are arranged on the driving back plate, and an epitaxial layer which is bonded on the driving back plate through a bonding metal layer, the ID identification graph is located in a peripheral area formed by surrounding the peripheral side parts of the chip functional area and the chip pin area on the driving backboard; wherein the ID identification pattern is a pattern for reserving the bonding metal layer after the epitaxial layer is subjected to a patterning process, and the peripheral region is a region for removing the bonding metal layer after the epitaxial layer is subjected to the patterning process. IDs are recorded in the graphical process, and the process cost of the Micro-LED micro display chip is reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor electronic device technology, and in particular to a Micro-LED micro-display chip. Background Technology

[0002] Micro LED microdisplay chips refer to high-density, tiny LED arrays integrated on a single chip. Like an LED display screen, each pixel can be addressed and individually driven to light up, making it a miniaturized version of outdoor LED displays, reducing pixel distance from millimeters to micrometers. Furthermore, due to the advantages of the miniaturized Micro LED microdisplay chip packaging structure—high resolution, low power consumption, high brightness, high contrast, fast response speed, and long lifespan—it has become a key component of next-generation display technology. Currently, to manage the large number of Micro LED microdisplay chips during production, each chip needs to be configured with an ID. This is typically done by internally embedding the ID code into the chip and reading it through power-on driving, or by using a laser to engrave the ID on the back of the chip wafer. However, both internal embedding and wafer engraving of ID markings require additional processes, significantly increasing production costs and lacking intuitiveness. Utility Model Content

[0003] In view of this, the present invention provides a Micro-LED micro-display chip, the main purpose of which is to solve the problem of high manufacturing cost of existing chip ID labels.

[0004] According to one aspect of the present invention, a Micro-LED microdisplay chip is provided, comprising:

[0005] Drive backplane,

[0006] The chip functional area and chip pin area are arranged on the driver backplane.

[0007] Epitaxial layer, which is bonded to the drive backplane by a bonding metal layer;

[0008] The ID identifier graphic is located in the outer area formed by the peripheral portion of the chip functional area and the chip pin area on the driver backplane;

[0009] Wherein, the ID identifier graphic is a graphic of the epitaxial layer after a patterning process is performed on the epitaxial layer, retaining the bonding metal layer, and the peripheral area is the area of ​​the epitaxial layer after a patterning process is performed on the epitaxial layer, removing the bonding metal layer.

[0010] Preferably, the bonding metal layer includes any one of a eutectic bonding layer, a solder bonding layer, a hot-press bonding layer, and a reactive bonding layer.

[0011] Preferably, the ID identifier graphic includes one or more combinations of number identifier graphics, letter identifier graphics, and text identifier graphics.

[0012] Preferably, the peripheral area includes a first peripheral area and a second peripheral area, wherein the first peripheral area is formed by surrounding the peripheral portion of the chip functional area, and the second peripheral area is formed by surrounding the peripheral portion of the chip pin area, and the ID identifier graphic is located in the first peripheral area and / or the second peripheral area.

[0013] Preferably, the size of the ID identifier graphic is less than or equal to the line width of the first outer region and the second outer region.

[0014] Preferably, the chip further includes: a graphical dam, the graphical dam being formed in the peripheral region;

[0015] The graphical dam includes a first dam, which is disposed around the chip functional area, exposing the chip functional area.

[0016] A first hole for exposing the ID identifier graphic is provided at the position corresponding to the first dam body.

[0017] Preferably, the graphical dam includes a second dam, which surrounds the chip pin area, exposing the chip pin area.

[0018] A second hole for exposing the ID identifier graphic is provided at the corresponding position on the second dam body.

[0019] Preferably, the material of the patterned dam includes at least one of cyclic rubber-type photoresist and cinnamic acid ester-based photoresist.

[0020] Preferably, the patterning process includes laser ablation and / or chemical etching.

[0021] Preferably, the ID identifier graphic is determined based on identity encoding of different chips.

[0022] By employing the above technical solutions, the technical solutions provided by the embodiments of this utility model have at least the following advantages:

[0023] This invention provides a Micro-LED microdisplay chip. Compared with the prior art, the embodiment of this invention includes a driving backplane, a chip functional area, and a chip pin area arranged on the driving backplane, an epitaxial layer bonded to the driving backplane by a bonding metal layer, and an ID identifier pattern located in the peripheral area formed by the chip functional area and the chip pin area on the driving backplane. The ID identifier pattern is a pattern that retains the bonding metal layer after the epitaxial layer is patterned, and the peripheral area is the area where the bonding metal layer is removed after the epitaxial layer is patterned. This allows the ID identifier to be retained during the photolithography process, forming the ID identifier pattern without adding additional processes, greatly reducing the complexity of the ID identifier manufacturing process, lowering manufacturing costs, and making the metal-based ID identifier easier to identify and more intuitive.

[0024] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description

[0025] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0026] Figure 1 This diagram illustrates a Micro-LED microdisplay chip structure according to an embodiment of the present invention.

[0027] Figure 2 This diagram illustrates a schematic of a graphic chip unit structure with an ID identifier provided in an embodiment of the present invention.

[0028] Figure 3 This illustration shows a graphic diagram of a number-letter combination ID identifier provided by an embodiment of the present invention;

[0029] Figure 4 This diagram illustrates a peripheral region structure according to an embodiment of the present invention.

[0030] Figure 5 This diagram illustrates a cross-sectional structure of a dam body according to an embodiment of the present invention.

[0031] Figure 6 A schematic diagram of a hole structure provided by an embodiment of the present invention is shown;

[0032] Reference numerals: 11-Driver backplane, 12-LED chip unit, 121-Chip functional area, 122-Chip pin area, 13-Epipolar layer, 14-Bonding metal layer, 15-ID identifier graphic, 16-Outer region, 161-First outer region, 162-Second outer region, 17-Graphical dam, 171-First dam, 172-Second dam, 18-First hole, 19-Second hole. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or it may extend over a localized area of ​​the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A single layer may comprise multiple layers. For example, a semiconductor layer may comprise one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0035] In the description of this invention, the terms "micro-LED" and "micro-device" refer to the descriptive dimensions of certain devices or structures according to embodiments of this invention. The term "micro-device" or structure as used herein is intended to indicate a scale of 100 nm to 100 μm. However, it should be understood that embodiments of this invention are not necessarily limited thereto, and certain aspects of the embodiments can be applied to larger and possibly smaller size scales.

[0036] This utility model embodiment provides a Micro-LED micro-display chip, such as Figure 1 As shown, the utility model includes: a drive backplate 11,

[0037] The chip functional area 121 and the chip pin area 122 are arranged on the driving backplate 11;

[0038] Epitaxial layer 13, which is bonded to the drive backplate 11 by bonding metal layer 14;

[0039] Among them, such as Figure 2As shown, the ID identifier graphic 15 is located in the peripheral area 16 formed by the peripheral portion of the chip functional area 121 and the chip pin area 122 on the driving backplate 11;

[0040] Wherein, the ID identifier pattern 15 is a pattern of the bonding metal layer 14 retained after the epitaxial layer 13 is patterned, and the peripheral area 16 is the area where the bonding metal layer 14 is removed after the epitaxial layer 13 is patterned.

[0041] In this invention, the driving backplane 11 can specifically be a wafer, and the LED chip unit 12 can be fabricated on the wafer using processes such as PSS, epitaxy, thin film, photolithography, etching, and polishing. The chip functional area 121 and the chip pin area 122 can be chip units (cell 12) that constitute a Micro-LED microdisplay chip (LED chip). Specifically, the chip functional area 121 includes the functional components of the LED chip, including but not limited to transistors, resistors, capacitors, inductors, and other components and circuits required by the LED chip. This area is easily damaged; dust particles and other contaminants falling onto the surface will directly affect its performance and are difficult to clean. The chip pin area 122 includes the input and output interfaces of the LED chip. The internal circuitry of the LED chip is connected to the external circuitry through the chip pin area 122 to achieve input and output functions. The chip pin area 122 can include, but is not limited to, pad structures. The number of pad structures can be one or more, and the arrangement of multiple pad structures can be set according to requirements and is not limited here. Specifically, the chip pin area 122 can be arranged around the chip functional area 121, or as... Figure 1 As shown, it is located on one side of the chip functional area 121. Meanwhile, in this utility model, as... Figure 2 As shown, a peripheral region 16 is formed on the driving backplate 11 around an LED chip unit 12, enclosing the chip functional area 121 and the chip pin area 122. Here, the chip functional area 121 can be the AA region of the LED chip, and the chip pin area 122 can be the PAD region of the chip. The peripheral region 16 surrounding the AA region is formed on the periphery of the chip functional area 121. At least one ID identifier pattern 15, coded for different LED chip units 12, is etched on the peripheral region 16. Additionally, the epitaxial layer 13 can be a single-crystal silicon wafer. The epitaxial layer 13 is bonded to the driving backplate 11 via a bonding metal layer 14. Through a patterning process, the bonding metal surrounding the chip functional area 121 and the chip pin area 122 is removed. Specifically, the bonding metal layer 14 is bonded to the driving backplane 11. Before etching the ID identification image, the bonding metal layer 14 covers the driving backplane 11. Then, the epitaxial layer 13 is patterned through a patterning process, so that the ID identification image is retained on the bonding metal layer 14 to form the chip ID.

[0042] It should be noted that before the patterning process of the Micro-LED microdisplay chip based on this utility model is carried out, the multiple Micro-LED microdisplay chips arranged on the driving backplane 11 are pre-encoded to obtain the ID identification pattern 15 information to be engraved on the driving backplane 11. The photolithography equipment performs patterned layout according to each ID identification pattern 15. At this time, the photolithography position for arranging different ID identification patterns 15 is located in the outer area 16 so as to perform photolithography, etching, resist removal, cleaning and other steps to complete the patterning of the ID identification pattern 15.

[0043] In other embodiments, the bonding metal layer 14 serves as a bonding epitaxial layer material to form a better ID identifier, and the bonding metal layer 131 includes any one of a eutectic bonding layer, a solder bonding layer, a hot-press bonding layer, and a reactive bonding layer.

[0044] In other embodiments, the ID identifier graphic 15 includes one or more combinations of number identifier graphics, letter identifier graphics, and text identifier graphics.

[0045] Specifically, to increase the diversity of encoding effects for Micro-LED microdisplay chips, when encoding chip units of multiple Micro-LED microdisplay chips, the ID identifier graphic 15 can be encoded according to numbers to obtain a numerical identifier graphic, or according to letters such as English letters or Pinyin to obtain a letter identifier graphic, or according to Chinese characters to obtain a text identifier graphic. Of course, the above numbers, letters, and characters can also be arbitrarily combined for encoding to obtain the corresponding ID identifier graphic 15, such as... Figure 3 As shown, the embodiments of this utility model are not specifically limited.

[0046] In other embodiments, such as Figure 4 As shown, the peripheral area 16 includes a first peripheral area 161 and a second peripheral area 162. The first peripheral area 161 is formed by surrounding the peripheral portion of the chip functional area 121, and the second peripheral area 162 is formed by surrounding the peripheral portion of the chip pin area 122. The ID identifier graphic 15 is located in the first peripheral area 161 and / or the second peripheral area 162.

[0047] Specifically, to make ID identification more flexible, during the graphical representation, at least one ID identifier graphic 15 can be retained in the first outer region 161, or at least one ID identifier graphic 15 can be retained in the second outer region 162, or at least one ID identifier graphic 15 can be graphically retained in both the first outer region 161 and the second outer region 162 simultaneously. This embodiment of the invention does not impose specific limitations. Furthermore, the position of the graphically retained ID identifier graphic 15 formed by the bonding metal can be determined based on the ID identification requirements; this embodiment of the invention does not impose specific limitations.

[0048] In other embodiments, the linewidth of the peripheral region 16 is less than or equal to 400 μm. Since multiple Micro-LED microdisplay chips are arranged on the driving backplane 11, the fabrication size of the ID identifier graphic 15 is less than or equal to the linewidth of the first peripheral region 161 and the second peripheral region 162. The linewidth of the peripheral region 16, which is less than or equal to 400 μm, can be below 400 μm to achieve controllable cutting of the chip bezel, significantly reducing the chip bezel area and chip size, and increasing the effective area ratio of the chip.

[0049] In other embodiments, it further includes: a graphical dam body 17, the graphical dam body 17 being formed in the peripheral region 16;

[0050] Since the peripheral area 16 is a non-display area, to prevent dust from entering, a dam material layer is formed on the drive backplate 11 before encapsulation with an optical cover plate structure or a light-transmitting layer. This involves a patterning process on the dam material layer to form multiple patterned dams on the drive backplate 11, such as... Figure 5 As shown, each patterned dam corresponds to a chip unit 12. Each patterned dam is formed in the support area of ​​each chip unit 12 and surrounds the chip functional area 121 and the chip pin area 122. The material of the patterned dam includes at least one of cyclic rubber-type photoresist and cinnamic acid ester-based photoresist. In order to enable the ID identifier pattern 15 to be effectively identified, the ID identifier pattern 15 needs to be exposed on the patterned dam. Since the patterned dam 17 is fabricated by patterning the dam material through an image processing process, and the patterned dam 17 is formed on the peripheral area 16, the area of ​​the ID identifier pattern 15 can be reserved during the image processing process as a hole to expose the ID identifier pattern 15. At this time, the image processing process includes laser ablation and / or chemical etching. For example, laser ablation can include photolithography, and chemical etching can include etching, etc. This embodiment of the present invention does not specifically limit the scope.

[0051] Specifically, such as Figure 6As shown, the graphical dam 17 includes a first dam 171, which surrounds the chip functional area 121 and exposes the chip functional area 121. A first hole 18 for exposing the ID identifier graphic 15 is provided on the first dam 171 at the position corresponding to the ID identifier graphic 15.

[0052] Specifically, the graphical dam 17 includes a second dam 172, which is disposed around the chip pin area 122 to expose the chip pin area 122. The second dam 172 has a second hole 19 at the position corresponding to the ID identifier graphic 15 for exposing the ID identifier graphic 15.

[0053] In other embodiments, the first dam 171 and the second dam 172 are partially joined, such that the dam, as a supporting part, can support the optical cover plate or light-transmitting layer, while exposing the chip functional area 121 and the chip pin area 122. Preferably, the linewidth of the patterned dam 17 can be less than 400 μm.

[0054] This invention provides a Micro-LED microdisplay chip. Compared with the prior art, the embodiment of this invention includes a driving backplane, a chip functional area, and a chip pin area arranged on the driving backplane, an epitaxial layer bonded to the driving backplane by a bonding metal layer, and an ID identifier pattern located in the peripheral area formed by the chip functional area and the chip pin area on the driving backplane. The ID identifier pattern is a pattern that retains the bonding metal layer after the epitaxial layer is patterned, and the peripheral area is the area where the bonding metal layer is removed after the epitaxial layer is patterned. This allows the ID identifier to be retained during the photolithography process, forming the ID identifier pattern without adding additional processes, greatly reducing the complexity of the ID identifier manufacturing process, lowering manufacturing costs, and making the metal-based ID identifier easier to identify and more intuitive.

[0055] It should be noted that, in the description of this utility model, the following definitions of terms shall apply unless a different definition is given elsewhere in the claims or this specification. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​to produce substantially the same properties, functions, results, etc. A range of numerical values ​​indicated by a low value and a high value is defined as including all numerical values ​​included within that range and all subranges included within that range.

[0056] It should be noted that in the description of this utility model, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0057] It should be noted that in the description of this utility model, the terms "on," "above," "over," and "above" should be interpreted in the broadest sense, meaning that a description including these terms is interpreted as "a component may be disposed on another component in direct contact, or there may be an intermediate component or layer between the components." Furthermore, for ease of description, this utility model may also use spatial relative terms such as "below," "under," "below," "on," "above," "lower," and "upper" to describe the relationship between one element or component and another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this utility model can be interpreted accordingly.

[0058] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A Micro-LED microdisplay chip, characterized in that, include: Drive backplane, The chip functional area and chip pin area are arranged on the driver backplane; Epitaxial layer, which is bonded to the drive backplane by a bonding metal layer; The ID identifier graphic is located in the outer area formed by the peripheral portion of the chip functional area and the chip pin area on the driver backplane; Wherein, the ID identifier graphic is a graphic of the epitaxial layer after a patterning process is performed on the epitaxial layer, retaining the bonding metal layer, and the peripheral area is the area of ​​the epitaxial layer after a patterning process is performed on the epitaxial layer, removing the bonding metal layer.

2. The chip according to claim 1, characterized in that, The bonding metal layer includes any one of the following: eutectic bonding layer, solder bonding layer, hot-press bonding layer, and reactive bonding layer.

3. The chip according to claim 1, characterized in that, The ID identifier graphic includes one or more combinations of number identifier graphics, letter identifier graphics, and text identifier graphics.

4. The chip according to claim 1, characterized in that, The peripheral area includes a first peripheral area and a second peripheral area. The first peripheral area is formed by surrounding the peripheral portion of the chip functional area, and the second peripheral area is formed by surrounding the peripheral portion of the chip pin area. The ID identifier graphic is located in the first peripheral area and / or the second peripheral area.

5. The chip according to claim 4, characterized in that, The size of the ID identifier graphic is less than or equal to the line width of the first outer area and the second outer area.

6. The chip according to claim 1, characterized in that, The chip further includes: a graphical dam, the graphical dam being formed in the peripheral region; The graphical dam includes a first dam, which is disposed around the chip functional area, exposing the chip functional area. A first hole for exposing the ID identifier graphic is provided at the position corresponding to the first dam body.

7. The chip according to claim 6, characterized in that, The graphical dam includes a second dam, which surrounds the chip pin area and exposes the chip pin area. A second hole for exposing the ID identifier graphic is provided at the corresponding position on the second dam body.

8. The chip according to claim 7, characterized in that, The material of the patterned dam includes at least one of cyclic rubber-type photoresist and cinnamic acid ester-based photoresist.

9. The chip according to claim 1, characterized in that, The patterning process includes laser ablation and / or chemical etching.

10. The chip according to any one of claims 1-9, characterized in that, The ID identifier graphic is determined based on the identity encoding of different chips.

Images