Display panel and display terminal

Abstract

The utility model relates to a display panel and a display terminal. The display panel comprises a substrate and a sub-pixel, wherein the sub-pixel comprises a first common electrode, a pixel electrode and a second common electrode; the pixel electrode and the second common electrode are both arranged on the side, away from the substrate, of the first common electrode, the pixel electrode comprises a plurality of pixel branch electrodes, and the second common electrode comprises a plurality of common branch electrodes; the orthographic projection of the pixel branch electrode on the substrate is not overlapped with the orthographic projection of the common branch electrode on the substrate, and the orthographic projection of the pixel branch electrode on the substrate and the orthographic projection of the first common electrode on the substrate have an overlapped part. The orthographic projection of the second common electrode and the orthographic projection of the pixel electrode on the substrate are not overlapped, and the pixel branch electrode and the common branch electrode can form an edge electric field; the orthographic projection of the pixel branch electrode and the orthographic projection of the first common electrode on the substrate have an overlapped part, the overlapped part can form a storage capacitor, and the capacitance value of the storage capacitor can be adjusted by adjusting the area of the overlapped part.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display terminal. BACKGROUND

[0002] HFS (Hybrid Fringe Field Switching) technology is an important technology in the field of liquid crystal display. By generating a specific distribution of electric field at the edge of the electrode, the orientation of the liquid crystal molecules not only changes in the plane, but also has a certain degree of adjustment in the direction perpendicular to the plane. This unique driving mode can achieve more precise control of liquid crystal molecules, and compared with some traditional technologies such as TN (Twisted Nematic) technology, it can make the response speed of liquid crystal molecules faster, and ensure good optical performance at different viewing angles.

[0003] The HFS technology faces the problem that the capacitance of the storage capacitor (Cst) is difficult to meet the requirements. If the storage capacitor is too large, it will be difficult to achieve high-frequency driving, and when displaying high-speed dynamic pictures, it will have a serious impact on the smoothness of the picture, and ghosting phenomenon is prone to occur. While a small storage capacitor is beneficial to the realization of high-frequency driving, but it is easy to cause image flicker, picture contrast reduction and other problems, which are not conducive to the display quality.

[0004] Therefore, it is urgent to solve the above technical problems. CONTENT OF THE INVENTION

[0005] The display panel provided by the embodiments of the present application can improve the technical problem that the capacitance of the storage capacitor in the display panel is difficult to meet the requirements.

[0006] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, comprising a substrate and a plurality of sub-pixels arranged on one side of the substrate, and each sub-pixel comprises:

[0007] a first common electrode arranged on one side of the substrate;

[0008] a pixel electrode and a second common electrode arranged in different layers, wherein the pixel electrode and the second common electrode are both arranged on the side of the first common electrode away from the substrate, the pixel electrode comprises a plurality of pixel branch electrodes arranged at intervals, and the second common electrode comprises a plurality of common branch electrodes arranged at intervals;

[0009] wherein the orthogonal projection of the pixel branch electrode on the substrate does not overlap with the orthogonal projection of the common branch electrode on the substrate, and the orthogonal projection of the pixel branch electrode on the substrate has an overlapping part with the orthogonal projection of the first common electrode on the substrate.

[0010] Optionally, the second common electrode is arranged on a side of the pixel electrode away from the substrate, and a width of the first common electrode is less than a width of the pixel electrode in a direction in which the two adjacent pixel branch electrodes are arranged.

[0011] Optionally, the second common electrode is arranged on a side of the pixel electrode away from the substrate, and a width of the first common electrode is greater than a width of the pixel electrode in a direction in which the two adjacent pixel branch electrodes are arranged.

[0012] Optionally, the pixel electrode is arranged on a side of the second common electrode away from the substrate, and a width of the first common electrode is less than a width of the pixel electrode in a direction in which the two adjacent pixel branch electrodes are arranged.

[0013] Optionally, the pixel electrode is arranged on a side of the second common electrode away from the substrate, and a width of the first common electrode is greater than a width of the pixel electrode in a direction in which the two adjacent pixel branch electrodes are arranged.

[0014] Optionally, a width of the pixel branch electrode is 1.0-3.0 microns, and a distance between the two adjacent pixel branch electrodes is 3.0-7.0 microns.

[0015] Optionally, a width of the common branch electrode is 1.0-3.0 microns, and a distance between the two adjacent common branch electrodes is 3.0-7.0 microns.

[0016] Optionally, a distance between a projection of the pixel branch electrode on the substrate and a projection of the adjacent common branch electrode on the substrate is 0-2.0 microns.

[0017] Optionally, a first insulating layer is arranged between the pixel electrode and the second common electrode, and a second insulating layer is arranged between the pixel electrode and the second common electrode close to the first common electrode and the first common electrode.

[0018] Optionally, a thickness of the first insulating layer is less than a thickness of the second insulating layer.

[0019] According to a second aspect of the present application, a display terminal is provided, which comprises the display panel.

[0020] In the display panel of the present application, the projection of the second common electrode and the pixel electrode on the substrate do not overlap, the pixel branch electrode can form an edge electric field with the common branch electrode, the projection of the pixel branch electrode and the first common electrode on the substrate has an overlapping part, the overlapping part can form a storage capacitor, and the capacitance of the storage capacitor can be adjusted by adjusting the area of the overlapping part to meet the capacitance requirement.

[0021] Other features and advantages of the present application will be illustrated in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0023] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0024] Figure 1 is a schematic top view of a display panel provided in an exemplary embodiment of the present disclosure;

[0025] Figure 2 is Figure 1 is a schematic enlarged structure of a sub-pixel in the display panel of

[0026] Figure 3 is Figure 2 is a schematic cross-sectional structure at C-C in the display panel of

[0027] Figure 4 is Figure 2 is another schematic cross-sectional structure at C-C in the display panel of

[0028] Figure 5 is Figure 1 is a schematic enlarged structure of another sub-pixel in the display panel of

[0029] Figure 6 is Figure 5 is a schematic cross-sectional structure at D-D in the display panel of

[0030] Figure 7 is Figure 5 is another schematic cross-sectional structure at D-D in the display panel of

[0031] Figure 8 is a schematic structure of a display terminal provided in an exemplary embodiment of the present disclosure.

[0032] Explanation of Reference Numerals:

[0033] 1 - display panel; AA - display area; NA - non-display area; 11 - sub-pixel;

[0034] 10 - substrate;

[0035] 20 - first common electrode;

[0036] 30 - pixel electrode; 31 - pixel branch electrode;

[0037] 40 - second common electrode; 41 - common branch electrode;

[0038] 51 - first insulating layer; 52 - second insulating layer;

[0039] 53 - black matrix;

[0040] 54 - data line; 55 - scan line;

[0041] 60 - thin film transistor; 61 - gate; 62 - source; 63 - drain;

[0042] W1 - width of the first common electrode 20; W2 - width of the pixel electrode 30;

[0043] L1 - width of the pixel branch electrode 31; S1 - spacing between two adjacent pixel branch electrodes 31;

[0044] L2 - width of the common branch electrode 41; S2 - spacing between two adjacent common branch electrodes 41;

[0045] H - spacing between the orthogonal projection of the pixel branch electrode 31 on the substrate 10 and the orthogonal projection of the adjacent common branch electrode 41 on the substrate 10;

[0046] 2 - display terminal; 3 - terminal body. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor are within the protection scope of the present application.

[0048] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, a display terminal is provided, comprising: Figures 1 to 4As shown, a display panel 1 is provided, which includes a substrate 10 and a plurality of sub-pixels 11 disposed on one side of the substrate 10. Each sub-pixel 11 includes a first common electrode 20, a pixel electrode 30 and a second common electrode 40. The first common electrode 20 is disposed on one side of the substrate 10. The pixel electrode 30 and the second common electrode 40 are both disposed on the side of the first common electrode 20 away from the substrate 10. The pixel electrode 30 includes a plurality of pixel branch electrodes 31 disposed at intervals. The second common electrode 40 includes a plurality of common branch electrodes 41 disposed at intervals. The orthogonal projection of the pixel branch electrodes 31 on the substrate 10 does not overlap the orthogonal projection of the common branch electrodes 41 on the substrate 10. The orthogonal projection of the pixel branch electrodes 31 on the substrate 10 has an overlapping portion with the orthogonal projection of the first common electrode 20 on the substrate 10.

[0049] The display panel 1 is a liquid crystal panel. The display panel 1 includes a substrate 10 and an opposing substrate (not shown in the figure) opposite and spaced apart from each other. A liquid crystal layer (not shown in the figure) is disposed between the substrate 10 and the opposing substrate. The liquid crystal molecules in the liquid crystal layer have special optical properties. Under the action of an applied electric field, the molecular arrangement direction of the liquid crystal molecules changes, thereby changing the polarization state and transmittance of light.

[0050] In some embodiments, the substrate 10 and the opposing substrate can be made of glass or other materials.

[0051] In some embodiments, the display panel 1 includes a color filter layer, which can be disposed on the substrate 10 or the opposing substrate. The color filter layer includes a plurality of red color resist, a plurality of green color resist and a plurality of blue color resist. The red color resist allows red light to pass through while blocking other colors of light. The green color resist allows green light to pass through while blocking other colors of light. The blue color resist allows blue light to pass through while blocking other colors of light.

[0052] A black matrix 53 is disposed between adjacent two color resist. The black matrix 53 can be a light-blocking material and can block light. The black matrix 53 can prevent color crosstalk between adjacent two sub-pixels 11.

[0053] It should be noted that the liquid crystal panel is a non-self-luminous panel. A backlight source needs to be disposed on one side of the display panel 1. The white light emitted by the backlight source is converted into color light of corresponding colors by the color filter layer, thereby realizing color display.

[0054] As shown in FIG. 1, the display panel 1 includes a plurality of sub-pixels 11 disposed on one side of the substrate 10. Each sub-pixel 11 includes a first common electrode 20, a pixel electrode 30 and a second common electrode 40. The first common electrode 20 is disposed on one side of the substrate 10. The pixel electrode 30 and the second common electrode 40 are both disposed on the side of the first common electrode 20 away from the substrate 10. The pixel electrode 30 includes a plurality of pixel branch electrodes 31 disposed at intervals. The second common electrode 40 includes a plurality of common branch electrodes 41 disposed at intervals. The orthogonal projection of the pixel branch electrodes 31 on the substrate 10 does not overlap the orthogonal projection of the common branch electrodes 41 on the substrate 10. The orthogonal projection of the pixel branch electrodes 31 on the substrate 10 has an overlapping portion with the orthogonal projection of the first common electrode 20 on the substrate 10. Figure 1As shown, the display panel 1 includes a display area AA and a non-display area NA disposed around the periphery of the display area AA. The display area AA may be provided with multiple sub-pixels 11, which may include red sub-pixels 11, green sub-pixels 11, and blue sub-pixels 11. One color resist corresponds to one sub-pixel 11; for example, one red color resist corresponds to one red sub-pixel 11, one green color resist corresponds to one green sub-pixel 11, and one blue color resist corresponds to one blue sub-pixel 11.

[0055] The non-display area NA can be equipped with a driving circuit, such as a gate driving circuit, which can provide driving signals for the sub-pixel 11.

[0056] like Figure 2 and Figure 3 As shown, a sub-pixel 11 includes a first common electrode 20, which can be a continuous block of electrodes or a patterned electrode. Figure 2 The description of the first common electrode 20 as a continuous, monolithic electrode should not be construed as a limitation of this application. The first common electrode 20 can be connected to a constant voltage.

[0057] like Figure 2 and Figure 3 As shown, the display panel 1 includes pixel electrodes 30 and a second common electrode 40 disposed in different layers. Both the pixel electrodes 30 and the second common electrode 40 are disposed on the substrate 10. Dissimilar layer placement means that the pixel electrodes 30 and the second common electrode 40 are separated by an insulating layer, and the pixel electrodes 30 and the second common electrode 40 are fabricated sequentially through two processes. The pixel electrodes 30 can be connected to a pixel voltage, and the second common electrode 40 can be connected to a constant voltage.

[0058] In some embodiments, such as Figure 3 As shown, in the thickness direction of the display panel 1, the pixel electrode 30 can be disposed between the first common electrode 20 and the second common electrode 40. The thickness direction of the display panel 1 is... Figure 3 The vertical direction in the middle.

[0059] In other embodiments, such as Figure 4 As shown, in the thickness direction of the display panel 1, the second common electrode 40 can be disposed between the first common electrode 20 and the pixel electrode 30. The thickness direction of the display panel 1 is... Figure 4 The vertical direction in the middle.

[0060] To prevent the first common electrode 20, pixel electrode 30, and second common electrode 40 from blocking light, the first common electrode 20, pixel electrode 30, and second common electrode 40 are all transparent conductive materials, such as one or more of the following stacked materials: ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), and InO (indium oxide).

[0061] like Figure 2 and Figure 3 As shown, the pixel electrode 30 includes a plurality of pixel branch electrodes 31 spaced apart. This means that the pixel electrode 30 can be a comb-shaped electrode, with a gap between adjacent pixel branch electrodes 31. The second common electrode 40 includes a plurality of common branch electrodes 41 spaced apart. This means that the second common electrode 40 can be a comb-shaped electrode, with a gap between adjacent common branch electrodes 41.

[0062] In some embodiments, such as Figure 2 As shown, the ends of multiple pixel branch electrodes 31 are connected, which facilitates connection to the same pixel voltage. The end of a pixel branch electrode 31 refers to one of two ends along the extension direction of the pixel branch electrode 31.

[0063] In some embodiments, such as Figure 2 As shown, the ends of multiple common branch electrodes 41 are connected to facilitate connection to the same common voltage. The end of the common branch electrode 41 refers to one of two ends along the extension direction of the common branch electrode 41.

[0064] For example, such as Figure 2 As shown, multiple pixel branch electrodes 31 are connected near the lower end, and multiple common branch electrodes 41 are connected near the upper end.

[0065] like Figure 2 and Figure 3 As shown, the orthographic projection of the pixel branch electrode 31 on the substrate 10 does not overlap with the orthographic projection of the common branch electrode 41 on the substrate 10. This means that the pixel branch electrode 31 and the common branch electrode 41 can be staggered, with the pixel branch electrode 31 positioned between the gaps of two adjacent common branch electrodes 41. Through this arrangement, adjacent pixel branch electrodes 31 and common branch electrodes 41 can generate an edge electric field. This edge electric field can control the deflection of liquid crystal molecules in the liquid crystal layer to achieve different light transmittances, thereby controlling the brightness of the displayed image.

[0066] like Figure 2and Figure 3 As shown, the orthographic projection of the pixel branch electrode 31 on the substrate 10 overlaps with the orthographic projection of the first common electrode 20 on the substrate 10. This means that at least a portion of the orthographic projection of the pixel branch electrode 31 on the substrate 10 lies within the orthographic projection of the first common electrode 20 on the substrate 10. The overlap between the pixel branch electrode 31 and the first common electrode 20 forms a storage capacitor. By adjusting the size and pattern of the first common electrode 20, the overlap area between the first common electrode 20 and the pixel branch electrode 31 can be adjusted, thereby adjusting the size of the storage capacitor. Since the size and pattern of the first common electrode 20 are not affected by the pixel electrode 30 and the second common electrode 40, the size and pattern of the first common electrode 20 can be flexibly adjusted to ensure that the capacitance value of the storage capacitor meets the requirements.

[0067] In some embodiments, such as Figure 2 As shown, the display panel 1 also includes multiple data lines 54, multiple scan lines 55, and multiple thin-film transistors 60, etc.

[0068] Multiple data lines 54 can extend along a first direction, and multiple scan lines 55 can extend along a second direction. The intersection of the data lines 54 and scan lines 55 defines the area of ​​the sub-pixel 11. The first direction and the second direction are set at an angle, for example, the angle can be 90 degrees, but is not limited to this.

[0069] Thin-film transistors 60 can be disposed in the display area AA and the non-display area NA. Thin-film transistors 60 located in the non-display area NA can be used to form gate 61 driving circuits, etc. Thin-film transistors 60 located in the display area AA can be used to form pixel driving circuits, etc. Figure 2 The image shows a thin-film transistor 60 located in display area AA.

[0070] like Figure 2 As shown, the thin-film transistor 60 includes a source 62, a drain 63, and a gate 61. In the display area AA, the source 62 of the thin-film transistor 60 can be connected to the data line 54, the drain 63 can be electrically connected to the pixel electrode 30, and the gate 61 can be connected to the scan line 55. The data line 54 inputs a pixel voltage to the pixel electrode 30 via the thin-film transistor 60. The liquid crystal molecules in the liquid crystal layer are deflected under the drive of the pixel voltage and the common voltage of the second common electrode 40, thereby controlling the light transmittance of the display panel 1.

[0071] In some embodiments, the source electrode 62, the drain electrode 63 and the data line 54 are arranged on the same layer, so that they can be formed using the same patterning process, simplifying the manufacturing process of the display panel 1.

[0072] In some embodiments, the gate 61 and the scan line 55 are disposed on the same layer, so that they can be formed using the same patterning process, simplifying the manufacturing process of the display panel 1.

[0073] It should be noted that the two adjacent layers of conductive material are separated by an insulating layer. The material of the insulating layer can be one or a stack of multiple of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0074] Optionally, as shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30. Figure 2 and Figure 3 As shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30.

[0075] According to the formula of capacitance, C = ∈S / d, where C represents the capacitance, ∈ is the dielectric constant of the dielectric between the two plates, S is the facing area of the two plates, and d is the distance between the two plates.

[0076] Since the pixel branch electrode 31 is located on the side of the second common electrode 40 close to the first common electrode 20, the distance d between the pixel branch electrode 31 and the first common electrode 20 is small. At this time, the width W1 of the first common electrode 20 can be less than the width W2 of the pixel electrode 30, so as to reduce S to achieve the capacitance value of the required storage capacitance.

[0077] As shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30. Figure 3 Optionally, as shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30.

[0078] Figure 5 As shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30. Figure 6 Figure 5 The difference between the embodiment in FIGS. 1B and 2B and the embodiment in FIGS. 1A and 2A is the width W1 of the first common electrode 20. Figure 2 As shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30. Through the above arrangement, the capacitance value of the required storage capacitance can be achieved. Figure 6 Optionally, as shown in FIGS. 1B and 2B, the second common electrode 40 is disposed on the side of the pixel electrode 30 away from the substrate 10. In the arrangement direction of the two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is less than the width W2 of the pixel electrode 30.

[0079] Figure 2 The difference between the embodiment in FIGS. 1B and 2B and the embodiment in FIGS. 1A and 2A is the layering order of the pixel electrode 30 and the second common electrode 40. Figure 4 Figure 4 The difference between the embodiment in FIGS. 1B and 2B and the embodiment in FIGS. 1A and 2A is the layering order of the pixel electrode 30 and the second common electrode 40. Figure 3 Figure 4 ​​​​​The pixel electrode 30 is disposed on the side of the second common electrode 40 away from the substrate 10. In the arrangement direction of two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is smaller than the width W2 of the pixel electrode 30. With the above arrangement, the required capacitance value of the storage capacitor can be achieved.

[0080] Optionally, such as Figure 5 and Figure 7 As shown, Figure 7 The embodiments and Figure 6 The difference in the embodiments lies in the different stacking order of the pixel electrode 30 and the second common electrode 40. Figure 7 The pixel electrode 30 is disposed on the side of the second common electrode 40 away from the substrate 10. In the arrangement direction of two adjacent pixel branch electrodes 31, the width W1 of the first common electrode 20 is greater than the width W2 of the pixel electrode 30. With the above arrangement, the required capacitance value of the storage capacitor can be achieved.

[0081] Optionally, such as Figure 3 As shown, the width L1 of the pixel branch electrode 31 ranges from 1.0 micrometer to 3.0 micrometer. For example, the width L1 of the pixel branch electrode 31 can be 1.0 micrometer, 1.1 micrometer, 1.2 micrometer, 1.3 micrometer, 1.4 micrometer, 1.5 micrometer, 1.6 micrometer, 1.7 micrometer, 1.8 micrometer, 1.9 micrometer, 2.0 micrometer, 2.1 micrometer, 2.2 micrometer, 2.3 micrometer, 2.4 micrometer, 2.5 micrometer, 2.6 micrometer, 2.7 micrometer, 2.8 micrometer, 2.9 micrometer, 3.0 micrometer, etc.

[0082] like Figure 3 As shown, the spacing S1 between two adjacent pixel branch electrodes 31 ranges from 3.0 micrometers to 7.0 micrometers. For example, the spacing S1 between two adjacent pixel branch electrodes 31 can be 3.0 micrometers, 3.1 micrometers, 3.2 micrometers, 3.3 micrometers, 3.4 micrometers, 3.5 micrometers, 3.6 micrometers, 3.7 micrometers, 3.8 micrometers, 3.9 micrometers, 4.0 micrometers, 4.1 micrometers, 4.2 micrometers, 4.3 micrometers, 4.4 micrometers, 4.5 micrometers, 4.6 micrometers, 4.7 micrometers, 4.8 micrometers, 4.9 micrometers, 5.0 micrometers, 5.1 micrometers, 5.2 micrometers, 5.3 micrometers, 5.4 micrometers, 5.5 micrometers, 5.6 micrometers, 5.7 micrometers, 5.8 micrometers, 5.9 micrometers, 6.0 micrometers, 6.1 micrometers, 6.2 micrometers, 6.3 micrometers, 6.4 micrometers, 6.5 micrometers, 6.6 micrometers, 6.7 micrometers, 6.8 micrometers, 6.9 micrometers, 7.0 micrometers, etc.

[0083] Optionally, such as Figure 3As shown, the width L2 of the common branch electrode 41 ranges from 1.0 micrometer to 3.0 micrometer. For example, the width L2 of the common branch electrode 41 is 1.0 micrometer, 1.1 micrometer, 1.2 micrometer, 1.3 micrometer, 1.4 micrometer, 1.5 micrometer, 1.6 micrometer, 1.7 micrometer, 1.8 micrometer, 1.9 micrometer, 2.0 micrometer, 2.1 micrometer, 2.2 micrometer, 2.3 micrometer, 2.4 micrometer, 2.5 micrometer, 2.6 micrometer, 2.7 micrometer, 2.8 micrometer, 2.9 micrometer, 3.0 micrometer, etc.

[0084] like Figure 3 As shown, the spacing S2 between two adjacent common branch electrodes 41 ranges from 3.0 micrometers to 7.0 micrometers. For example, the spacing S2 between two adjacent common branch electrodes 41 can be 3.0 micrometers, 3.1 micrometers, 3.2 micrometers, 3.3 micrometers, 3.4 micrometers, 3.5 micrometers, 3.6 micrometers, 3.7 micrometers, 3.8 micrometers, 3.9 micrometers, 4.0 micrometers, 4.1 micrometers, 4.2 micrometers, 4.3 micrometers, 4.4 micrometers, 4.5 micrometers, 4.6 micrometers, 4.7 micrometers, 4.8 micrometers, 4.9 micrometers, 5.0 micrometers, 5.1 micrometers, 5.2 micrometers, 5.3 micrometers, 5.4 micrometers, 5.5 micrometers, 5.6 micrometers, 5.7 micrometers, 5.8 micrometers, 5.9 micrometers, 6.0 micrometers, 6.1 micrometers, 6.2 micrometers, 6.3 micrometers, 6.4 micrometers, 6.5 micrometers, 6.6 micrometers, 6.7 micrometers, 6.8 micrometers, 6.9 micrometers, 7.0 micrometers, etc.

[0085] Optionally, such as Figure 3 As shown, the distance H between the orthographic projection of the pixel branch electrode 31 on the substrate 10 and the orthographic projection of the adjacent common branch electrode 41 on the substrate 10 is 0 micrometers to 2.0 micrometers. For example, the distance H between the orthographic projection of the pixel branch electrode 31 on the substrate 10 and the orthographic projection of the adjacent common branch electrode 41 on the substrate 10 is 0 micrometers, 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, 1.0 micrometers, 1.1 micrometers, 1.2 micrometers, 1.3 micrometers, 1.4 micrometers, 1.5 micrometers, 1.6 micrometers, 1.7 micrometers, 1.8 micrometers, 1.9 micrometers, 2.0 micrometers, etc.

[0086] The smaller the distance H between the orthographic projection of the pixel branch electrode 31 on the substrate 10 and the orthographic projection of the adjacent common branch electrode 41 on the substrate 10, the higher the contrast ratio (CR), the higher the transmittance, and the faster the response time of the display panel 1.

[0087] like Figure 3As shown, the orthogonal projection of the pixel branch electrode 31 on the substrate 10 is located between the orthogonal projections of two adjacent common branch electrodes 41 on the substrate 10. The interval H between the orthogonal projection of the pixel branch electrode 31 on the substrate 10 and the orthogonal projection of the adjacent common branch electrode 41 on the substrate 10 refers to the interval between the pixel branch electrode 31 and the closest common branch electrode 41 in the orthogonal projection pattern.

[0088] Optionally, as shown in FIG. 1A, a first insulating layer 51 is arranged between the pixel electrode 30 and the second common electrode 40, and a second insulating layer 52 is arranged between one of the pixel electrode 30 and the second common electrode 40 close to the first common electrode 20 and the first common electrode 20. Figure 3 As shown, the orthogonal projection of the pixel branch electrode 31 on the substrate 10 is located between the orthogonal projections of two adjacent common branch electrodes 41 on the substrate 10. The interval H between the orthogonal projection of the pixel branch electrode 31 on the substrate 10 and the orthogonal projection of the adjacent common branch electrode 41 on the substrate 10 refers to the interval between the pixel branch electrode 31 and the closest common branch electrode 41 in the orthogonal projection pattern.

[0089] The material of the first insulating layer 51 can be one or a stack of multiple of silicon nitride, silicon oxide, and silicon oxynitride.

[0090] In some embodiments, the thickness of the first insulating layer 51 can be 1000 angstroms to 5000 angstroms. For example, the thickness of the first insulating layer 51 can be 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, etc.

[0091] The one of the pixel electrode 30 and the second common electrode 40 close to the first common electrode 20 refers to the one of the pixel electrode 30 and the second common electrode 40 with a smaller interval from the first common electrode 20 in the thickness direction of the display panel 1.

[0092] As shown in FIG. 1A, the one of the pixel electrode 30 and the second common electrode 40 close to the first common electrode 20 is the second common electrode 40. Figure 4 and Figure 7 As shown in FIG. 1A, the one of the pixel electrode 30 and the second common electrode 40 close to the first common electrode 20 is the second common electrode 40.

[0093] As shown in FIG. 1A, the one of the pixel electrode 30 and the second common electrode 40 close to the first common electrode 20 is the second common electrode 40. Figure 3 and Figure 6 As shown in FIG. 1A, the one of the pixel electrode 30 and the second common electrode 40 close to the first common electrode 20 is the second common electrode 40.

[0094] The material of the second insulating layer 52 can be one or a stack of multiple of silicon nitride, silicon oxide, and silicon oxynitride.

[0095] In some embodiments, the thickness of the second insulating layer 52 can be 6000 angstroms to 10000 angstroms. For example, the thickness of the second insulating layer 52 can be 6000 angstroms, 7000 angstroms, 8000 angstroms, 9000 angstroms, 10000 angstroms, etc.

[0096] In some embodiments, as shown in FIG. 1, the display panel 1 includes a first insulating layer 51, a second insulating layer 52, a first common electrode 20, a second common electrode 40, a data line 54, a pixel electrode 30, and a storage capacitor C. Figure 3 In some embodiments, as shown in FIG. 1, the display panel 1 includes a first insulating layer 51, a second insulating layer 52, a first common electrode 20, a second common electrode 40, a data line 54, a pixel electrode 30, and a storage capacitor C.

[0097] In some embodiments, the thickness of the gate insulating layer can be 3000 angstroms to 5000 angstroms. For example, the thickness of the gate insulating layer can be 3000 angstroms, 4000 angstroms, 5000 angstroms, etc.

[0098] In some embodiments, the thickness of the passivation layer can be 3000 angstroms to 5000 angstroms. For example, the thickness of the passivation layer can be 3000 angstroms, 4000 angstroms, 5000 angstroms, etc.

[0099] According to the formula of capacitance, C = ∈S / d, where C represents the capacitance, ∈ is the dielectric constant of the dielectric between the two plates, S is the facing area of the two plates, and d is the distance between the two plates.

[0100] In some embodiments, as shown in FIG. 1, the display panel 1 includes a first insulating layer 51, a second insulating layer 52, a first common electrode 20, a second common electrode 40, a data line 54, a pixel electrode 30, and a storage capacitor C. Figure 3 and Figure 6 As shown in FIG. 1, ∈ is the dielectric constant of the second insulating layer 52, S is the facing area of the first common electrode 20 and the pixel electrode 30, and d is the thickness of the second insulating layer 52. By adjusting S, d, ∈, the storage capacitance can meet the requirements, and the best capacitance value of the storage capacitor is obtained.

[0101] In some embodiments, as shown in FIG. 1, the display panel 1 includes a first insulating layer 51, a second insulating layer 52, a first common electrode 20, a second common electrode 40, a data line 54, a pixel electrode 30, and a storage capacitor C. Figure 4 and Figure 7 As shown in FIG. 1, ∈1 is the dielectric constant of the first insulating layer 51, ∈2 is the dielectric constant of the second insulating layer 52, S is the facing area of the first common electrode 20 and the pixel electrode 30, d1 is the thickness of the first insulating layer 51, and d2 is the thickness of the second insulating layer 52. Then C = S / (d1 / ∈1 + d2 / ∈2). By adjusting S, d1, d2, ∈1, ∈2, the storage capacitance can meet the requirements, and the best capacitance value of the storage capacitor is obtained.

[0102] According to the second aspect of the present application, as shown in FIG. 2, a display terminal 2 is provided, which includes the display panel 1 described above. Figure 8 In the present embodiment, as shown in FIG. 2, the display terminal 2 includes the display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one.

[0103] Figure 8 In the present embodiment, as shown in FIG. 2, the display terminal 2 includes the display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one.

[0104] ​In the embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0105] In the description of the present application, the terms "first", "second" are only used for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0106] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0107] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0108] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment without departing from the technical solution of the present application and according to the technical essence of the present application still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate, one of the sub-pixels comprising: a first common electrode arranged on one side of the substrate; a pixel electrode and a second common electrode arranged in layers, the pixel electrode and the second common electrode are both arranged on the side of the first common electrode away from the substrate, the pixel electrode comprises a plurality of pixel branch electrodes arranged at intervals, and the second common electrode comprises a plurality of common branch electrodes arranged at intervals; wherein the orthogonal projection of the pixel branch electrode on the substrate does not overlap with the orthogonal projection of the common branch electrode on the substrate, and the orthogonal projection of the pixel branch electrode on the substrate has an overlapping part with the orthogonal projection of the first common electrode on the substrate.

2. The display panel of claim 1, wherein, The second common electrode is arranged on the side of the pixel electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is smaller than the width of the pixel electrode.

3. The display panel of claim 1, wherein, The second common electrode is arranged on the side of the pixel electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is greater than the width of the pixel electrode.

4. The display panel of claim 1, wherein, The pixel electrode is arranged on the side of the second common electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is smaller than the width of the pixel electrode.

5. The display panel of claim 1, wherein, The pixel electrode is arranged on the side of the second common electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is greater than the width of the pixel electrode.

6. The display panel of any one of claims 1 to 5, wherein, The width of the pixel branch electrode is 1.0-3.0 microns, and the distance between the two adjacent pixel branch electrodes is 3.0-7.0 microns.

7. The display panel of claim 6, wherein, The width of the common branch electrode is 1.0-3.0 microns, and the distance between the two adjacent common branch electrodes is 3.0-7.0 microns.

8. The display panel of claim 7, wherein, The distance between the orthogonal projection of the pixel branch electrode on the substrate and the orthogonal projection of the adjacent common branch electrode on the substrate is 0-2.0 microns.

9. The display panel of any one of claims 1 to 5, wherein, A first insulating layer is arranged between the pixel electrode and the second common electrode, and a second insulating layer is arranged between the one of the pixel electrode and the second common electrode close to the first common electrode and the first common electrode; wherein the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

10. A display terminal, characterized by The display panel comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate, one of the sub-pixels comprising: a first common electrode arranged on one side of the substrate; a pixel electrode and a second common electrode arranged in layers, the pixel electrode and the second common electrode are both arranged on the side of the first common electrode away from the substrate, the pixel electrode comprises a plurality of pixel branch electrodes arranged at intervals, and the second common electrode comprises a plurality of common branch electrodes arranged at intervals; wherein the orthogonal projection of the pixel branch electrode on the substrate does not overlap with the orthogonal projection of the common branch electrode on the substrate, and the orthogonal projection of the pixel branch electrode on the substrate has an overlapping part with the orthogonal projection of the first common electrode on the substrate. The second common electrode is arranged on the side of the pixel electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is smaller than the width of the pixel electrode. The second common electrode is arranged on the side of the pixel electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is greater than the width of the pixel electrode. The pixel electrode is arranged on the side of the second common electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is smaller than the width of the pixel electrode. The pixel electrode is arranged on the side of the second common electrode away from the substrate, and in the arrangement direction of the two adjacent pixel branch electrodes, the width of the first common electrode is greater than the width of the pixel electrode. The width of the pixel branch electrode is 1.0-3.0 microns, and the distance between the two adjacent pixel branch electrodes is 3.0-7.0 microns. The width of the common branch electrode is 1.0-3.0 microns, and the distance between the two adjacent common branch electrodes is 3.0-7.0 microns. The distance between the orthogonal projection of the pixel branch electrode on the substrate and the orthogonal projection of the adjacent common branch electrode on the substrate is 0-2.0 microns. A first insulating layer is arranged between the pixel electrode and the second common electrode, and a second insulating layer is arranged between the one of the pixel electrode and the second common electrode close to the first common electrode and the first common electrode; wherein the thickness of the first insulating layer is smaller than the thickness of the second insulating layer. The display panel comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate, one of the sub-pixels comprising: a first common electrode arranged on one side of the substrate; a pixel electrode and a second common electrode arranged in layers, the pixel electrode and the second common electrode are both arranged on the side of the first common electrode away from the substrate, the pixel electrode comprises a plurality of pixel branch electrodes arranged at intervals, and the second common electrode comprises a plurality of common branch electrodes arranged at intervals; wherein the orthogonal projection of the pixel branch electrode on the substrate does not overlap with the orthogonal projection of the common branch electrode on the substrate, and the orthogonal projection of the pixel branch electrode on the substrate has an overlapping part with the orthogonal projection of the first common electrode on the substrate.

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