Hardware reset circuit for system anomaly detection

Abstract

According to the hardware reset circuit for system abnormity detection provided by the utility model, the working voltage output by the control module is subjected to two-stage signal processing of the first signal receiving module and the second signal receiving module, and is combined with superposition control of external trigger signals, so that accurate detection and timely reset of system abnormity are realized, and the problem of false triggering is avoided; besides, the external trigger signal is generated when the terminal equipment is charged, the charging process is combined with a system reset trigger mechanism, when the system crash abnormity is detected, the system reset can be quickly and automatically triggered only by charging the equipment, and the user operation process is simplified; furthermore, a system power supply control module is adopted to automatically execute reset operation, manual intervention is not needed, the automation degree of exception handling is improved, and the circuit is simple in structure, convenient to maintain and high in practical value.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic product technical field, especially a kind of hardware reset circuit of system abnormality detection. BACKGROUND

[0002] With the design trend of electronic product to the direction of simple and integrated, product generally adopts non-detachable battery design, and maximum limit reduces external physical button and interface, usually only retains necessary charging interface.This design trend although improves the appearance and protection performance of product, but also brings the problem that reset operation is difficult to realize when system is abnormal.

[0003] Traditional reset scheme, such as setting physical button, reserving reset hole or charging trigger reset, either affects product appearance integrity, or affects normal use experience of user.Therefore, how to provide reliable system reset mechanism while ensuring high simple appearance of product becomes technical problem to be solved in modern electronic product design. UTILITY MODEL CONTENTS

[0004] The utility model provides a kind of hardware reset circuit of system abnormality detection, realizes the fast and automatic reset of triggering system.

[0005] The utility model discloses a kind of hardware reset circuit of system abnormality detection, comprising:

[0006] Control module, according to the size of system power supply voltage Output operating voltage VDD_BUCK_1PB to the first signal receiving module;

[0007] First signal receiving module, according to the voltage value of the operating voltage VDD_BUCK_1PB Output first control signal to the second signal receiving module;

[0008] Second signal receiving module, receives the first control signal and external trigger signal VDD_BUS, and according to the superimposed signal of the first control signal and the external trigger signal VDD_BUS Output second control signal VDD_RST;

[0009] System power supply control module, according to the size of the second control signal VDD_RST Control system power supply reset or continuous work.

[0010] Further, the first signal receiving module includes first NMOS tube Q1, the gate of the first NMOS tube Q1 receives the operating voltage VDD_BUCK_1PB, the drain of the first NMOS tube Q1 Output the first control signal to the second signal receiving module, the source of the first NMOS tube Q1 is grounded.

[0011] Further, the first signal receiving module further comprises a first resistor R1, a second resistor R2 and a third resistor R3, the gate of the first NMOS tube Q1 is grounded through the first resistor R1, and the gate of the first NMOS tube Q1 is also connected to the working voltage VDD_BUCK_1PB through the second resistor R2; and the drain of the first NMOS tube Q1 further outputs the first control signal to the second signal receiving module through the third resistor R3.

[0012] Further, the second signal receiving module comprises a second NMOS tube Q2, the gate of the second NMOS tube Q2 receives the external trigger signal VDD_BUS and the first control signal, the source of the second NMOS tube Q2 is grounded, and the drain of the second NMOS tube Q2 outputs a second control signal VDD_RST.

[0013] Further, the second signal receiving module further comprises a fourth resistor R4 and a fifth resistor R5.

[0014] The gate of the second NMOS tube Q2 is connected to the external trigger signal VDD_BUS through the fourth resistor R4.

[0015] The drain of the second NMOS tube Q2 is connected to the input end of the system power control module through the fifth resistor R5.

[0016] Further, the system power control module is an LDO.

[0017] The second control signal VDD_RST is connected to the enable end EN of the control chip in the LDO.

[0018] Further, the control module is an MCU.

[0019] Compared with the prior art, the utility model has at least the following technical effects:

[0020] The working voltage VDD_BUCK_1PB output by the control module is processed by the double-stage signal receiving module and the second signal receiving module, and the external trigger signal VDD_BUS is superimposed and controlled, so that the system abnormality is accurately detected and reset in time, and the false triggering problem is avoided; in addition, the external trigger signal VDD_BUS is generated when the terminal equipment is charged, and by combining the charging process with the system reset triggering mechanism, when the system abnormality is detected, the device is only charged to automatically trigger the system reset, so that the user operation process is simplified; further, the system power control module is automatically executed to reset, without manual intervention, the automation degree of abnormality processing is improved, and the circuit structure is simple, easy to maintain and has high practical value. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is the working flow schematic view of hardware reset circuit in an embodiment of the utility model;

[0022] Figure 2 It is the structure schematic diagram of hardware reset circuit in an embodiment of the utility model;

[0023] Figure 3 It is the structure schematic diagram of LDO in an embodiment of the utility model;

[0024] Figure 4 It is the voltage signal change diagram of each signal when the system is normal in an embodiment of the utility model;

[0025] Figure 5 It is the voltage signal change diagram of each signal when the system is abnormal in an embodiment of the utility model. DETAILED DESCRIPTION

[0026] The utility model will be described below in conjunction with the schematic diagram of a kind of system abnormality detection hardware reset circuit, wherein the preferred embodiment of the utility model is indicated, it should be understood that the utility model described herein can be modified by the person skilled in the art, and still realize the advantageous effect of the utility model. Therefore, the following description should be understood as the extensive knowledge of the person skilled in the art, and not as the limitation of the utility model.

[0027] The utility model is described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the utility model will be more apparent according to the following description. It should be noted that the drawings are all very simplified and all use non-precise scale, only to facilitate, clearly assist the purpose of explaining the embodiment of the utility model.

[0028] Please refer to Figure 1 The embodiment discloses a kind of system abnormality detection hardware reset circuit, comprising: control module, first signal receiving module, second signal receiving module and system power supply control module.

[0029] Specifically, control module, according to the size of system power voltage Output working voltage VDD_BUCK_1PB to the first signal receiving module;First signal receiving module, according to the voltage value of the working voltage VDD_BUCK_1PB Output first control signal to the second signal receiving module;Second signal receiving module, receives the first control signal and external trigger signal VDD_BUS, and according to the superposition signal of the first control signal and the external trigger signal VDD_BUS Output second control signal VDD_RST;System power supply control module, according to the voltage value of the second control signal VDD_RST Control system power supply reset or continuous work.

[0030] In the embodiment, the hardware reset circuit for system abnormality detection is applicable to terminal devices such as mobile phones, tablet computers and notebook computers.

[0031] Further, in the embodiment, the external trigger signal is a voltage generated when the terminal device is charging, and preferably, the charging mode of the terminal device is the suction charging.

[0032] In the embodiment, through the double-stage signal processing of the working voltage VDD_BUCK_1PB output by the control module via the first signal receiving module and the second signal receiving module, combined with the superposition control of the external trigger signal VDD_BUS, the accurate detection and timely reset of the system abnormality are realized, and the false triggering problem is avoided. In addition, the external trigger signal VDD_BUS can be generated when the terminal device is suction charging. By combining the charging process with the system reset triggering mechanism, when the system crash abnormality is detected, the device only needs to be charged to automatically trigger the system reset, which simplifies the user operation process. Further, the system power control module is automatically executed to reset, without manual intervention, which improves the automation degree of abnormality processing, and the circuit structure is simple and easy to maintain, and has high practical value.

[0033] In the embodiment, when the first control signal is low and the external trigger signal VDD_BUS is high, the second control signal VDD_RST is high, so as to realize the control reset. When the first control signal is low, the second control signal VDD_RST is low, so as not to control the system power control module power reset.

[0034] Please refer to Figure 2 , the circuit for realizing the above technical effects is as follows:

[0035] Specifically, the first signal receiving module includes a first NMOS tube Q1, a first resistor R1, a second resistor R2 and a third resistor R3. The gate of the first NMOS tube Q1 is grounded through the first resistor R1, and the gate of the first NMOS tube Q1 is also connected to the working voltage VDD_BUCK_1PB through the second resistor R2. The drain of the first NMOS tube Q1 also outputs the first control signal to the second signal receiving module through the third resistor R3.

[0036] Further specifically, the second signal receiving module comprises a second NMOS transistor Q2, a fourth resistor R4 and a fifth resistor R5. The gate of the second NMOS transistor Q2 is connected to an external trigger signal VDD_BUS through the fourth resistor R4, and the gate also receives a first control signal from the first signal receiving module. The source of the second NMOS transistor Q2 is grounded. The drain of the second NMOS transistor Q2 is connected to an input end of the system power supply control module through the fifth resistor R5, and outputs a second control signal VDD_RST.

[0037] In the embodiment, when the system is normally working, the working voltage VDD_BUCK_1PB output by the control module is input through the gate of the first NMOS transistor Q1. Due to the grounding effect of the first resistor R1, the gate-source voltage of the first NMOS transistor Q1 is maintained within the normal working range. The drain of the first NMOS transistor Q1 is connected to the working voltage VDD_BUCK_1PB through the second resistor R2, forming a stable first control signal output. At this time, the first control signal is maintained at a high level.

[0038] When the system is abnormal, the working voltage VDD_BUCK_1PB output by the control module is reduced, causing the gate-source voltage of the first NMOS transistor Q1 to drop, and the first NMOS transistor Q1 gradually turns off, and the first control signal output by the drain of the first NMOS transistor Q1 is lowered. At the same time, when the device is charging, an external trigger signal VDD_BUS is generated, which is input to the gate of the second NMOS transistor Q2 through the fourth resistor R4. Due to the superposition effect of the first control signal and the external trigger signal VDD_BUS, the gate-source voltage of the second NMOS transistor Q2 changes, thereby changing the on-off state of the second NMOS transistor Q2. The drain of the second NMOS transistor Q2 outputs a high-level second control signal VDD_RST to the system power supply control module through the fifth resistor R5. When the second NMOS transistor Q2 is turned off, the second control signal VDD_RST becomes low, triggering the system power supply to reset, thereby realizing system reset.

[0039] Further, in the embodiment, the first resistor R1 functions as a gate pull-down resistor of the first NMOS tube Q1, connects the gate to the ground, plays a role in stabilizing the gate potential, prevents the gate voltage from drifting, ensures that the first NMOS tube Q1 is in a controllable state when there is no control signal input, and also plays a role in protecting the gate. The second resistor R2 connects the working voltage VDD_BUCK_1PB and the gate of the first NMOS tube Q1, functions as an input current-limiting resistor, and performs preliminary voltage division on the input working voltage VDD_BUCK_1PB to protect the gate from overvoltage damage. The third resistor R3 functions as a drain load resistor of the first NMOS tube Q1 and is used to connect the drain output signal of the first NMOS tube Q1 to the second signal receiving module. When the first NMOS tube Q1 is turned on or turned off, the voltage drop change generated by the resistor forms the high and low levels of the first control signal, and also plays a role in current-limiting protection. The fourth resistor R4 functions as a gate current-limiting resistor of the second NMOS tube Q2 and connects the external trigger signal VDD_BUS and the gate of the second NMOS tube Q2. The resistor can limit the current entering the gate and also performs preliminary voltage division on the external trigger signal VDD_BUS to protect the gate of the second NMOS tube Q2 from overvoltage damage. The fifth resistor R5 functions as a drain pull-up resistor of the second NMOS tube Q2 and connects the drain of the second NMOS tube Q2 to the system power control module. The resistor can form a stable output level between the on and off states of the second NMOS tube Q2, provide a reliable control signal for the system power control module, and also play a role in current-limiting protection.

[0040] In a specific embodiment, the resistance value of the first resistor R1 is 100K, and the resistance value of the second resistor R2 is 70K. Those skilled in the art can select the resistance values of the first resistor R1 and the second resistor R2 according to actual conditions. Similarly, the resistance values of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can also be selected.

[0041] In a specific embodiment, the supply voltage has a magnitude of 0V-4V, for example, 0V or 3V. The supply voltage is the voltage output by the system power control module. Generally, the supply voltage generated when the system is in a normal working state is higher, and the supply voltage generated when the system is in a dead state is lower. For example, when the system is in a dead state, the supply voltage has a magnitude of 0V, and when the system is in a normal working state, the supply voltage has a magnitude of 3.3V.

[0042] In another embodiment, the working voltage VDD_BUCK_1PB ranges from 0V to 3V, for example, 0V, 1.1V and 1.8V. Generally, the working voltage VDD_BUCK_1PB output by the MCU is higher when the system is in normal working state, and the working voltage VDD_BUCK_1PB output by the MCU is lower when the system is in dead state. For example, when the system is in normal working state, the working voltage VDD_BUCK_1PB is maintained at 1.8V. When the system is in dead state, the working voltage VDD_BUCK_1PB is 0V or 1.1V.

[0043] In another embodiment, the external trigger signal VDD_BUS ranges from 0V to 6V, for example, 0V and 5V. The external trigger signal VDD_BUS is generated after the terminal device is charged. For example, when the terminal device is not attached to the charging device, the external trigger signal VDD_BUS is 0V, and when the terminal device is attached, the external trigger signal VDD_BUS is 5V.

[0044] In one embodiment, the hardware reset circuit for system anomaly detection is an LDO (low dropout linear regulator). Please refer to Figure 3 The specific connection relationship of the LDO circuit is as follows: between the input end VIN of the LDO control chip and the power supply end VSYS, and between the power supply end VDD3V3 (3.3V voltage) and the power supply end VSYS, a fifth resistor R483 and a sixth resistor R482 are connected to form a voltage dividing network. The output end VOUT of the LDO is connected to the power supply end VDD3V3; the output end of the LDO is configured with a first capacitor C479 and a second capacitor C478 as filter capacitors; the enable end EN of the LDO is connected to the second control signal VDD_RST, in addition, the EN end is pulled up through a seventh resistor R484, and at the same time, a third capacitor C477 and a fourth capacitor C480 are configured as decoupling capacitors.

[0045] It can be seen that in this embodiment, the reset design takes the attachment of the terminal device for charging as the reset condition. The attachment of the terminal device is one of the use scenarios. When the system appears abnormal condition, the attachment of the terminal device will disconnect the power supply of the system, and when the terminal device is separated, the power supply of the system will be turned on again. Thus, a hardware reset action is completed. When the system is normal, the attachment of the terminal device will not trigger the power down of the system, and will not cause reset. The stable operation of the system is ensured. This design ingeniously combines the charging and reset functions, and improves the reliability and user experience of the system.

[0046] In one embodiment, please refer to Figure 4When the system is in normal working state, the control module outputs 2V working voltage VDD_BUCK_1PB to the gate of the first NMOS Q1. Since the gate-source voltage of the first NMOS Q1 is greater than the threshold voltage, the first NMOS Q1 is in the on state; the first NMOS Q1 drain outputs a high level of the first control signal to the gate of the second NMOS Q2 through the drain load resistor; at this time, even if there is a 5V external trigger signal VDD_BUS input to the gate of the second NMOS Q2 through the gate current limiting resistor, due to the high level control signal output by the first NMOS Q1, the second NMOS Q2 remains off state. When the second NMOS Q2 is off, its drain outputs a high level of the second control signal VDD_RST through the pull-up resistor, maintaining normal power supply of the system. When the second NMOS Q2 is off, its drain outputs a high level of the second control signal VDD_RST through R4, maintaining normal power supply of the system.

[0047] In another embodiment, please refer to Figure 5 When the system is abnormal, the MCU detects the dead state according to the size change of the system power supply voltage, and the output working voltage VDD_BUCK_1PB decreases from 2V to close to 0V or to 1.1V. At the same time, if the device is connected to the charger at this time, a 5V external trigger signal VDD_BUS is generated. In addition, after the double-stage NMOS processing of the first signal receiving module and the second signal receiving module, the VDD_RST signal is reduced. The VDD_RST signal controls the LDO output through the EN pin of the LDO. When the EN pin level is reduced, the LDO output is off. The LDO output off leads to the interruption of system power supply, and the system power supply such as VDD_BUCK_1PB is reduced. After a short off time, the system is powered on again, and each power supply is restored to the normal working level in turn.

[0048] Various modifications and variations without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. A hardware reset circuit for system anomaly detection, the hardware reset circuit comprising: The system abnormality detection hardware reset circuit comprises: a control module, which outputs a working voltage VDD_BUCK_1PB to a first signal receiving module according to the size of a system power supply voltage; the first signal receiving module outputs a first control signal to a second signal receiving module according to the voltage value of the working voltage VDD_BUCK_1PB; the second signal receiving module receives the first control signal and an external trigger signal VDD_BUS, and outputs a second control signal VDD_RST according to the superimposed signal of the first control signal and the external trigger signal VDD_BUS; a system power supply control module, which controls the reset or continuous operation of the system power supply according to the size of the second control signal VDD_RST; wherein the first signal receiving module comprises a first NMOS tube Q1, the gate of the first NMOS tube Q1 receives the working voltage VDD_BUCK_1PB, the drain of the first NMOS tube Q1 outputs the first control signal to the second signal receiving module, and the source of the first NMOS tube Q1 is grounded; the second signal receiving module comprises a second NMOS tube Q2, the gate of the second NMOS tube Q2 receives the external trigger signal VDD_BUS and the first control signal, the gate of the second NMOS tube Q2 is grounded, and the drain of the second NMOS tube Q2 outputs the second control signal VDD_RST.

2. The system abnormality detection hardware reset circuit of claim 1, wherein the first signal receiving module further comprises a first resistor R1, a second resistor R2 and a third resistor R3, the gate of the first NMOS tube Q1 is grounded through the first resistor R1, the gate of the first NMOS tube Q1 is also connected to the working voltage VDD_BUCK_1PB through the second resistor R2, and the drain of the first NMOS tube Q1 outputs the first control signal to the second signal receiving module through the third resistor R3.

3. The system abnormality detection hardware reset circuit of claim 1, wherein the second signal receiving module further comprises a fourth resistor R4 and a fifth resistor R5; the gate of the second NMOS tube Q2 is connected to the external trigger signal VDD_BUS through the fourth resistor R4; the drain of the second NMOS tube Q2 is connected to the input end of the system power supply control module through the fifth resistor R5.

4. The system abnormality detection hardware reset circuit of claim 1, wherein the system power supply control module is an LDO; the second control signal VDD_RST is connected to the enable end EN of the control chip in the LDO.

5. The hardware reset circuit for system anomaly detection of claim 1, wherein, the control module is an MCU.

6. The hardware reset circuit for system anomaly detection of claim 1, wherein, the working voltage VDD_BUCK_1PB is 0V-3V.

7. The hardware reset circuit for system anomaly detection of claim 1, wherein, the external trigger signal VDD_BUS is 0V-6V.

8. The hardware reset circuit for system anomaly detection of claim 1, wherein, the size of the power supply voltage is 0V-4V.

Images