Low-power-consumption anti-reverse-connection circuit and low-power-consumption anti-reverse-connection chip
By combining components such as switching modules, capacitors, and diodes, and utilizing the parasitic diodes of NMOS transistors and pulse signal control, a low-power reverse connection protection circuit was achieved, which features low power consumption when the power supply is connected in the correct direction and protection against reverse connection. This solves the problems of complex circuit structure and high cost in existing technologies.
Patent Information
- Application Number
- CN202520351063.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-02-28
AI Technical Summary
Existing technologies cannot design low-power reverse connection protection circuits that are simple in structure and low in cost. In particular, reverse connection protection circuits based on MOSFETs have problems such as high cost or complex circuit structure.
By employing a combination of a switching module, a first capacitor, a first diode, a first resistor, a second diode, and a pull-down module, and utilizing the parasitic diode of the NMOS transistor and pulse signals to control the conduction and disconnection of the circuit, a low-power reverse connection protection function is achieved.
It achieves low-power operation when the power supply is connected in the correct direction and prevents the circuit from operating when the power supply is connected in the reverse direction, thereby reducing the cost and power consumption of the circuit, and the structure is simple.
Smart Images
Figure CN223858836U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a circuit field especially is related to a low -power consumption anti -reversal circuit and low -power consumption anti -reversal chip. BACKGROUND
[0002] In the circuit field, on one hand, power reverse connection is a kind of more serious error operation, not only can cause equipment damage, there is certain security risk, therefore through anti -reversal protection circuit, can effectively prevent the equipment damage caused by wiring error, and improve the reliability and service life of equipment, on the other hand, in the process of power positive connection, power supply can continuously discharge in circuit, cause circuit normal operation when from power supply place cannot obtain sufficient electric quantity, therefore anti -reversal circuit also needs to be low -power consumption circuit to improve the reliability and service life of equipment when positive connection.
[0003] The existing power anti-reversal technology mainly includes: using a diode to realize power anti-reversal, using a rectifier bridge circuit to realize power anti-reversal, and using a MOS tube to realize power anti-reversal. Among them, the anti-reversal circuit based on diode has the advantages of simplicity, practicality and low cost, but has the disadvantage of inapplicability to low-voltage circuits; the anti-reversal circuit based on rectifier bridge has the advantage of effectively preventing reverse connection, but has the disadvantage of high power consumption; the anti-reversal circuit based on MOS tube can effectively overcome the disadvantages of the anti-reversal circuit based on diode and the anti-reversal circuit based on rectifier bridge, and is the most widely used anti-reversal circuit at present.
[0004] The anti-reversal circuit based on MOS tube can be divided into PMOS tube anti-reversal circuit and NMOS tube anti-reversal circuit, but the PMOS tube anti-reversal circuit still has the problem of high cost, and the NMOS tube anti-reversal circuit also has the problem of complex circuit structure; and the above two anti-reversal circuits cannot meet the low-power consumption requirement when the circuit is connected in positive.
[0005] Therefore, how to design a low-power consumption anti-reversal circuit with simple circuit structure and low cost has become one of the problems to be solved by the technical personnel in the field.
[0006] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical scheme of the utility model, and to facilitate the understanding of the technical personnel in the field. The above technical scheme cannot be considered as known to the technical personnel in the field only because it is described in the background art section of the utility model. CONTENT OF THE UTILITY MODEL
[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the utility model is to provide a low-power consumption anti-reversal circuit and a low-power consumption anti-reversal chip, to solve the problem that a low-power consumption anti-reversal circuit with simple circuit structure and low cost cannot be designed in the prior art.
[0008] To achieve the above object and other related objects, the utility model provides a low -power consumption prevents the circuit of reverse connection, low -power consumption prevents the circuit of reverse connection at least includes: switch module, first electric capacity, first diode, first resistance, second diode and pull -down module, the first end of switch module connects the first end of power, and the second end connects the power end of load, the ground end of load connects the second end of power, the first end of first resistance connects the cathode of first diode, and the second end connects the control end of switch module, the anode of first diode is applied drive voltage, and the cathode connects the second pole plate of first electric capacity, the first pole plate of first electric capacity connects the cathode of second diode, the anode of second diode connects the control end of switch module, the first end of pull -down module connects the first pole plate of first electric capacity, and the second end connects the second end of power, and the control end is applied pulse signal.
[0009] Optionally, the switch module includes a first NMOS tube, a second NMOS tube and a second capacitor; the source of the first NMOS tube is connected to the source of the second NMOS tube, the drain of the first NMOS tube is used as the first end of the switch module, the drain of the second NMOS tube is used as the second end of the switch module, the gate of the first NMOS tube and the gate of the second NMOS tube are both the control end of the switch module; the first pole plate of the second capacitor is connected to the gate of the first NMOS tube, and the second pole plate is connected to the source of the first NMOS tube.
[0010] More optionally, the switch module further includes a second resistor, and the second resistor is connected in parallel with the second capacitor.
[0011] Optionally, the low-power consumption prevents the circuit of reverse connection further includes a third resistor, and the third resistor is connected between the second diode and the first electric capacity.
[0012] Optionally, the pull-down module includes a pull-down tube.
[0013] More optionally, the pull-down tube is an NPN type triode, the collector of the NPN type triode is used as the first end of the pull-down module, the emitter is used as the second end of the pull-down module, and the base is used as the control end of the pull-down module; or the pull-down tube is a PNP type triode, the emitter of the PNP type triode is used as the first end of the pull-down module, the collector is used as the second end of the pull-down module, and the base is used as the control end of the pull-down module.
[0014] More optionally, the pull-down tube is an NMOS tube, a drain of the NMOS tube is used as the first end of the pull-down module, a source is used as the second end of the pull-down module, and a gate is used as the control end of the pull-down module; or the pull-down tube is a PMOS tube, a source of the PMOS tube is used as the first end of the pull-down module, a drain is used as the second end of the pull-down module, and a gate is used as the control end of the pull-down module.
[0015] More optionally, the pull-down module further comprises a fourth resistor and a fifth resistor; the fourth resistor is connected between the pulse signal and the control end of the pull-down module; one end of the fifth resistor is connected to the control end of the pull-down module, and the other end is connected to the second end of the power supply.
[0016] To achieve the above object and other related objects, the utility model also provides a low-power anti-reverse connection chip, the low-power anti-reverse connection chip includes the low-power anti-reverse connection circuit.
[0017] As described above, the low-power anti-reverse connection circuit and the low-power anti-reverse connection chip have the following beneficial effects:
[0018] 1, the utility model in power supply end through the first capacitor and the second capacitor control two NMOS tube's gate source voltage difference, therefore the utility model has realized under the condition of ground wire integrity uses NMOS tube to build the purpose of anti-reverse connection circuit, has reduced the cost and power consumption of circuit.
[0019] 2, the utility model sets up two NMOS tubes of source electrode connection, utilizes the parasitic diode in NMOS tube, the utility model can always be in the non-conducting state under the condition that the circuit does not work, realizes the function of low power consumption.
[0020] 3, the utility model sets up the pull-down module connected with the first capacitor and the second capacitor, has realized the purpose of controlling circuit according to the frequency of pulse signal, therefore the utility model can control the time of low-power anti-reverse connection circuit conduction or disconnection. ACCURACY OF DRAWINGS
[0021] Figure 1 It shows a structure schematic diagram of a low-power anti-reverse connection circuit.
[0022] Figure 2 It shows a structure schematic diagram of another low-power anti-reverse connection circuit.
[0023] Figure 3 It shows a structure schematic diagram of a third low-power anti-reverse connection circuit.
[0024] Figure 4 It shows a structure schematic diagram of a low-power anti-reverse connection circuit in the utility model.
[0025] Component designation explanation
[0026] 1 Switch Module
[0027] 1a First NMOS transistor
[0028] 1b Second NMOS transistor
[0029] 1c Second capacitor
[0030] 1d Second resistor
[0031] 2 First capacitor
[0032] 3 First Diode
[0033] 4 First resistor
[0034] 5. Second Diode
[0035] 6. Drop-down module
[0036] 6a pull-down tube
[0037] 6b Fourth resistor
[0038] 6c Fifth resistor
[0039] 7. Third resistor Detailed Implementation
[0040] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0041] Please see Figures 1-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Therefore, the illustrations only show the components related to this utility model and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0042] like Figure 1 The diagram shows a low-power reverse polarity protection circuit based on PMOS transistors. The main principle is as follows: two back-to-back PMOS transistors Q1 and Q2 are used at the power supply end. The conduction and cutoff of Q1 and Q2 are controlled by transistor Q3, ensuring that the power supply and load only operate when the power supply is connected in the correct direction and there is no low-power requirement. Resistors R1, R2, and R3 work in conjunction with Q1, Q2, and Q3. However, if... Figure 1The circuit shown has the problem of high power consumption and cost caused by PMOS tubes (the use of PMOS tubes is not as widespread as NMOS tubes, so the cost is higher; even at the same cost, the internal resistance of PMOS tubes is larger, so the power consumption is higher). As shown in Figure 2 The circuit shown is a low-power anti-reverse connection circuit implemented based on NMOS tubes, and the main principle is: two back-to-back NMOS tubes Q4 and Q5 are used at the ground end, and the conduction and turn-off of Q1 and Q2 are controlled through control of the transistor Q6, so that the power supply and the load only work when the power supply is connected in the correct direction and there is no low-power consumption demand, wherein resistors R4, R5 and R6 cooperate with Q4, Q5 and Q6 to work, but as shown in Figure 2 The circuit shown reduces the integrity of the ground and needs to be isolated from external communication. As shown in Figure 3 The circuit shown is another low-power anti-reverse connection circuit implemented based on NMOS tubes, and the main principle is: two back-to-back NMOS tubes Q7 and Q8 are used at the power supply end, and the conduction and turn-off of Q7 and Q8 are controlled through control of the pump power supply chip S1, so that the power supply and the load only work when the power supply is connected in the correct direction and there is no low-power consumption demand, wherein resistors R7 and R8 cooperate with Q7 and Q8 to work, but as shown in Figure 3 The circuit shown has the problem of increased cost and complex structure caused by the pump power supply chip S1. In summary, the circuits shown in Figure 1 、 Figure 2 and Figure 3 still have the problem of high circuit cost or complex circuit structure, and in the context of large current use, the present embodiment provides a low-power anti-reverse connection circuit with low circuit cost and simple circuit structure, and the specific implementation scheme is as follows:
[0043] Embodiment One
[0044] As shown in Figure 4 The present embodiment provides a low-power anti-reverse connection circuit, which comprises: a switch module 1, a first capacitor 2, a first diode 3, a first resistor 4, a second diode 5 and a pull-down module 6.
[0045] As shown in Figure 4 The first end of the switch module 1 is connected to the first end of the power supply, and the second end is connected to the power supply end of the load; the ground end of the load is connected to the second end of the power supply.
[0046] Specifically, in the embodiment, the switch module 1 can realize the function of closing when the power is connected in positive and realize the function of opening when the power is connected in reverse. Further, the switch module 1 comprises a first NMOS tube 1a, a second NMOS tube 1b and a second capacitor 1c; the source of the first NMOS tube 1a is connected with the source of the second NMOS tube 1b, the drain of the first NMOS tube 1a is the first end of the switch module 1, the drain of the second NMOS tube 1b is the second end of the switch module 1, the gate of the first NMOS tube 1a and the gate of the second NMOS tube 1b together constitute the control end of the switch module 1; the first plate of the second capacitor 1c is connected with the gate of the first NMOS tube 1a, and the second plate is connected with the source of the first NMOS tube 1a. Further, the purpose of using the second capacitor 1c is to maintain the gate voltage of the two NMOS tubes at high level when the first capacitor 2 is charging. Further, the switch module 1 further comprises a second resistor 1d which is connected in parallel with the second capacitor 1c, and the purpose of using the second resistor 1d is to ensure that the voltage between the gate and the source of the two NMOS tubes is not suspended.
[0047] As shown in Figure 4 , the first end of the first resistor is connected with the cathode of the first diode, and the second end is connected with the control end of the switch module; the anode of the first diode is applied with a driving voltage, and the cathode is connected with the second plate of the first capacitor; the first plate of the first capacitor is connected with the cathode of the second diode; the anode of the second diode is connected with the control end of the switch module.
[0048] Specifically, in the embodiment, when the power is connected in positive, and after the first NMOS tube is turned on, the gate voltage of the first NMOS tube will be higher than the driving voltage (the driving voltage is set according to the specification of the NMOS tube), so the purpose of setting the first diode 3 is to prevent the current from flowing back into the driving voltage when the NMOS tube is turned on. Further, the purpose of setting the first resistor 4 is to adjust the charging time of each capacitor in the low-power anti-reverse connection circuit and limit the current in each capacitor and NMOS tube. Further, the purpose of setting the second diode 5 is to prevent the positive pole of the power supply, the pull-down module 6 and the negative pole of the power supply from forming a path when the power supply is connected in reverse, that is, to prevent the pull-down module 6 from being damaged when the power supply is connected in reverse. Further, the low-power anti-reverse connection circuit further comprises a third resistor 7 connected between the second diode 5 and the first capacitor 2, and the purpose of setting the third resistor 7 is to limit the current flowing through the pull-down module 6.
[0049] As shown in Figure 4 , the first end of the pull-down module 6 is connected with the first plate of the first capacitor 2, the second end is connected with the second end of the power supply, and the control end is applied with a pulse signal.
[0050] Specifically, in this embodiment, the pull-down module 6 includes a pull-down transistor 6a. Further, the pull-down transistor 6a is an NPN transistor, with its collector serving as the first terminal of the pull-down module 6, its emitter serving as the second terminal, and its base serving as the control terminal. Even further, the pull-down transistor 6a is a PNP transistor, with its emitter serving as the first terminal, its collector serving as the first terminal, and its base serving as the control terminal. Even further, the pull-down transistor 6a is an NMOS transistor, with its drain serving as the first terminal, its source serving as the second terminal, and its gate serving as the control terminal. Even further, the pull-down transistor 6a is a PMOS transistor, with its source serving as the first terminal, its drain serving as the second terminal, and its gate serving as the control terminal. Furthermore, the pull-down module 6 also includes a fourth resistor 6b and a fifth resistor 6c; the fourth resistor 6b is connected between the pulse signal and the control terminal of the pull-down module 6; one end of the fifth resistor 6c is connected to the control terminal of the pull-down module 6, and the other end is connected to the second terminal of the power supply; the fourth resistor 6b is set to limit the base current of the pull-down transistor 6a, and the fifth resistor 6c is set to stabilize the static operating point of the pull-down transistor 6a.
[0051] Specifically, in this embodiment, the pulse signal applied to the control terminal of the pull-down module 6 can control the pull-down module 6 to be turned on or off. Further, when the pull-down transistor 6a of the pull-down module 6 is an NPN transistor or an NMOS transistor, the pull-down module 6 is turned on when the pulse signal is high and off when the pulse signal is low; when the pull-down transistor 6a of the pull-down module 6 is a PNP transistor or a PMOS transistor, the pull-down module 6 is turned on when the pulse signal is low and off when the pulse signal is high. As an example, such as... Figure 4 As shown, when the power supply is positive, the pulse signal is high, the pull-down module 6 is turned on, and the driving voltage charges the first capacitor 2. When the pulse signal changes to low, the pull-down module 6 is turned off, and the first capacitor 2, the first resistor 4, the second capacitor 1c, the first NMOS transistor 1a, and the second diode 5 form an RC charging circuit. Therefore, in this example, the frequency of the pulse signal can be set according to the resistance value of the first resistor 4 and the capacitance value of the second capacitor 1c. In practical applications, the frequency of the pulse signal can be set as needed, and is not limited to this embodiment.
[0052] It should be noted that when the power supply is connected in positive (i.e. the first end of the power supply is positive, the second end of the power supply is negative, the negative pole of the power supply is grounded, and the second end of the pull-down module and the ground end of the load are connected to the negative pole of the power supply), first, the pulse signal makes the pull-down module 6 conductive, and because the anode of the first diode 2 is applied with a driving voltage, the first capacitor 2 starts to charge, at this time, the first plate of the first capacitor is grounded, and the potential of the second plate is V1; second, the pulse signal makes the pull-down module 6 disconnected, because of the existence of the parasitic diode, a loop is formed between the first capacitor, the first resistor, the first NMOS tube and the second diode, at this time, the potential of the first plate of the first capacitor is lifted to BAT, and the potential of the second plate is lifted to BAT+V1, that is, the gate-source voltage difference of the first NMOS tube and the second NMOS tube also reaches the conduction condition, the switch module 1 is turned on, and at the same time, the first capacitor 2 also charges the second capacitor 1c, so that the second capacitor 1c ensures that the first NMOS tube and the second NMOS tube can continue to conduct when the first capacitor is charging, and the switch module 1 can be continuously turned on; finally, the pulse signal makes the pull-down module 6 conductive again, and the driving voltage charges the first capacitor 2 again, so that the low-power anti-reverse connection circuit can continuously run. In actual application, the devices in the switch module 1 and the pull-down module 6 are set as needed, which is not limited to the embodiment.
[0053] It should be further explained that when the power supply is connected in reverse (i.e. the first end of the power supply is negative, the second end of the power supply is positive, the negative pole of the power supply is grounded, and the second end of the pull-down module and the ground end of the load are connected to the positive pole of the power supply), because the driving voltage disappears (the driving voltage comes from the power supply when connected in positive), and the pull-down module cannot be turned on due to reverse bias, the first capacitor and the second capacitor cannot be charged, so that the gate-source voltage difference of the first NMOS tube and the second NMOS tube cannot reach the conduction condition, and the circuit cannot work normally, so that the embodiment realizes the purpose of power supply anti-reverse connection. In actual application, the devices in the switch module 1 and the pull-down module 6 are set as needed, which is not limited to the embodiment.
[0054] It should be further explained that when the pulse signal has not been applied to the control end of the pull-down module, whether the power supply is connected in positive or reverse, the first NMOS tube and the second NMOS tube will not be turned on, and because the parasitic diode is in a reverse bias state, no path will be formed between the positive and negative poles of the power supply, and the power of the power supply can be saved, so that the low-power anti-reverse connection circuit of the utility model can realize the purpose of low power consumption when it does not need to work.
[0055] Embodiment two
[0056] The embodiment provides a low-power anti-reverse connection chip, and the low-power anti-reverse connection chip of the embodiment includes the low-power anti-reverse connection circuit of the embodiment one.
[0057] Specifically, in the embodiment, the low-power anti-reverse connection chip can detect the positive and negative of the power supply during installation, and prevent the chip from burning out, short circuit and other phenomena when the power supply is reversed. Further, the driving voltage can come from a driving circuit in the low-power anti-reverse connection chip, and the driving circuit in the low-power anti-reverse connection chip is powered by the power supply in the positive connection, so the driving voltage will disappear when the power supply is reversed. In actual application, the circuit structure in the low-power anti-reverse connection chip is designed according to actual needs, and is not limited to the embodiment.
[0058] In summary, the low-power anti-reverse connection circuit and the low-power anti-reverse connection chip of the utility model include a switch module, a first capacitor, a first diode, a first resistor, a second diode and a pull-down module. When the power supply is connected in positive, first, the pull-down module is turned on to charge the first capacitor and make the two plates have a potential difference. Second, the pull-down module is disconnected, the potential difference between the plates of the first capacitor becomes the gate-source voltage difference of the NMOS tube, the switch module is turned on, and the second capacitor is also charged. Finally, the pull-down module is turned on again, the first capacitor is charged again, and in the charging process of the first capacitor, the switch module continues to be turned on based on the second capacitor power supply, so the low-power anti-reverse connection circuit can continue to operate. In addition, when the power supply is connected in positive, if the circuit stops working, the switch module will not be turned on, so the utility model can be kept in a low-power state. When the power supply is reversed, the first capacitor and the second capacitor will not be charged, and the switch module cannot be turned on, so the low-power anti-reverse connection circuit cannot operate. In summary, the utility model realizes the anti-reverse connection and low-power function of the power supply. In addition, the utility model has the advantages of low cost and simple structure. Therefore, the utility model effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.
[0059] The above embodiment only illustrates the principle and effect of the utility model, and is not used to limit the utility model. Any person skilled in the art can modify or change the above embodiment without departing from the spirit and scope of the utility model. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the utility model should be covered by the claims of the utility model.
Claims
1. A low power consumption reverse connection prevention circuit, characterized by comprising: The low-power anti-reverse connection circuit at least comprises a switch module, a first capacitor, a first diode, a first resistor, a second diode and a pull-down module. The first end of the switch module is connected to the first end of a power supply, and the second end is connected to the power supply end of a load; the ground end of the load is connected to the second end of the power supply; The first end of the first resistor is connected to the cathode of the first diode, and the second end is connected to the control end of the switch module; the anode of the first diode is applied with a driving voltage, and the cathode is connected to the second plate of the first capacitor; the first plate of the first capacitor is connected to the cathode of the second diode; the anode of the second diode is connected to the control end of the switch module; The first end of the pull-down module is connected to the first plate of the first capacitor, the second end is connected to the second end of the power supply, and the control end is applied with a pulse signal.
2. The low power consumption reverse connection prevention circuit according to claim 1, characterized by: The switch module comprises a first NMOS tube, a second NMOS tube and a second capacitor; The source of the first NMOS tube is connected to the source of the second NMOS tube, the drain of the first NMOS tube serves as the first end of the switch module, the drain of the second NMOS tube serves as the second end of the switch module, and the gate of the first NMOS tube and the gate of the second NMOS tube both serve as the control end of the switch module; The first plate of the second capacitor is connected to the gate of the first NMOS tube, and the second plate is connected to the source of the first NMOS tube.
3. The low power consumption reverse connection prevention circuit according to claim 2, characterized by: The switch module further comprises a second resistor, which is connected in parallel with the second capacitor.
4. The low power consumption reverse connection prevention circuit according to claim 1, characterized by: The low-power anti-reverse connection circuit further comprises a third resistor, which is connected between the second diode and the first capacitor.
5. The low power consumption reverse connection prevention circuit according to claim 1, characterized by: The pull-down module comprises a pull-down tube.
6. The low power consumption reverse connection prevention circuit according to claim 5, characterized by: The pull-down tube is an NPN triode, the collector of the NPN triode serves as the first end of the pull-down module, the emitter serves as the second end of the pull-down module, and the base serves as the control end of the pull-down module; or the pull-down tube is a PNP triode, the emitter of the PNP triode serves as the first end of the pull-down module, the collector serves as the second end of the pull-down module, and the base serves as the control end of the pull-down module.
7. The low power consumption reverse connection prevention circuit according to claim 5, wherein: The pull-down tube is an NMOS tube, the drain of the NMOS tube serves as the first end of the pull-down module, the source serves as the second end of the pull-down module, and the gate serves as the control end of the pull-down module; or the pull-down tube is a PMOS tube, the source of the PMOS tube serves as the first end of the pull-down module, the drain serves as the second end of the pull-down module, and the gate serves as the control end of the pull-down module.
8. The low power consumption reverse connection prevention circuit according to claim 5, characterized by: The pull-down module further comprises a fourth resistor and a fifth resistor; the fourth resistor is connected between the pulse signal and the control end of the pull-down module; one end of the fifth resistor is connected to the control end of the pull-down module, and the other end is connected to the second end of the power supply.
9. A low power consumption reverse connection prevention chip, characterized by, The low-power anti-reverse connection chip comprises the low-power anti-reverse connection circuit according to any one of claims 1-8.