Chip packaging structure and electronic equipment

Abstract

The utility model discloses a chip packaging structure and electronic equipment, and relates to the technical field of semiconductor packaging. The chip packaging structure comprises a substrate, a chip and a cover body, the substrate is provided with a bonding pad, the chip is provided with a functional area and bonding wires located on the periphery of the functional area, the cover body is provided with a groove and via holes located on the periphery of the groove, the chip and the cover body are fixedly connected to form a chip module, and the bonding pad is arranged on the bonding pad. The substrate is provided with a plurality of through holes, the bonding pad is provided with a functional area, the functional area and the groove are correspondingly arranged, the bonding wire is arranged in the through holes in a penetrating mode and extends out of the through holes, the chip module is arranged on the substrate, the bonding wire is electrically connected with the bonding pad, and sealant is arranged between the substrate and the cover body. The chip packaging structure can solve the problem that the welding structure between the chip and the substrate is easy to layer in the traditional chip packaging process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and an electronic device. BACKGROUND

[0002] With the rapid development of the semiconductor industry, surface acoustic wave filters (saw filters) are widely used in receiver front ends and duplexers and receive filters. Generally, the chip of a surface acoustic wave filter (saw filter) is made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) material, uses the piezoelectric properties of piezoelectric materials, and uses input and output transducers to convert an input signal of an electric wave into mechanical energy, which is processed and then converted into an electric signal, to achieve the effect of filtering unnecessary signals and noise and improve reception quality.

[0003] In the conventional technology, to ensure that the functional area of the chip of the surface acoustic wave filter (saw filter) does not contact any substance, i.e. a cavity structure design, the chip of the surface acoustic wave filter (saw filter) usually adopts a flip-chip process, is attached to a substrate, and then a film coating process is used on the surface of the chip to form a space around the chip by using the film, and the bottom of the chip and the surface of the substrate are electrically connected through a soldering structure, which has the problem of easy delamination of the soldering structure. CONTENT OF THE INVENTION

[0004] The present application aims to provide a chip packaging structure and an electronic device, which can solve the problem of easy delamination of the soldering structure between the chip and the substrate in the conventional chip packaging process.

[0005] The embodiments of the present application are implemented as follows:

[0006] In a first aspect, the present application provides a chip packaging structure, which comprises a substrate, a chip and a cover. The substrate is provided with a bonding pad. The chip is provided with a functional area and a wire on the periphery of the functional area. The cover is provided with a groove and a via on the periphery of the groove. The chip and the cover are fixedly connected to form a chip module, and the functional area and the groove are correspondingly arranged. The wire is arranged in the via and extends out of the via. The chip module is arranged on the substrate, and the wire is electrically connected to the bonding pad. The substrate and the cover are provided with a sealing adhesive therebetween. The chip packaging structure can solve the problem of easy delamination of the soldering structure between the chip and the substrate in the conventional chip packaging process.

[0007] As an implementable manner, the bonding pad is further provided with a conductive layer, and the wire is electrically connected to the bonding pad through the conductive layer.

[0008] As an implementation, the projection of the functional area on the substrate is located in the projection range of the groove on the substrate.

[0009] As an implementation, the wires and the vias are both multiple, and the multiple wires and the multiple vias are one-to-one corresponding.

[0010] As an implementation, the multiple wires are uniformly distributed along the periphery of the functional area.

[0011] As an implementation, the material of the wire includes gold, silver, copper or aluminum.

[0012] As an implementation, the shape of the via includes rectangle, circle, sector, ellipse, trapezoid, triangle or polygon.

[0013] As an implementation, a film layer is further included, and the chip and the cover are fixedly connected through the film layer.

[0014] As an implementation, a plastic sealing layer is further arranged on the substrate provided with the chip module.

[0015] The second aspect of the embodiments of the present application provides an electronic device including the chip packaging structure. The chip packaging structure can solve the problem that the welding structure between the chip and the substrate is easy to delaminate in the conventional chip packaging process.

[0016] The beneficial effects of the embodiments of the present application include:

[0017] The chip packaging structure comprises a substrate, a chip and a cover body, the substrate is provided with a bonding pad, the chip is provided with a functional area and a wire which is located at the periphery of the functional area, the cover body is provided with a groove and a via hole which is located at the periphery of the groove, the chip and the cover body are fixedly connected to form a chip module, the functional area is correspondingly arranged with the groove, the wire is arranged in the via hole and extends out of the via hole, the chip module is arranged on the substrate, the wire is electrically connected with the bonding pad, and the sealing glue is arranged between the substrate and the cover body. In the chip packaging structure provided in the application, the chip and the cover body are fixedly connected to form a chip module, the wire on the chip is arranged in the via hole on the cover body and extends out of the via hole, and then the wire is electrically connected with the bonding pad on the substrate. This connection mode changes the traditional welding connection between the chip and the substrate into the connection between the wire and the bonding pad, avoids the direct welding of the chip and the substrate, and fundamentally eliminates the delamination problem caused by the welding of the chip and the substrate. Furthermore, the chip and the cover body are fixedly connected to form a chip module, the functional area is correspondingly arranged with the groove on the cover body, and in the actual use process, even if there is temperature change, since the chip and the cover body form a relatively stable whole, the thermal expansion consistency is relatively good. Compared with the large thermal stress generated due to the difference in the material thermal expansion coefficient when the traditional chip and the substrate are welded, the thermal stress of this structure is less affected, and the delamination possibility is further reduced. In addition, the sealing glue is arranged between the substrate and the cover body. The sealing glue not only can play a sealing role to prevent the impurities such as air, water vapor and dust in the outside from entering the chip packaging interior to affect the performance, but also can buffer the mechanical stress and thermal stress from the outside to a certain extent. When subjected to the stress from the outside, the sealing glue can absorb part of the stress, reduce the direct impact of the stress on the connection parts of the wire and the bonding pad and the connection parts of the chip and the cover body, and thus the risk of delamination or damage of the connection parts is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0019] Figure 1 One of the preparation process schematic diagrams of the chip module provided in the embodiments of the present application;

[0020] Figure 2 The second preparation process schematic diagram of the chip module provided in the embodiments of the present application;

[0021] Figure 3 The third preparation process schematic diagram of the chip module provided in the embodiments of the present application;

[0022] Figure 4A schematic diagram of a preparation process of a chip packaging structure provided by an embodiment of the present application is shown in FIG. 1.

[0023] Figure 5 A schematic diagram of a preparation process of a chip packaging structure provided by an embodiment of the present application is shown in FIG. 2.

[0024] Figure 6 A schematic diagram of a preparation process of a chip packaging structure provided by an embodiment of the present application is shown in FIG. 3.

[0025] Figure 7 A schematic diagram of a preparation process of a chip packaging structure provided by an embodiment of the present application is shown in FIG. 4.

[0026] Figure 8 A schematic diagram of a structure of a cover provided by an embodiment of the present application is shown in FIG. 5.

[0027] Icon: 10 - substrate; 11 - pad; 12 - conductive layer; 20 - chip; 21 - functional area; 22 - wire; 30 - cover; 31 - groove; 32 - via hole; 40 - sealing glue; 50 - adhesive film layer; 60 - plastic sealing layer. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0029] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "horizontal", "vertical" and the like do not mean that the components must be absolutely horizontal or vertical, but can be slightly inclined. The terms "first", "second", "third" and the like are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0030] In the description of the present application, it also needs to be explained that, unless otherwise explicitly specified and limited, the terms "set", "install", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0031] Please refer to Figures 1 to 8 The chip 20 packaging structure provided by the embodiment of the present application includes a substrate 10, a chip 20 and a cover 30. The substrate 10 is provided with a pad 11. The chip 20 is provided with a functional area 21 and a wire 22 located at the periphery of the functional area 21. The cover 30 is provided with a groove 31 and a via 32 located at the periphery of the groove 31. The chip 20 is fixedly connected with the cover 30 to form a chip 20 module. The functional area 21 is correspondingly arranged with the groove 31. The wire 22 is arranged in the via 32 and extends out of the via 32. The chip 20 module is arranged on the substrate 10. The wire 22 is electrically connected with the pad 11. The substrate 10 and the cover 30 are provided with a sealing glue 40. The chip 20 packaging structure can solve the problem that the welding structure between the chip 20 and the substrate 10 is easy to delaminate in the traditional chip packaging process.

[0032] It should be noted that, as Figures 5 to 7 The chip 20 packaging structure includes a substrate 10, a chip 20 and a cover 30. The substrate 10 is the basic bearing component of the entire chip 20 packaging structure, which provides fixation and support for the chip 20 and the cover 30 through the substrate 10. In addition, the substrate 10 also plays a key role in electrical connection. The pad 11 arranged on the substrate 10 is used for electrical connection with the wire 22 arranged on the chip 20, so as to realize signal transmission between the chip 20 and the external circuit. For example, the material of the substrate 10 can be ceramic or organic resin.

[0033] The chip 20 is the core component of the entire chip 20 packaging structure, which integrates various electronic elements (such as transistors, capacitors, resistors, etc.) inside to realize specific functions. For example, the chip 20 can be a chip 20 of a surface acoustic wave filter or other chips 20. For example, in the chip 20 of the surface acoustic wave filter, the functional area 21 is responsible for completing the filtering processing of the signal. The wire 22 located at the periphery of the functional area 21 on the chip 20 is mainly used for connecting the internal circuit of the chip 20 with the external circuit, so as to realize the input and output of the signal.

[0034] As Figure 8As shown, the groove 31 provided on the cover 30 can provide a relatively closed space for the functional area 21 of the chip 20, preventing external air, water vapor, dust and other impurities from contacting the functional area 21, thereby affecting the performance of the chip 20. At the same time, the via 32 on the cover 30 outside the groove 31 can provide a channel for the wire 22 on the chip 20 to pass out, so that the wire 22 can smoothly electrically connect with the pad 11 on the substrate 10. In this way, the cover 30 and the chip 20 are fixedly connected to form a chip 20 module, thereby enhancing the stability of the chip 20 in the packaging structure. For example, the cover 30 is made of a material with certain mechanical strength and insulation performance, such as ceramic, plastic, etc.

[0035] The sealing glue 40 is filled between the substrate 10 and the cover 30 to play a dual role of sealing and fixing: from the perspective of sealing, the sealing glue 40 can prevent external air, water vapor, dust and other impurities from entering the inside of the chip 20 packaging structure, so as to protect the functional area 21 and the internal circuit of the chip 20 from the influence of the external environment; from the perspective of fixing, the sealing glue 40 enhances the connection strength between the substrate 10 and the cover 30, so that the entire chip 20 packaging structure is more stable, and when subjected to external force impact or vibration, the relative positions of the components can remain unchanged, preventing the components from loosening, displacement and other situations, thereby ensuring the reliability of electrical connection.

[0036] In the traditional chip packaging process, the bottom of the chip 20 and the surface of the substrate 10 are electrically connected through a welding structure. Due to the difference in the thermal expansion coefficient of the materials of the chip 20 and the substrate 10, improper welding process parameters and other factors, the welding structure is prone to delamination. In the chip 20 packaging structure provided in the present application, the chip 20 and the cover 30 are fixedly connected to form a chip 20 module, the wire 22 on the chip 20 is arranged in the via 32 on the cover 30 and extends out of the via 32, and then the wire 22 is electrically connected with the pad 11 on the substrate 10. This connection mode changes the traditional welding connection between the chip 20 and the substrate 10 into the connection between the wire 22 and the pad 11, avoiding direct welding of the chip 20 and the substrate 10, thereby fundamentally eliminating the delamination problem caused by welding of the chip 20 and the substrate 10.

[0037] Furthermore, in the chip 20 packaging structure provided in the present application, the chip 20 and the cover 30 are fixedly connected to form a chip 20 module, and the functional area 21 is correspondingly arranged with the groove 31 on the cover 30. In actual use, even if there is temperature change, since the chip 20 and the cover 30 form a relatively stable whole, the thermal expansion consistency is relatively good, and compared with the relatively large thermal stress generated by the difference in the thermal expansion coefficient of the materials when the traditional chip 20 and the substrate 10 are welded, the thermal stress of this structure is less affected, further reducing the possibility of delamination.

[0038] In addition, the sealant 40 is arranged between the substrate 10 and the cover 30. The sealant 40 not only can play a sealing role to prevent the outside air, water vapor, dust and other impurities from entering the inside of the chip 20 package to affect its performance, but also can buffer the external mechanical stress and thermal stress to a certain extent. When subjected to external stress, the sealant 40 can absorb part of the stress, reduce the direct impact of the stress on the connection part of the wire 22 and the pad 11 and the connection part of the chip 20 and the cover 30, thereby reducing the risk of delamination or damage of the connection part.

[0039] As an implementable manner, as shown in Figures 4 to 7 In this embodiment, the conductive layer 12 is further arranged on the pad 11, and the wire 22 is electrically connected to the pad 11 through the conductive layer 12.

[0040] It should be noted that the conductive layer 12 is further arranged on the pad 11 to further optimize the electrical connection performance between the wire 22 and the pad 11 through the conductive layer 12, reduce the contact resistance, ensure that the current can be more smoothly transmitted between the wire 22 and the pad 11, and improve the stability and efficiency of signal transmission. Generally, the material of the pad 11 is metal, such as copper, and the surface is plated with a layer of other metal (such as gold, tin, etc.) to enhance its oxidation resistance and corrosion resistance performance and ensure long-term reliable electrical connection. For example, the conductive layer 12 is made of a metal material or an alloy with high electrical conductivity, such as a thin film or an alloy coating of silver, gold, etc. The conductive layer 12 has extremely low resistance and can greatly reduce energy loss in the signal transmission process. The thickness is generally controlled between several microns and tens of microns, which can ensure sufficient electrical conductivity and cannot affect the overall performance and dimensional accuracy of the pad 11 due to excessive thickness. The conductive layer 12 and the pad 11 are tightly combined through special processes such as electroplating, chemical plating, etc., to ensure that delamination and falling off do not occur during long-term use, thereby continuously and stably playing the role of optimizing electrical connection.

[0041] As an implementable manner, as shown in Figures 2 to 7 In this embodiment, the projection of the functional area 21 on the substrate 10 is located within the projection range of the groove 31 on the substrate 10.

[0042] It should be noted that the functional area 21 is a key area for the chip 20 to realize its core function, for example, in the chip 20 of the surface acoustic wave filter, it is responsible for signal filtering processing, and the groove 31 is arranged on the cover body 30 and mainly used for providing a relatively closed and protected space for the functional area 21. The projection of the above-mentioned functional area 21 on the substrate 10 is within the projection range of the groove 31 on the substrate 10, which means that the functional area 21 is completely covered by the groove 31 from the direction perpendicular to the substrate 10. This design ensures the close correspondence of the functional area 21 and the groove 31 in position, so that the groove 31 can maximize the protection of the functional area 21.

[0043] As an implementable manner, as shown in the figure, Figures 2 to 7 In this embodiment, the wire 22 and the via 32 are both multiple, and the multiple wire 22 and the multiple via 32 are one-to-one corresponding.

[0044] It should be noted that the wire 22 is a key component for electrical connection between the chip 20 and the substrate 10, responsible for leading out the signal of the internal circuit of the chip 20, and the via 32 is arranged on the cover body 30 to provide a through channel for the wire 22 to pass through the cover body 30 from the side of the chip 20 and connect with the pad 11 on the substrate 10. The above-mentioned multiple wire 22 and multiple via 32 are one-to-one corresponding, which means that each wire 22 has its corresponding via 32. From the layout of the chip 20, the wire 22 on the periphery of the functional area 21 of the chip 20 is accurately matched with the via 32 at the corresponding position of the cover body 30 according to a specific arrangement order, so as to ensure that the wire 22 can smoothly and accurately pass through the corresponding via 32 and then realize electrical connection with the pad 11 on the substrate 10. For example, there are ten wires 22 on the chip 20, and ten vias 32 are correspondingly arranged on the cover body 30, and each wire 22 corresponds to a unique via 32, which are completely matched in position, quantity and arrangement order, so as to realize stable and accurate signal transmission between the chip 20 and the external circuit.

[0045] As an implementable manner, as shown in the figure, Figures 2 to 7 In this embodiment, the multiple wires 22 are uniformly distributed along the periphery of the functional area 21.

[0046] It should be noted that the wire 22 is arranged around the outer periphery of the functional area 21, and a plurality of wires 22 are uniformly distributed, in other words, from the outer periphery contour of the functional area 21, the interval distance between two adjacent wires 22 is equal or approximately equal. For example, the projection of the functional area 21 is rectangular, then on the outer periphery of its four sides, the wires 22 will be arranged in equal intervals; or, the projection of the functional area 21 is circular, and the wires 22 will be distributed along the circumference at equal angular intervals. In the actual manufacturing process, such uniform distribution requires precise process control to ensure that the wires 22 form a regular and neat arrangement on the outer periphery of the functional area 21, thereby laying the foundation for accurate connection with the via 32 on the cover 30 and the pad 11 on the substrate 10.

[0047] As an implementable manner, the material of the wire 22 includes gold, silver, copper or aluminum.

[0048] It should be noted that the gold wire 22 has extremely high chemical stability and excellent electrical conductivity, strong anti-oxidation and anti-corrosion ability, which can ensure long-term stable electrical connection in complex environments, and is not easy to cause resistance increase and signal transmission obstruction due to oxidation and other problems; the silver wire 22 also has excellent electrical conductivity, and its electrical conductivity ranks first among common metals, with extremely high signal transmission efficiency, which can effectively reduce the loss in the signal transmission process; the copper wire 22 has good electrical conductivity and relatively low cost, which can reduce the material cost of chip 20 packaging while meeting the electrical performance requirements, and is suitable for large-scale production scenarios that are more sensitive to cost; the aluminum wire 22 has relatively low price, certain electrical conductivity and mechanical strength, and can play its cost advantage in some applications with relatively less stringent electrical performance requirements, to realize economical and efficient electrical connection.

[0049] As an implementable manner, the shape of the via 32 includes a rectangle, a circle, a sector, an ellipse, a trapezoid, a triangle or a polygon.

[0050] It should be noted that the rectangular via hole 32 has a regular shape, which is relatively easy to control the precision during the manufacturing process, and the right angle edge can better adapt to the arrangement of the wire 22 in a certain direction, facilitating the correspondence with the wire 22 on the outer periphery of the rectangular functional area 21; the circular via hole 32 is a relatively common shape, and the circumference is uniform in all directions, which can provide more uniform space for the wire 22. When the wire 22 passes through, it can maintain a relatively stable environment from any angle, reducing damage between the wire 22 and the wall of the via hole 32 caused by stress concentration; the fan-shaped via hole 32 is usually used for some special layout requirements, and the fan-shaped opening can be designed according to the distribution angle of the wire 22. For example, in the case of radial distribution of the wire 22 on the outer periphery of the functional area 21, the fan-shaped via hole 32 can better cooperate with the wire 22 and optimize the space layout; the elliptical via hole 32 has different size characteristics in the long axis and short axis directions, which can be adjusted according to the thickness of the wire 22 and the space limitation around the wire 22, providing more flexible passing space for the wire 22; the trapezoidal via hole 32 has the shape characteristics of wide at the top and narrow at the bottom or vice versa, which is beneficial to form a certain stress buffer area inside the via hole 32. When the wire 22 passes through, it can relieve the deformation or fracture risk of the wire 22 caused by stress in different directions to a certain extent; the three angles and three sides of the triangular via hole 32 form a unique structure. In some designs that require extremely high space utilization and have fewer wires 22, the triangular via hole 32 can fully utilize the space of the cover 30 while providing sufficient passing channels for the wire 22; the polygonal via hole 32 can be customized into various unique shapes according to specific design requirements to meet complex wire 22 layout and electrical performance requirements.

[0051] As an implementable manner, as shown in the figure, in the embodiment, the chip 20 packaging structure further comprises a film layer 50, and the chip 20 and the cover 30 are fixedly connected through the film layer 50. Figures 2 to 7

[0052] It should be noted that the film layer 50 is usually made of high-molecular materials with adhesion, such as epoxy resin-based film, etc. During the assembly process of the chip 20 and the cover 30, the film layer 50 is placed at the predetermined position between the chip 20 and the cover 30, and treated through certain temperature, pressure and other process conditions. The film layer 50 will undergo a curing reaction. Its adhesion can make the chip 20 and the cover 30 tightly fit together to form a firm fixed connection. This connection mode can ensure that the chip 20 is stably placed in the protection space provided by the cover 30, and the functional area 21 is accurately corresponding to the groove 31 on the cover 30, while creating a stable structural basis for the wire 22 to pass through the via hole 32 and connect with the pad 11 of the substrate 10. Moreover, the film layer 50 can also fill the possible small gaps between the chip 20 and the cover 30 during the curing process, further enhancing the tightness and sealing of the connection.​

[0053] As an implementable manner, as shown in Figure 6 and Figure 7 In the embodiment, a plastic sealing layer 60 is further arranged on the substrate 10 with the chip 20 module arranged thereon.

[0054] It should be noted that the plastic sealing layer 60 is usually made of thermosetting plastic or thermoplastic plastic and the like, and is covered on the chip 20 module and part of the substrate 10 by injection molding, potting, plastic sealing and the like. The plastic sealing layer 60 completely wraps the chip 20 module therein and forms isolation with the external environment. The role is not only to further protect the chip 20 module from physical damage from the external environment, such as air, water vapor, dust, mechanical impact and the like, but also to reinforce the connection structure between the chip 20 module and the substrate 10. The plastic sealing material fills the gap between the chip 20 module and the substrate 10, enhances the integrity of the entire chip 20 packaging structure, and reduces the possibility of loosening the connection between the chip 20 module and the substrate 10 due to external factors.

[0055] As shown in Figures 1 to 7 The packaging method of the chip 20 packaging structure provided by the application is generally as follows:

[0056] S1, providing a wafer, and arranging a wire 22 on one side of a chip 20 on the wafer;

[0057] S2, fixing a cover 30 on the chip 20 through an adhesive film layer 50, and arranging a functional area 21 and a groove 31 correspondingly, and arranging the wire 22 in a via hole 32 and extending out of the via hole 32;

[0058] S3, cutting the wafer to obtain a single chip 20 module;

[0059] S4, providing a substrate 10, and fixing the chip 20 module on the substrate 10, so that the wire 22 is electrically connected to the pad 11 through the conductive layer 12;

[0060] S5, arranging a sealing adhesive 40 between the substrate 10 and the cover 30 by a dispensing process;

[0061] S6, arranging a plastic sealing layer 60 on the substrate 10 with the chip 20 module arranged thereon by a plastic sealing process;

[0062] S7, cutting the substrate 10 to obtain a single product.

[0063] The application further provides an electronic device comprising the chip 20 packaging structure. Since the structure and advantages of the chip 20 packaging structure have been described in detail in the foregoing embodiments, they will not be described here.

[0064] The above merely describes optional embodiments of the present application, and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, and the like made within the principles and technical scope of the present application should be included in the protection scope of the present application.

[0065] In addition, it should be noted that various technical features described in the above specific embodiments can be combined in any suitable manner, without contradiction, and various possible combinations are not described again in the present application in order to avoid unnecessary repetition.

Claims

1. A chip package structure, characterized by, The chip package structure comprises a substrate, a chip and a cover, the substrate is provided with a pad, the chip is provided with a functional area and a wire which is located at the periphery of the functional area, the cover is provided with a groove and a via hole which is located at the periphery of the groove, the chip and the cover are fixedly connected to form a chip module, the functional area is correspondingly arranged with the groove, the wire is arranged in the via hole and extends out of the via hole, the chip module is arranged on the substrate, the wire is electrically connected with the pad, and the sealant is arranged between the substrate and the cover.

2. The chip package structure of claim 1, wherein, The pad is further provided with a conductive layer, and the wire is electrically connected with the pad through the conductive layer.

3. The chip package structure of claim 1, wherein, The projection of the functional area on the substrate is located in the projection range of the groove on the substrate.

4. The chip package structure of claim 1, wherein, The wire and the via hole are both multiple, and the multiple wires and the multiple via holes are one-to-one corresponding.

5. The chip package structure of claim 4, wherein, The multiple wires are uniformly distributed along the periphery of the functional area.

6. The chip package structure of claim 1, wherein, The material of the wire comprises gold, silver, copper or aluminum.

7. The chip package structure of claim 1, wherein, The shape of the via hole comprises a circle, a sector, an ellipse or a polygon.

8. The chip package structure of claim 1, wherein, The chip and the cover are fixedly connected through the adhesive film layer.

9. The chip package structure of claim 1, wherein, The substrate provided with the chip module is further provided with a plastic sealing layer.

10. An electronic device, comprising: The chip package structure comprises any one of claims 1-9. The chip package structure comprises any one of claims 1-9.

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