Incremental encoder signal phase discrimination and single-cycle signal output circuit

Abstract

The utility model provides an incremental encoder signal phase discrimination and single-cycle signal output circuit, which is positioned between an incremental encoder normalization circuit and an MCU (Microprogrammed Control Unit) processing circuit and sequentially comprises a jitter elimination circuit module, a shaping circuit module, a signal frequency multiplication module and a D-type trigger, the signal frequency multiplication module is composed of an exclusive-OR gate and an OR gate digital circuit and comprises an exclusive-OR gate U2A and an OR gate U1C, the exclusive-OR gate and OR gate digital circuit is used for generating a quadruplicated frequency signal from two signals which are input from the shaping circuit module and have a 90-degree phase difference, and the D-type trigger comprises an IC chip U3A and an IC chip U3B. The two ends of the IC chip U3A are respectively connected with the shaping circuit module and the phase discrimination unit, the two ends of the IC chip U3B are respectively connected with the signal frequency multiplication module and the output unit, the phase discrimination and frequency division functions can be realized, and the encoder can be further applied to scenes requiring direction judgment, speed measurement and encoder output period (pulse line number).

Description

TECHNICAL FIELD

[0001] The utility model relates to circuit control technical field, especially relates to a kind of incremental encoder signal phase discrimination and single cycle signal output circuit. BACKGROUND

[0002] In prior art, incremental encoder signal phase discrimination and cycle output circuit belong to the field of automation control and measurement, the signal phase discrimination and cycle output circuit of incremental encoder play a key role in various industries and automation scenarios, especially suitable for the application occasion needing high precision and real-time feedback;However, the current incremental encoder is not enough in the application processing precision of direction judgment, speed measurement, position signal feedback in motion control, displacement measurement and industrial automation, resulting in many errors in actual work. UTILITY MODEL CONTENT

[0003] In view of the deficiencies of prior art, the utility model aims at providing a kind of incremental encoder signal phase discrimination and single cycle signal output circuit, to solve the technical problems that the application processing precision of incremental encoder in motion control, displacement measurement and industrial automation, direction judgment, speed measurement, position signal feedback is not enough in prior art, resulting in many errors in actual work.

[0004] In order to achieve the above-mentioned purpose, the utility model is realized through the following technical schemes:

[0005] A kind of incremental encoder signal phase discrimination and single cycle signal output circuit, between incremental encoder normalization circuit and MCU processing circuit, the incremental encoder signal phase discrimination and single cycle signal output circuit successively include shake-off circuit module, shaping circuit module, signal frequency multiplication module, and D type flip-flop, the signal frequency multiplication module is by exclusive OR gate and or gate digital circuit, including exclusive OR gate U2A and or gate U1C, the exclusive OR gate and or gate digital circuit are used to generate four times frequency signal from the two signals with 90 degrees phase difference input from the shaping circuit module, the D type flip-flop includes IC chip U3A and IC chip U3B, two ends of the IC chip U3A are connected with the shaping circuit module and phase discrimination unit respectively, two ends of the IC chip U3B are connected with the signal frequency multiplication module and output unit respectively.

[0006] According to an aspect of the above technical solution, the de-bouncing circuit module comprises a resistor unit and a diode unit arranged in parallel with each other, and a capacitor unit connected with the resistor unit and the diode unit respectively, the front ends of the resistor unit and the diode unit are connected with the output signal unit of the incremental encoder normalization circuit, the shaping circuit module comprises a digital circuit unit connected with the de-bouncing circuit module, and the digital circuit unit is used for converting the irregular trend signal output from the de-bouncing circuit module into a rising level signal or a falling level signal.

[0007] According to an aspect of the above technical solution, the output signal of the incremental encoder normalization circuit comprises an A-phase single-end signal and a B-phase single-end signal.

[0008] According to an aspect of the above technical solution, the resistor unit comprises a resistor R1 connected with the A-phase single-end signal and a resistor R2 connected with the B-phase single-end signal, the diode unit comprises a diode D1 connected with the A-phase single-end signal and a diode D2 connected with the B-phase single-end signal, and the capacitor unit comprises a capacitor C1 connected with the resistor R1 and the diode D1 respectively and a capacitor C2 connected with the resistor R2 and the diode D2 respectively.

[0009] According to an aspect of the above technical solution, the ends of the capacitor C1 and the capacitor C2 are grounded.

[0010] According to an aspect of the above technical solution, the digital circuit unit comprises an OR gate U1A connected with the resistor R1 and an OR gate U1B connected with the resistor R2.

[0011] According to an aspect of the above technical solution, the OR gate U1A and the OR gate U1B are connected with the XOR gate U2A.

[0012] According to an aspect of the above technical solution, the OR gate U1A is connected with the CP1 end of the IC chip U3A through the 3rd pin of the IC chip U3A, the OR gate U1B is connected with the D1 end of the IC chip U3B through the 5th pin of the IC chip U3B, and the IC chip U3A is connected with the phase discrimination unit through the 2nd pin.

[0013] According to an aspect of the above technical solution, the OR gate U1C is connected with the CP2 end of the IC chip U3B through the 11th pin of the IC chip U3B, and the D2 end and the O2 end of the IC chip U3B are connected with the output unit through the 9th pin and the 12th pin respectively.

[0014] According to an aspect of the above technical solution, the SD1 end and the CD1 end of the IC chip U3A are grounded through the 6th pin and the 4th pin respectively, and the SD2 end and the CD2 end of the IC chip U3B are grounded through the 8th pin and the 10th pin respectively.

[0015] Compared with the prior art, the utility model has the beneficial effects that:

[0016] Through setting the incremental encoder signal phase detection and single cycle signal output circuit between the incremental encoder normalization circuit and MCU processing circuit, the signal output by the incremental encoder normalization circuit will pass through the debouncing circuit module to remove the burr signal caused by mechanical switch, encoder pulse jitter and other factors, ensure that the signal has higher definition and stability in the following logic circuit, effectively avoid the problem of false triggering or multiple triggering, then the signal processed by the debouncing circuit module is a standard high and low square wave, and then waveform shaping is carried out, a more standard logic level is output, the signal quality after shaping is better, convenient for subsequent logic circuit processing, then through the phase detection characteristics of the exclusive OR gate and the OR gate digital circuit of the signal frequency multiplication module, four times frequency signal can be generated through exclusive OR operation of two 90 degree phase difference signals. Since the two signals are phase difference signals, the pulse frequency of exclusive OR output is 2 times or 4 times the frequency of the input signal, and higher resolution can be obtained after frequency multiplication processing, which is suitable for control systems with high precision requirements, finally, when receiving the clock signal, the D type flip-flop stores the level state on the data input end D into the flip-flop, and outputs to the Q end of the phase detection unit at the rising or falling edge of the clock, and then the direction of the incremental encoder normalization circuit output signal can be distinguished through the high and low levels of the Q end, the phase detection unit can also calculate the signal speed by measuring the number of pulses in a unit time, and the D type flip-flop can also convert the frequency information into a standard cycle signal and output to the output unit, which is used for transmitting cycle data of speed and position change, and convenient for the main control system to process. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is the schematic diagram of the incremental encoder signal phase detection and single cycle signal output circuit in the whole control circuit in the first embodiment of the utility model;

[0018] Figure 2 It is the structure schematic of the incremental encoder signal phase detection and single cycle signal output circuit in the first embodiment of the utility model Figure 1 Figure 1 ;

[0019] Figure 3 It is the structure schematic of the incremental encoder signal phase detection and single cycle signal output circuit in the first embodiment of the utility model Figure 1 Figure 2 ;

[0020] MAIN ELEMENT SYMBOL EXPLANATION:

[0021]

[0022] ​​The following detailed description will further explain the present application with reference to the above mentioned drawings. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. Several embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] It should be noted that when an element is referred to as being "fixedly attached" to another element, it can be directly on the other element or intervening elements can also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. As used herein the terms "vertical", "horizontal", "left", "right" and similar terms are used for explanation only.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] Referring to Figures 1 to 3 , a kind of incremental encoder signal phase discrimination and single cycle signal output circuit 20 in the first embodiment of the present application is located between incremental encoder normalization circuit 10 and MCU processing circuit 30, the incremental encoder signal phase discrimination and single cycle signal output circuit 20 successively includes anti-wobble circuit module 21, shaping circuit module 22, signal frequency multiplication module 23, and D flip-flop 24, the signal frequency multiplication module 23 is constituted by exclusive OR gate and or gate digital circuit, including exclusive OR gate U2A and or gate U1C, the exclusive OR gate and or gate digital circuit is used to generate four times frequency signal from the two signals with 90 degree phase difference input from the shaping circuit module 22, the D flip-flop 24 includes IC chip U3A and IC chip U3B, two ends of the IC chip U3A are connected with the shaping circuit module 22 and phase discrimination unit 25 respectively, two ends of the IC chip U3B are connected with the signal frequency multiplication module 23 and output unit 26 respectively.

[0027] It can be understood that the utility model discloses a signal phase discrimination and single cycle signal output circuit 20 is arranged between the incremental encoder normalization circuit 10 and MCU processing circuit 30, the signal of incremental encoder normalization circuit 10 output will pass through the debouncing circuit module 21 to remove the burr signal caused by mechanical switch, encoder pulse jitter and other factors, guarantee signal in the logic circuit of following has higher definition and stability, effectively avoid the problem of false triggering or multiple triggering, then through the shaping circuit module 22, the signal that passes through the debouncing circuit module 21 processing is the high, low square wave of standard side length, and then carries out waveform shaping, and outputs more standard logic level, and the signal quality after shaping is better, and it is convenient for subsequent logic circuit processing, then through the phase detection characteristics of the exclusive or gate and or gate digital circuit of signal frequency multiplication module 23, two 90 degree phase difference signals can generate four times frequency signal through exclusive or operation. Since two signals are phase difference signals, the pulse frequency of exclusive or output is 2 times or 4 times of the frequency of input signal, and higher resolution can be obtained after frequency multiplication processing, and it is suitable for the control system with higher precision requirement, and finally, when receiving the clock signal, the D-type flip-flop 24 stores the level state on the data input end D into the flip-flop, and outputs to the Q end of the phase discrimination unit 25 at the rising edge or falling edge of the clock, and then the direction of the signal output by the incremental encoder normalization circuit 10 can be distinguished through the high level and low level of the Q end, and the phase discrimination unit 25 can also calculate the signal speed by measuring the number of pulses in a unit time, and the frequency information can also be converted into a standard cycle signal by the D-type flip-flop 24 and output to the output unit 26, to transmit the cycle data of speed and position change, and facilitate the processing of the main control system.

[0028] Specifically, in the embodiment, the debouncing circuit module 21 includes a resistance unit and a diode unit arranged in parallel with each other, and a capacitor unit connected with the resistance unit and the diode unit respectively, the front end of the resistance unit and the diode unit is connected with the output signal unit of the incremental encoder normalization circuit 10, and the shaping circuit module 22 includes a digital circuit unit connected with the debouncing circuit module 21, and the digital circuit unit is used for converting the irregular trend signal output from the debouncing circuit module 21 into a rising level signal or a falling level signal.

[0029] It can be understood that when receiving the signal sent by the incremental encoder normalization circuit 10, first, the combination of the resistance unit, the diode unit and the capacitor unit in the debouncing circuit module 21 is used to filter out the glitches and noise in the signal, ensuring that the signal is smooth and stable; then the signal after debouncing processing is reshaped into a standard square wave pulse signal through the digital circuit unit in the shaping circuit unit, because the output signal of the encoder may become irregular after long distance transmission or interference, the shaping circuit module 22 can use the Schmidt trigger and other logic circuits to restore the input signal to a standard TTL square wave signal, so as to improve the anti-interference ability of the signal and ensure that the signal can be accurately recognized and processed in different terminals of the back-end processing circuit, further improving the accuracy of signal transmission.

[0030] Further, the output signal of the incremental encoder normalization circuit 10 includes an A-phase single-ended signal 11 and a B-phase single-ended signal 12; the resistance unit includes a resistance R1 connected to the A-phase single-ended signal 11 and a resistance R2 connected to the B-phase single-ended signal 12, the diode unit includes a diode D1 connected to the A-phase single-ended signal 11 and a diode D2 connected to the B-phase single-ended signal 12, and the capacitor unit includes a capacitor C1 connected to the resistance R1 and the diode D1 respectively, and a capacitor C2 connected to the resistance R2 and the diode D2 respectively; the ends of the capacitor C1 and the capacitor C2 are grounded.

[0031] It can be understood that in this embodiment, two single-ended signals (A-phase single-ended signal 11 and B-phase single-ended signal 12) are taken as an example, and during the transmission of the output signal unit of the incremental encoder normalization circuit 1010, glitches or noise may occur on the signal edge due to mechanical movement, jitter or interference. The debouncing circuit filters out these glitch signals through the combination of resistance R1 (R1=470Ω), capacitor C1 (C1=10pF) and diode D1 (D1=1N5819G), ensuring that the transmission of A-phase single-ended signal 11 is smoother and more stable; similarly, the combination of resistance R2 (R2=470Ω), capacitor C2 (C2=10pF) and diode D2 (D2=1N5819G) is used to filter out these glitch signals, ensuring that the transmission of B-phase single-ended signal 12 is smoother and more stable.

[0032] The principle is that the debouncing circuit absorbs the sudden high-frequency interference (glitch signal) through the charging and discharging process of the capacitor, and the diode provides protection, and the resistance and the capacitor constitute a low-pass filter, which can filter out unnecessary high-frequency noise and avoid signal false triggering. effectively eliminate the glitch signal caused by mechanical jitter or electrical noise, ensure that the pulse signal of the encoder is cleaner and more stable, and facilitate subsequent shaping circuit processing.

[0033] Further, the digital circuit unit comprises an OR gate U1A connected with the resistor R1, and an OR gate U1B connected with the resistor R2; the OR gate U1A and the OR gate U1B are both connected with the XOR gate U2A.

[0034] It can be understood that, by the OR gate U1A and the OR gate U1 (MC14071), the signal is converted into a standard high, low square wave, and for a weak or distorted signal, the OR gate can perform waveform shaping by pulling up or pulling down the level, and output a more standard logic level; the shaped signal has better quality, facilitating subsequent logic circuit processing.

[0035] Specifically, by using the phase detection characteristics of the XOR gate U2A and the OR gate U1C, two signals with a 90-degree phase difference (such as the A-phase single-ended signal 11 and the B-phase single-ended signal 12) are generated by XOR operation to generate a four-fold frequency signal. Since the A-phase single-ended signal 11 and the B-phase single-ended signal 12 are phase difference signals, the pulse frequency of the XOR output is 2 times or 4 times the frequency of the input signal; after frequency multiplication processing, higher resolution can be obtained, which is suitable for control systems with high accuracy requirements.

[0036] Further, the OR gate U1A is connected with the CP1 end of the IC chip U3A through the 3rd pin of the IC chip U3A, the OR gate U1B is connected with the D1 end of the IC chip U3B through the 5th pin of the IC chip U3B, and the IC chip U3A is connected with the phase detection unit 25 through the 2nd pin; the OR gate U1C is connected with the CP2 end of the IC chip U3B through the 11th pin of the IC chip U3B, and the D2 end and the O2 end of the IC chip U3B are connected with the output unit 26 through the 9th pin and the 12th pin respectively; the SD1 end and the CD1 end of the IC chip U3A are grounded through the 6th pin and the 4th pin respectively, and the SD2 end and the CD2 end of the IC chip U3B are grounded through the 8th pin and the 10th pin respectively.

[0037] The IC symbols U3A and U3B constitute a double D-type flip-flop, wherein the D-type flip-flop with the IC symbol U3A outputs the real-time direction signal of the encoder after superimposing and inverting the A / B phase signal processed by the shaping circuit; the D-type flip-flop with the IC symbol U3B gives a single-cycle encoder line value by 2-dividing the A / B phase signal processed by the shaping circuit and processed by the frequency multiplication circuit, facilitating the application of the rear-end system.

[0038] It can be understood that the above circuit structure can realize the functions of phase detection and frequency division, for example, in the embodiment, the phase detection function: by inputting the A-phase single-ended signal 11 as the clock and the B-phase single-ended signal 12 as the data, when the rising edge of the A-phase single-ended signal 11 arrives, the D flip-flop outputs the current state of the B-phase single-ended signal 12. In this way, if the A-phase single-ended signal 11 leads the B-phase single-ended signal 12, the Q output of the phase detection circuit outputs high level, otherwise low level, thereby distinguishing the positive and negative rotation of the incremental encoder, and further determining the direction of the signal.

[0039] The frequency division function: when multiple D flip-flops are cascaded, the frequency division output of the input signal can be realized, for example, 2 frequency division or 4 frequency division, to reduce the frequency of the output signal and facilitate the control system processing.

[0040] The phase detection and frequency division functions of the D flip-flop ensure accurate direction detection and frequency control, so that the circuit can effectively adapt to different application scenarios.

[0041] Through the phase detection and frequency division functions, it can be applied in the fields of direction judgment, speed measurement, encoder output period (pulse line number), etc.

[0042] Direction judgment: the two signal channels (A-phase single-ended signal 11 and B-phase single-ended signal 12) output by the incremental encoder have a phase difference of 90 degrees, and by comparing the phase relationship of the two signals, the accurate judgment of the rotation or movement direction can be realized. When the encoder rotates clockwise, the A-phase single-ended signal 11 leads the B-phase single-ended signal 12; when it rotates counterclockwise, the B-phase single-ended signal 12 leads the A-phase single-ended signal 11. This direction information is used for direction judgment in the control system, ensuring the accuracy of the movement direction.

[0043] Speed measurement:

[0044] The phase detection circuit calculates the speed by measuring the number of pulses (period output) in a unit time. The faster the encoder rotates, the higher the output pulse frequency. Real-time speed feedback is very important for accurate control of acceleration, deceleration and stable running speed.

[0045] Period output:

[0046] The period output circuit converts the frequency information in the encoder signal into a standard period signal, which is used to transmit the period data of speed and position change for processing by the main control system.

[0047] In summary, the incremental encoder signal phase detection and single period signal output circuit in the above embodiment of the present application can realize the functions of phase detection and frequency division, and can be applied in scenarios requiring direction judgment, speed measurement, and encoder output period (pulse line number).

[0048] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the utility model. In the specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0049] The above-described embodiments only express several implementation manners of the utility model, the description is more specific and detailed, but it cannot be understood as the limitation of the utility model patent scope. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the utility model, a number of modifications and improvements can be made, which belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent should be subject to the appended claims.

Claims

1. An incremental encoder signal phase discrimination and one-cycle signal output circuit, located between an incremental encoder normalization circuit and an MCU processing circuit, characterized by, The incremental encoder signal phase detection and single cycle signal output circuit sequentially comprises a debounce circuit module, a shaping circuit module, a signal frequency multiplication module, and a D-type flip-flop, the signal frequency multiplication module is composed of an XOR gate and an OR gate digital circuit, including an XOR gate U2A and an OR gate U1C, the XOR gate and the OR gate digital circuit are used for generating a four times frequency signal from two signals with a 90 degree phase difference input from the shaping circuit module, the D-type flip-flop includes an IC chip U3A and an IC chip U3B, two ends of the IC chip U3A are connected with the shaping circuit module and the phase detection unit respectively, two ends of the IC chip U3B are connected with the signal frequency multiplication module and the output unit respectively.

2. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 1, wherein, The debounce circuit module includes a resistance unit and a diode unit arranged in parallel with each other, and a capacitor unit connected with the resistance unit and the diode unit respectively, the front ends of the resistance unit and the diode unit are connected with the output signal unit of the incremental encoder normalization circuit, the shaping circuit module includes a digital circuit unit connected with the debounce circuit module, the digital circuit unit is used for converting an irregular trend signal output from the debounce circuit module into a rising level signal or a falling level signal.

3. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 2, wherein, The output signal of the incremental encoder normalization circuit includes an A-phase single-ended signal and a B-phase single-ended signal.

4. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 3, wherein, The resistance unit includes a resistance R1 connected with the A-phase single-ended signal and a resistance R2 connected with the B-phase single-ended signal, the diode unit includes a diode D1 connected with the A-phase single-ended signal and a diode D2 connected with the B-phase single-ended signal, and the capacitor unit includes a capacitor C1 connected with the resistance R1 and the diode D1 respectively, and a capacitor C2 connected with the resistance R2 and the diode D2 respectively.

5. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 4, wherein, The ends of the capacitor C1 and the capacitor C2 are grounded.

6. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 5, wherein, The digital circuit unit includes an OR gate U1A connected with the resistance R1 and an OR gate U1B connected with the resistance R2.

7. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 6, wherein, The OR gate U1A and the OR gate U1B are connected with the XOR gate U2A.

8. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 7, wherein, The OR gate U1A is connected with the CP1 end of the IC chip U3A through the 3rd pin of the IC chip U3A, the OR gate U1B is connected with the D1 end of the IC chip U3B through the 5th pin of the IC chip U3B, and the IC chip U3A is connected with the phase detection unit through the 2nd pin.

9. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 8, wherein, The OR gate U1C is connected with the CP2 end of the IC chip U3B through the 11th pin of the IC chip U3B, and the D2 end and the O2 end of the IC chip U3B are connected with the output unit through the 9th pin and the 12th pin respectively.

10. The incremental encoder signal phase detection and one-cycle signal output circuit of claim 9, wherein, The SD1 end and the CD1 end of the IC chip U3A are grounded through the 6th pin and the 4th pin respectively, and the SD2 end and the CD2 end of the IC chip U3B are grounded through the 8th pin and the 10th pin respectively.

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