Vertical phase change memory device

Abstract

A vertical phase change memory device includes: a device layer; and an interconnect structure on the device layer, the interconnect structure including a phase change random access memory (PCRAM) device. The phase change random access memory device includes: an electrode layer on a device layer; an oxide semiconductor layer on the electrode layer; a gate structure surrounding the oxide semiconductor layer; an insulating layer on the gate structure; and a phase change resistor. The phase change resistor includes: a bottom electrode on an oxide semiconductor layer; a phase change layer on the bottom electrode; and a top electrode on the phase change layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a vertical phase change memory device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased with each successive generation. This scaling down of features size benefits from among other things the decrease in operating voltages that has occurred for reasons of reduced power dissipation, increased processor speeds, and the like. However, decreasing equipment and manufacturing process complexities have generally become more difficult and more expensive with each successive generation of ICs. For these and / or other reasons, it is increasingly critical that SUMMARY

[0003] Some embodiments of the present disclosure provide a vertical phase change memory device, including a device layer and an interconnect structure on the device layer. The interconnect structure includes a phase change random access memory device, the phase change random access memory device includes an electrode layer above the device layer, an oxide semiconductor layer on the electrode layer, a gate structure surrounding the oxide semiconductor layer, an insulating layer on the gate structure, and a phase change resistor. The phase change resistor includes a bottom electrode on the oxide semiconductor layer, a phase change layer on the bottom electrode, and a top electrode on the phase change layer.

[0004] Some embodiments of the present disclosure provide a vertical phase change memory device, including a device layer and an interconnect structure on the device layer. The interconnect structure includes a phase change random access memory device, the phase change random access memory device includes a phase change resistor, an oxide semiconductor layer on a bottom electrode, a first insulating layer on the phase change resistor, a gate structure on the first insulating layer, the gate structure surrounding the oxide semiconductor layer, a second insulating layer on the gate structure, and an electrode layer above the oxide semiconductor layer. Wherein the phase change resistor includes a top electrode above the device layer, a phase change layer on the top electrode, and a bottom electrode on the phase change layer.

[0005] Some embodiments of the present disclosure provide a vertical phase change memory device, including a substrate, a device layer on the substrate, a first portion of an interconnect structure on the device layer, a phase change random access memory device on the first portion, and a second portion of the interconnect structure on the phase change random access memory device. The phase change random access memory device includes an oxide semiconductor layer, a gate structure surrounding the oxide semiconductor layer, and a phase change resistor. The phase change resistor and the oxide semiconductor layer are stacked in a vertical direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawings. It is emphasized that various features are not to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the clarity of the discussion.

[0007] FIGS. 1A-1Q Views of various embodiments of an IC device at different stages of assembly in accordance with aspects of the present disclosure;

[0008] FIGS. 2A-2B Diagrammatic cross-sectional and circuit diagram views of various embodiments of an IC device in accordance with aspects of the present disclosure;

[0009] FIGS. 3A-3U Views of various embodiments of an IC device at different stages of assembly in accordance with aspects of the present disclosure;

[0010] FIGS. 4A-4B Diagrammatic cross-sectional and circuit diagram views of various embodiments of an IC device in accordance with aspects of the present disclosure;

[0011] FIGS. 5-6 Flowchart of a method of forming an IC device in accordance with aspects of the present disclosure.

[0012]

LEGEND

[0013] 10, 10A: IC device

[0014] 16, 36, 200, 200P: gate structure

[0015] 18, 18M, 38: fuse device

[0016] 20, 20M, 40: phase change random access memory device

[0017] 22: via

[0018] 35, 37: opening

[0019] 41: gate spacer

[0020] 74: internal spacer

[0021] 80: nanostructure transistor

[0022] 82: source / drain feature

[0023] 82P: source / drain

[0024] 110: substrate

[0025] 160: first dielectric layer

[0026] 162: first electrode layer

[0027] 162C: electrode contact portion

[0028] 164: channel layer / oxide semiconductor layer

[0029] 164C: channel

[0030] 164H: horizontal portion

[0031] 164L, 164L': oxide semiconductor layer

[0032] 166: dielectric layer / gate dielectric layer

[0033] 166H: horizontal portion

[0034] 166L, 166L': gate dielectric layer

[0035] 166V: vertical portion

[0036] 168, 168L, 168L': gate conductive layer

[0037] 168H: horizontal portion

[0038] 168V: vertical portion

[0039] 170: mask layer / oxide layer

[0040] 172: oxide layer

[0041] 174: insulating layer

[0042] 180, 180M: bottom electrode

[0043] 180L: bottom electrode layer

[0044] 180B: horizontal portion

[0045] 180S: vertical sidewall portion

[0046] 180V: V-shaped portion

[0047] 182, 182L, 182M: phase change material layer

[0048] 182B: horizontal portion

[0049] 182S: vertical sidewall portion

[0050] 182V: V-shaped portion

[0051] 184, 184L, 184M: heating layer

[0052] 184B: horizontal portion

[0053] 184S: vertical sidewall portion

[0054] 184V: V-shaped portion

[0055] 186, 186M: top electrode

[0056] 186B: horizontal portion

[0057] 186L: top electrode layer

[0058] 186S: vertical sidewall portion

[0059] 186V: V-shaped portion

[0060] 188L: spacer

[0061] 188M: spacer material layer

[0062] 190BL, 190G, 190WL: opening

[0063] 192: electrode layer

[0064] 194, 196, 198: contact element

[0065] 260: transistor

[0066] 270: phase change resistor / resistor

[0067] 300: planar transistor

[0068] 352: fourth dielectric layer

[0069] 360: first dielectric layer

[0070] 364: channel / oxide semiconductor channel

[0071] 364L: oxide semiconductor layer

[0072] 366L, 366L': gate dielectric layer

[0073] 368: gate electrode layer

[0074] 368L, 368L': Gate conductive layer

[0075] 370: Mask layer

[0076] 372B, 372L: Second dielectric layer

[0077] 374, 374L: Insulation layer

[0078] 380: Bottom electrode

[0079] 380L: Bottom Electrode Layer

[0080] 382, 382L: Phase change material layer

[0081] 384, 384L: Heating layer

[0082] 386: Top Electrode

[0083] 386C: Electrode contact portion

[0084] 390: Electrode layer

[0085] 390L: Electrode layer

[0086] 392: Third dielectric layer

[0087] 392L: Third dielectric layer

[0088] 393: Second Insulation Layer

[0089] 394, 396, 398: Contact elements

[0090] 460: Transistor

[0091] 470: Phase-changing resistor

[0092] 500: Masking layer / Dielectric layer

[0093] 700, 700A: Front-side interconnect structure

[0094] 710, 710A: Device Layer

[0095] 720: Dielectric layer

[0096] 730, 730A, 730B: Conductivity characteristics

[0097] 740: Conductive Through-hole

[0098] 800, 800A: Backside interconnect structure

[0099] 810: Dielectric layer

[0100] 820: Conductivity characteristics

[0101] 820A: conductive feature

[0102] 820B: conductive feature / second power rail

[0103] 820C: first power rail

[0104] 830: conductive via

[0105] 840: backside via

[0106] 850: well

[0107] 900: semiconductor layer

[0108] 1000, 2000: method

[0109] 1010, 1020, 1030, 1040, 1050, 1060, 1070, 1080: operation

[0110] 2010, 2020, 2030, 2040, 2050, 2060, 2070: operation

[0111] D1: distance DETAILED DESCRIPTION

[0112] The following detailed description provides many different embodiments, or examples, for implementing different features of the provided application. The specific examples of elements and arrangements are provided to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature over a second feature during the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features can not be in direct contact. Further, the present disclosure can refer to reference numerals that are the same in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0113] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0114] Indicative of relative size, the terms "about", "substantially", and the like, are to be understood in a manner understandable in the art once in view of the current description and one or more of the drawings discerned by one of ordinary skill in the art.

[0115] The words "first," "second," and "third," and the like, are used to describe events or elements in a sequence, but can be interchanged or changed in certain circumstances. For example, a second layer can be formed on (e.g., subsequent to) a first layer, but in certain circumstances the first layer can be considered a "second layer," a "third layer," a "fourth layer," etc., and the second layer can be considered a "first layer," a "third layer," a "fourth layer," etc.

[0116] The word "surrounding" is used to describe a structure completely or partially encircling another element or structure, e.g., in three-dimensional space. For example, a first structure can surround four sides (e.g., left, right, front, and back) of a second structure, but not two perpendicular sides (e.g., top and bottom) of the second structure. In other examples, a first structure can partially surround a second structure, e.g., by surrounding three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0117] The present disclosure relates generally to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanoscale FETs such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), etc.

[0118] Integrated memory refers to memory technology that is built directly on a microchip or integrated circuit, rather than being a separate or "stand-alone" element. Phase change random access memory (PCRAM) is one such technology. PCRAM is a non-volatile memory technology that has the benefits of high density, low power, and fast access.

[0119] Phase change random access memory (PCRAM) is also known as phase change memory (PCM) and is a non-volatile memory that uses the properties of a phase change material to store information. PCRAM relies on the ability of a material, such as germanium-antimony-tellurium (Ge2Sb2Te5 or "GST"), to transform between crystalline (ordered) and amorphous (disordered) states. These two phases have different resistances, allowing the different phases to represent different binary data (0s and Is). To write data, a controlled electrical pulse is applied to the material. A high intensity pulse can melt the material and rapidly cool it, leaving the material in an amorphous state with a high resistance. A lower intensity pulse can heat the material and is sufficient to crystallize the material, resulting in a low resistance state. To read the stored data, a small current is passed through the material. By measuring the resistance, the device can determine whether the material is in a self-crystallized or amorphous state, to read the stored binary data. PCRAM is non-volatile, retaining data even when the power is turned off. PCRAM can provide faster write and read speeds compared to some other non-volatile memories, such as flash memory. PCRAM can withstand a large number of write and erase cycles. Planar memory devices can include two separate planar devices, including a single transistor (1T) and a single resistor (1R) that are typically placed in two separate metal layers. Thus, increasing device density becomes difficult.

[0120] In several embodiments, for further improvements in device density, grounding resistors or "ground fuses" are stacked on the source / drain or source / drain regions to reduce the area occupied by passive components. Depending on the context, source / drain or source / drain regions may refer to the source or drain individually or together. Depending on the embodiment, the phase-change random access memory (PCM) device may be a vertical phase-change random access memory (VRAM) device and may be referred to as a VRAM device. For example, PCM devices may be used in front-end-of-line (FEOL) planar, fin field-effect transistor (FET), or gate-all-around field-effect transistor (GAAFET) logic devices. The interconnect between the PCM device and the logic device may be via back-end-of-line (BEOL) metal wiring. In interconnect structures (such as back-end processes or back-side interconnects), vertical phase-change random access memory (VRAM) devices can be inserted between two metal layers, such as between Mx and Mx+1 metal layers (e.g., M3 and M4, M6 and M7, etc.), similar to vertical all-around gate VRAM devices. The VRAM device may include a metal-insulator-metal (MIM) fuse above or below the oxide semiconductor channel, such as an indium gallium zinc oxide (IGZO) channel.

[0121] Nanostructured transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes typically involve lithography and self-alignment processes, allowing the fabricated patterns to have, for example, smaller spacing than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Using a self-alignment process, spacers are formed along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructured structure.

[0122] Based on all aspects of this disclosure, FIGS. 1A-1Q These are views of different embodiments of the phase-change random access memory devices 20 and 20M at different stages of assembly. According to various aspects of this disclosure, FIG. 2A and FIG. 2B These are illustrated cross-sectional and circuit diagram views of various embodiments of IC devices 10 and 10A including phase-change random access memory devices 20 and 20M. FIG. 5 This is a flowchart of a method 1000 for forming a memory device according to different embodiments.

[0123] According to one or more aspects of the present disclosure, FIG. 5 A flow diagram of a method 1000 of forming an IC device or portion from a workpiece is shown. The method 1000 is merely an example and is not intended to limit the present disclosure to anything described in the method 1000. Additional operations can be provided before, during, and after the method 1000, and some operations described can be removed, omitted, or modified. For the sake of simplicity, the various operations are not depicted in detail. According to embodiments of the method 1000, fragmented perspective and / or cross-sectional views of the workpiece are incorporated at various stages of assembly, such as FIGS. 1A-1Q The method 1000 is shown below. For the avoidance of doubt, the X direction is perpendicular to the Y direction in all of the figures, and the Z direction is perpendicular to both the X direction and the Y direction. Notably, because the workpiece can be assembled into a semiconductor device, the workpiece can be considered a semiconductor device for the purposes of the disclosure.

[0124] In FIG. 1A , a first electrode layer 162 is formed on a first dielectric layer 160 of an integrated circuit or integrated wafer (IC) device. The first dielectric layer 160 can be formed on a first portion of an interconnect structure above or below a device layer, or included in the first portion of the interconnect structure, more details of which are described in FIG. 2A and FIG. 2B Briefly, the device layer can include one or more integrated devices, such as planar field effect transistors, fin field effect transistors, nanostructure field effect transistors, metal-oxide-semiconductor (MOS) capacitors, and the like. The interconnect structure can be above the device layer and can include mid-end-of-line (MEOL) and / or back-end-of-line (BEOL) interconnect structures that provide electrical connections between the integrated devices of the device layer and other devices external to the IC device. The interconnect structure can include replacement or additional backside interconnect structures at the backside of the device layer. Examples of frontside and backside interconnect structures 700, 800A and planar field effect transistor and nanostructure field effect transistor device layers 710, 710A are depicted in FIG. 2A and FIG. 2B Operations 1010 and 1020 of the method 1000 include forming a device layer (operation 1010) and forming a first portion of an interconnect structure on the device layer (operation 1020), both of which are described in more detail in FIG. 2A and FIG. 2B .

[0125] The first dielectric layer 160 can be or include an oxide, such as silicon oxide, and can be included in an interconnect structure on or below the device layer. The first dielectric layer 160 can be formed by a suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like. The first dielectric layer 160 can be present on a metallization layer that includes metal features (such as contact elements, contact lines, electrical lines, vias, and the like) embedded in an intermetal dielectric (IMD). The intermetal dielectric layer can be or include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric material, and the like.

[0126] The first electrode layer 162 is formed on the first dielectric layer 160. In some embodiments, the first electrode layer 162 is or includes a transition metal nitride. For example, the first electrode layer 162 can be or include titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and the like, and is formed by a suitable deposition method, such as physical vapor deposition (PVD), chemical vapor deposition, low-pressure CVD (LPCVD), plasma-enhanced chemical vapor deposition, atomic layer deposition, and the like.

[0127] Corresponding to operation 1030 of the method 1000, after the first electrode layer 162 is formed on the first dielectric layer 160, an oxide semiconductor layer 164L is formed on the first electrode layer 162. The oxide semiconductor layer 164L can be or include indium gallium zinc oxide. In some embodiments, the oxide semiconductor layer 164L is or includes one or more of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), hafnium indium zinc oxide (HIZO), gallium zinc oxide (GZO), indium gallium oxide (IGO), zinc indium tin oxide (ZITO), combinations thereof, and the like. The oxide semiconductor layer 164L can be formed by a suitable deposition method, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, e-beam evaporation, and the like.

[0128] FIG. 1B In this process, after forming the oxide semiconductor layer 164L, a patterned oxide semiconductor layer 164L' containing the channel 164C is formed by patterning the oxide semiconductor layer 164L. The channel 164C may have a columnar shape. In other words, the channel 164C may have a cross-sectional profile in the XY plane that is circular, square, rectangular, irregular, etc. The height of the channel 164C in the Z-axis direction relative to the width of the channel 164C in the X-axis or Y-axis direction may have an aspect ratio of the channel 164C. The aspect ratio of the channel 164C may be in the range of about 1.5 to about 20, about 2 to about 15, about 4 to about 10, or other suitable ranges. An aspect ratio exceeding about 20 may cause the channel 164C to collapse. An aspect ratio below about 1.5 may not provide sufficient channel length.

[0129] FIGS. 1C-1F In the middle, corresponding to operation 1040 of method 1000, a gate structure 16 is formed around channel 164C (see FIG. 1F The gate structure 16 includes a dielectric layer 166 and a gate conductive layer 168.

[0130] exist FIG. 1C In this process, after forming a channel 164C with a columnar shape, a gate dielectric layer 166L is formed on an oxide semiconductor layer 164L' containing the channel 164C. The gate dielectric layer 166L surrounds and covers the channel 164C. In other words, the gate dielectric layer 166L can be in direct contact with the sidewalls and top surface of the channel 164C. The gate dielectric layer 166L can be or contains at least a dielectric material, such as silicon dioxide, or a high dielectric constant gate dielectric material, which may be referenced to a dielectric material having a higher dielectric constant than silicon dioxide (k≈3.9). Examples of high dielectric constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, and combinations thereof. In some embodiments, the gate dielectric layer 166L contains one or more SiO2, HfO, La, SiON, SiCON, Zn, or Zr. In some embodiments, the gate dielectric layer 166L has a thickness of about 5 angstroms to about 100 angstroms. High dielectric constant dielectric materials can be deposited by atomic layer deposition, chemical vapor deposition, physical vapor deposition, molecular beam epitaxy (MBE), etc.

[0131] Continue to refer to FIG. 1CAfter the gate dielectric layer 166L is formed, a gate conductive layer 168L is formed on the gate dielectric layer 166L. The gate conductive layer 168L may be in direct contact with the gate dielectric layer 166L. For example, the gate conductive layer 168L may be in direct contact with the sidewalls and top surface of the gate dielectric layer 166L. The gate conductive layer 168L may contain a conductive material, such as polysilicon, silicon, titanium, tantalum, aluminum, tungsten, nickel, zinc, indium, gallium, germanium, carbon, cobalt, ruthenium, iridium, molybdenum, copper, or combinations thereof. The conductive material may be deposited by a suitable deposition method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electron beam evaporation, etc. In some embodiments, the gate conductive layer 168L has a thickness of about 5 angstroms to about 100 angstroms.

[0132] exist FIG. 1D In the process, after the gate conductive layer 168L is formed, a masking layer 170, which may be or includes an oxide layer, is formed. FIG. 1C The oxide layer 170 is formed on the structure depicted herein. The oxide layer 170 may be a blanket covering the gate conductive layer 168L. The oxide layer 170 may be formed by any of the methods mentioned above in relation to the first dielectric layer 160.

[0133] exist FIG. 1E In the process, after the oxide layer 170 is formed, the oxide layer 170 is patterned to expose the electrode contact portion 162C. FIG. 1E The diagram is indicated by a dashed box. After patterning the oxide layer 170, the exposed portions of the gate conductive layer 168L, the gate dielectric layer 166L, and the oxide semiconductor layer 164L' are removed to expose the electrode contact portion 162C. The oxide layer 170 can be etched by reactive ion etching (RIE), wet etching, plasma etching, inductively coupled plasma (ICP) etching, etc. After patterning the oxide layer 170, for example, the exposed portions of the gate conductive layer 168L are etched using reactive ion etching, inductively coupled plasma etching, etc., with an etchant such as carbon tetrafluoride to form the gate conductive layer 168L'. For example, the gate dielectric layer 166L is etched using dry etching, such as reactive ion etching, inductively coupled plasma etching, etc., with an etchant such as chlorine or fluorine-based etchant, to form the gate dielectric layer 166L'. For example, dry etching, such as active ion etching, inductively coupled plasma etching, etc., is used by using chlorine or fluorine-based etchants, followed by etching of the oxide semiconductor layer 164L' to form the channel layer 164.

[0134] like FIG. 1FAfter the gate conductive layer 168L', the gate dielectric layer 166L', and the channel layer 164 are formed, portions of the gate conductive layer 168L' and the gate dielectric layer 166L' in the region above the channel 164C are removed. In some embodiments, the portions of the gate conductive layer 168L' and the gate dielectric layer 166L' in the region above the channel 164C are removed by a combination of chemical mechanical planarization (CMP) and anisotropic etching. In some embodiments, the portions of the gate conductive layer 168L' and the gate dielectric layer 166L' in the region above the channel 164C are removed by a combination of chemical mechanical planarization (CMP) and isotropic etching. FIG. 1F After the operation of the method 1000, the oxide layer 170 is removed and another oxide layer 172 is formed. The oxide layer 172 is recessed to a level lower than the upper surface of the channel 164C by, for example, chemical mechanical planarization (CMP), anisotropic etching, or a combination thereof. After the recessing, portions of the gate conductive layer 168L' and the gate dielectric layer 166L' in the region above the channel 164C are exposed. In some embodiments, the height of the portion of the channel 164C protruding from the oxide layer 172 is in the range of about 1 / 10 to 2 / 3 of the total height of the channel 164C.

[0135] After the oxide layer 172 is recessed, the exposed portions of the gate conductive layer 168L' and the gate dielectric layer 166L' in the region above the channel 164C are removed. The removal method can be the same as described with reference to the method 1000, including the same etching process and chemicals. After the exposed portions are removed, the gate conductive layer 168 and the gate dielectric layer 166 are retained, and the resulting structure is depicted in FIG. 1E . The gate dielectric layer 166 includes a vertical portion 166V surrounding the channel 164C and a horizontal portion 166H covering the horizontal portion of the oxide semiconductor layer 164. The gate conductive layer 168 includes a vertical portion 168V surrounding the channel 164C and a horizontal portion 168H covering the horizontal portion 166H of the gate dielectric layer 166 and the horizontal portion 164H of the oxide semiconductor layer 164, respectively. FIG. 1F

[0136] In the structure depicted in FIGS. 1G-1I , the fuse device 18 is formed on the exposed upper portion of the channel 164C, corresponding to the operation 1050 of the method 1000. The fuse device 18 can be a metal-insulator-metal device. The fuse device 18 can be a phase change resistor and can include one or more of the following layers: a bottom electrode, a phase change material (PCM) layer, a heater or heating layer, a top electrode, a passivation or dielectric layer (optional), a package (optional).

[0137] In the structure depicted in FIG. 1G , the insulating layer 174 is formed covering the gate dielectric layer 166 and the gate conductive layer 168. The insulating layer 174 provides electrical insulation between the gate structure 16 and the fuse device 18 formed in subsequent operations. In some embodiments, the insulating layer 174 is a dielectric layer including one or more of SiN, SiCN, SiON, SiOCN, SiOC, and the like. In some embodiments, the insulating layer 174 is a dielectric layer including one or more of SiN, SiCN, SiON, SiOCN, SiOC, and the like.​FIG. 1F In the structure described herein, an insulating layer 174 can be formed by blanket deposition of one or more conformal layers of the aforementioned dielectrics. Deposition can be performed using suitable deposition methods such as chemical vapor deposition, low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, etc. The insulating layer 174 can be recessed after deposition to expose the region above the channel 164C.

[0138] exist FIG. 1G In the middle, the upper portion of channel 164C extends above insulating layer 174 and has tapered sidewalls in the XZ plane. For example, the upper portion is conical or pyramidal in perspective view. The sloping sidewalls can be formed or combined into, such as... FIG. 1G The pointed tip described. In some embodiments, the sloping sidewalls form a rounded or blunt tip instead of a pointed tip.

[0139] exist FIG. 1H In the process, after the insulating layer 174 is deposited, the metal layer forming the fusible device 18 can be subsequently deposited as a blanket-covered conformal layer covering the channel 164C and the insulating layer 174. The blanket-covered conformal layer will inherit the pointed shape of the portion above the channel 164C.

[0140] First, a bottom electrode layer 180L can be formed. The bottom electrode layer 180L may contain a transition metal nitride, such as TiN, or other conductive metals, such as tungsten. The bottom electrode layer 180L can be formed by a suitable deposition method, such as atomic layer deposition, chemical vapor deposition, etc.

[0141] After the bottom electrode layer 180L is formed, a phase change material layer 182L can be formed. The phase change material layer 182L can be a layer with phase change characteristics as previously described, and can contain germanium-antimony-tellurium. In some embodiments, the phase change material layer 182L contains GeTe, SbTe, SbSeTe, GeSbSe, GaSb, GaSbTe, SiSbTe, GeCuTe, GeCrTe, InSbTe, AgInSbTe, SnSb, and combinations thereof, etc. The phase change material layer 182L can be formed by a suitable deposition method, such as atomic layer deposition, chemical vapor deposition, etc.

[0142] After the phase change material layer 182L is formed, a heating or heated layer 184L can be formed. The heated layer 184L can be a layer of tungsten. A tungsten layer can be formed on the phase change material layer 182L by a suitable deposition method, such as atomic layer deposition, chemical vapor deposition, etc.

[0143] After the formation of the heating layer 184L, a top electrode layer 186L is formed. The top electrode layer 186L can include a transition metal nitride, such as titanium nitride, or other conductive metal, such as tungsten. The top electrode layer 186L can be formed by suitable deposition methods, such as atomic layer deposition, chemical vapor deposition, and the like. In some embodiments, the top electrode layer 186L and the bottom electrode layer 180L are the same material or substantially the same material.

[0144] In FIG. 1I , after the formation of the bottom electrode layer 180L, a patterning process is performed on the phase change material layer 182L, the heating layer 184L, and the top electrode layer 186L to form the fuse device 18. The patterning can include one or more etching processes to remove some portions of each of the bottom electrode layer 180L, the phase change material layer 182L, the heating layer 184L, and the top electrode layer 186L between adjacent channels 164C to form independent fuse devices 18 on each channel 164C, where each channel 164C is electrically and physically isolated from each other. In addition, the removal of the material of the bottom electrode layer 180L, the phase change material layer 182L, the heating layer 184L, and the top electrode layer 186L between the channels 164C opens up space for forming contact elements to the first electrode layer 162 and the gate conductive layer 168, as described in more detail below. FIGS. 1L-1N The bottom electrode layer 180L, the phase change material layer 182L, the heating layer 184L, and the top electrode layer 186L can be removed by reactive ion etching, inductively coupled plasma etching, and the like. The fuse device 18 includes the structure resulting from the bottom electrode 180, the phase change material layer 182, the heating layer 184, and the top electrode 186, which is depicted in FIG. 1I .

[0145] In FIGS. 1J-1K , corresponding to operation 1060 of the method 1000, a spacer 188L is formed on the fuse device 18. The spacer 188L includes a lower spacer 188L that surrounds a lower portion of the fuse device 18. The spacer 188L facilitates providing protection during the formation of the contact elements and provides physical isolation and electrical insulation between the fuse device 18 and the formed contact elements.

[0146] In FIG. 1JIn this process, a spacer material layer 188M is formed on the fuse 18 and the insulating layer 174. The spacer material layer 188M can be or contains one or more SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, or other suitable materials. The spacer material layer 188M can be formed by suitable deposition methods, such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition (HDPCVD), atomic layer deposition, etc. A conformal thin layer can be deposited in a blanket manner on the exposed areas of the fuse 18 and the insulating layer 174 to form the spacer material layer 188M, resulting in a structure in... FIG. 1J The Chinese side indicated that...

[0147] exist FIG. 1K In this process, the spacer material layer 188M is etched to remove the horizontal portion covering the top electrode 186 and the insulating layer 174. Etching may include active ion etching, inductively coupled plasma etching, wet etching, or other suitable etching methods. After etching, the lower spacer 188L remains on the fuse 18, as... FIG. 1K As shown. Lower spacers 188L may surround the lower region of the fuse device 18, and may be placed on the sidewalls or ends of the horizontal portions of the adjacent (and directly contacting) top electrode 186, heating layer 184, phase change material layer 182, and bottom electrode 180, and placed on the upper surface of insulating layer 174. Each lower spacer 188L may have a circular profile. That is, after the etching process, the outer sidewalls may be circular rather than vertical.

[0148] exist FIGS. 1L-1N In operation 1070 of method 1000, contact elements 194, 196, and 198 are formed and landed on electrode contact portion 162C, top electrode 186, and gate conductive layer 168, respectively. Contact elements 194, 196, and 198 provide phase-change random access memory electrical connections. For example, bit lines (BL), word lines (WL), and ground (or other bias voltage) can be connected to the phase-change random access memory via contact elements 194, 196, and 198, wherein contact elements 194, 196, and 198 can carry voltages applied to electrode contact portion 162C, top electrode 186, and gate conductive layer 168 to clear or operate the phase-change random access memory device 20. FIG. 1O This is a simplified circuit diagram of a phase-change random access memory according to various embodiments.

[0149] exist FIG. 1LIn this process, a masking layer 500 is formed on the fuse device 18 and the insulating layer 174. The masking layer 500 may be or may contain an oxide layer, such as silicon oxide, and may be deposited by any of the methods described above.

[0150] exist FIG. 1M In this process, openings 190BL, 190G, and 190WL are formed in the mask layer 500 and the underlying structure to expose the electrode contact portion 162C, the top electrode 186, and the gate conductive layer 168. For example, openings 190BL, 190G, and 190WL can be formed first through the mask layer 500 and landing on the insulating layer 174 and the top electrode 186. Then, openings 190BL and 190WL can extend through the insulating layer 174 and the oxide layer 172 to expose the electrode contact portion 162C and the gate conductive layer 168. Openings 190BL, 190G, and 190WL can be formed using one or more suitable etching methods, such as active ion etching, inductively coupled plasma, etc.

[0151] exist FIG. 1N In the process, source / drain contact elements 194, gate contact elements 198, and top electrode contact elements 196 (or collectively referred to as contact elements 194, 196, and 198) are formed in openings 190BL, 190WL, and 190G, respectively. Contact elements 194, 196, and 198 may be or include one or more substrates, barrier layers, adhesive layers, conductive core layers, etc. In some embodiments, contact elements 194, 196, and 198 comprise one or more Cu, Co, Al, Ni, W, Ru, Ti, TiN, Ta, TaN, their alloys, their multilayers, and combinations thereof, etc. Contact elements 194, 196, and 198 layers can be formed by one or more suitable deposition methods, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0152] exist FIG. 1O In this circuit, the phase-change random access memory device 20 can be represented in a simple circuit form, such as a 1T1R ("one transistor, one resistor") circuit containing a transistor 260 and a resistor 270, wherein the resistor 270 can be a phase-change resistor 270. The gate conductive layer 168, the gate dielectric layer 166, and the channel 164C can contain the transistor 260. The gate electrode of the gate conductive layer 168 or the transistor 260 can be connected via a contact element 198 and a word line (WL). The source / drain electrodes of the transistor 260 can be a first electrode layer 162 and can be connected via a contact element 194 and a bit line. The top electrode 186 of the fuse device 18 can be a phase-change resistor 270 and can be connected via a contact element 196 and a bias voltage (e.g., ground).

[0153] Corresponding to operation 1080 of method 1000, after the contact elements 194, 196, 198 are formed, a second portion of the interconnect structure can be formed on the contact elements 194, 196, 198. In some embodiments, the second portion of the interconnect structure is formed by a deposition process. In some embodiments, the second portion of the interconnect structure is formed by a deposition process that is performed after the contact elements 194, 196, 198 are formed. FIG. 2A and FIG. 2B The front-side interconnect structure 700 and the back-side interconnect structure 800A including the first portion and the second portion and the phase change random access memory device 20 located therebetween are described in

[0154] According to various embodiments, FIG. 1P and FIG. 1Q are diagrams showing the M-type fuse device 18M.

[0155] In FIG. 1P , the fuse device 18M has an M-type cross-sectional profile in the XZ plane and / or the YZ plane. The M-type can be a result of etching the over portion of the passage 164C from the convex insulating layer 174. In other words, in a perspective view, the central region of the over portion is recessed to have a cutout shape of an inverted cone or an inverted pyramid. As shown in FIG. 1P , in some embodiments, after the over portion is etched, the subsequently formed layers will inherit the inverted cone or inverted pyramid shape. In other words, each of the bottom electrode 180M, the phase change material layer 182M, the heating layer 184M, and the top electrode 186M can have sloped sidewalls at the corresponding locations in the passage 164C. Due to the angular or pointed profile of the top electrode 186M, the contact area between the contact element 196 and the top electrode 186M is increased, which is advantageous to reduce the contact resistance between the contact element 196 and the top electrode 186M and to improve the performance of the phase change random access memory device 20 including the fuse device 18M.

[0156] According to various embodiments, FIG. 1Q is a detailed view of the fuse device 18M of the phase change random access memory device 20M of FIG. 1P . As shown, each of the bottom electrode 180M, the phase change material layer 182M, the heating layer 184M, and the top electrode 186M can include a horizontal portion 180B, 182B, 184B, 186B, a vertical sidewall portion 180S, 182S, 184S, 186S, and a V-shaped portion 180V, 182V, 184V, 186V, respectively. The V-shaped portion 180V, 182V, 184V, 186V is V-shaped in cross-section, but can be conical or pyramidal in perspective view.

[0157] The V-shaped portion 180V increases the contact area between channel 164C and bottom electrode 180M, and improves (e.g., reduces) the contact resistance between channel 164C and bottom electrode 180M, thus improving device performance. In other words, in addition to contacting channel 164C via vertical sidewall portion 180S (e.g., direct contact), the V-shaped portion 180V extending into channel 164C increases the contact area between the upper surface of channel 164C and bottom electrode 180M. In some embodiments, the V-shaped portion 180V of bottom electrode 180M extends to a position lower than horizontal portion 180B by a distance D1. Distance D1 can be in the range of about 10 angstroms to 10 nanometers. In some embodiments, the V-shaped portion 180V extends to the same extent as the lower surface of horizontal portion 180B, or to an extent above the lower or upper surface of horizontal portion 180B. Although the V-shaped portion 180V is drawn with a pointed tip, in some embodiments, the V-shaped portion 180V may have a rounded or blunt tip. In some embodiments, instead of forming a V-shaped portion 180V, a U-shaped portion is formed.

[0158] According to various embodiments FIG. 2A and FIG. 2B This is a schematic cross-sectional view of the phase-change random access memory device 20 included in IC devices 10 and 10A. FIG. 2A In this configuration, the phase-change random access memory device 20 is included in the front-side interconnect structure 700. FIG. 2B In this embodiment, the phase-change random access memory (PCM) device 20 is included in the back-side interconnect structure 800A. It should be understood that some embodiments of the IC devices 10, 10A may include the PCM device 20 in both the front-side interconnect structure 700 and the back-side interconnect structure 800A, which is advantageous for increasing the density of the PCM device per unit area of ​​the IC device. It should also be understood that, for illustrative purposes, the planar transistor 300 is drawn on... FIG. 2A In the middle, and nanostructured transistors 80 (e.g., gate-all-around field-effect transistors) are drawn. FIG. 2B In China, nanostructured transistors 80 can also be applied to... FIG. 2A The arrangement in the middle, and the planar transistor 300 can be applied to FIG. 2A The arrangement of transistors. According to various embodiments, in addition to planar transistors 300 and nanostructure transistors 80, IC devices 10 and 10A may include other types of transistors (e.g., fin field-effect transistors).

[0159] exist FIG. 2A In the IC device 10, a substrate 110, a device layer 710 on and / or within the substrate 110, and a front-side interconnect structure 700 on the device layer 710 including a phase-change random access memory device 20. (Drawn on...) FIG. 2AThe device layer 710 includes planar transistors 300. In some embodiments, the device layer 710 includes fin field-effect transistors, nanostructure transistors (such as gate-all-around field-effect transistors), etc.

[0160] Substrate 110 can be a semiconductor substrate, such as a host semiconductor, which may be doped (e.g., p-type doped or n-type doped) or undoped. The semiconductor material of substrate 110 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including germanium silicide, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; other compound semiconductors including gallium, zinc, indium, and / or oxygen; or combinations thereof. Other substrates may be single-layer, multi-layer, or gradient substrates.

[0161] The planar transistor 300 includes a source / drain 82P and a gate structure 200P formed on and within a well 850 in a substrate 110.

[0162] In well 850, the source / drain 82P can be a heavily doped region of substrate 110, doped with impurities to form an n-type (and donor impurity such as phosphorus or arsenic) semiconductor of N-type metal-oxide-semiconductor or a p-type (and acceptor impurity such as boron) semiconductor of P-type metal-oxide-semiconductor. Between the source / drain 82P is a lightly doped channel, doped with impurities of the opposite type to those of the source / drain 82P. For example, an N-type metal-oxide-semiconductor may have a p-type channel (e.g., boron), and a P-type metal-oxide-semiconductor may have an n-type channel (e.g., phosphorus). In some embodiments, the source / drain 82P is doped with carbon.

[0163] The gate structure 200P may be or contain polycrystalline silicon (“polycrystalline silicon”) or a metal such as tungsten. The gate structure 200P may contain an insulating layer or “gate dielectric” that may be or contains silicon dioxide (SiO2) or a high dielectric constant dielectric such as hafnium dioxide (HfO2), which is beneficial for reducing leakage current and improving performance.

[0164] Although not in FIG. 2A The diagrams are drawn separately, but contact elements providing 82P source / drain and 200P gate structure electrical connections may be present. The contact elements may contain tungsten (W), aluminum (Al), or other suitable conductive materials. The contact elements may include one or more barrier layers, such as titanium nitride, and an adhesive layer to improve physical contact and reduce diffusion.

[0165] A front-side interconnect structure 700 is located on a gate structure 200P, a source / drain structure 82P, and a substrate 110. The front-side interconnect structure 700 may include conductive features 730 embedded in a dielectric layer 720. For example, the front-side interconnect structure 700 may include one or more metal layers (e.g., M0, M1, M2, ..., Mn), each metal layer containing a dielectric layer 720 that may be an insulating dielectric (IMD) layer. Each insulating dielectric layer may be or include one or more silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), undoped glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiOxCy), spin-on-glass (SOG), or combinations thereof. The conductive features 730 may be connected to each other via conductive vias 740. For example, a first conductive feature 730A is connected to a second conductive feature 730B via a conductive via 740. The conductive features 730, 730A, 730B and the conductive via 740 may be or contain one or more metals, such as copper, aluminum, titanium nitride, tantalum nitride, tantalum, graphene, carbon nanotubes, conductive polymers, and combinations thereof.

[0166] The phase change random access memory (RAM) device 20 can be placed between two or more metal layers. For example, the phase change RAM device 20 can be placed between a third metal layer (M3) and a fourth metal layer (M4). In some embodiments, the phase change RAM device 20 can be placed between two metal layers separated by more than one layer. For example, the phase change RAM device 20 can be placed between a fourth metal layer (M4) and a sixth metal layer (M6), or a seventh metal layer (M7).

[0167] exist FIG. 2B In this configuration, the phase-change random access memory device 20 is housed within a back-side interconnect structure 800A. The back-side interconnect structure 800A is similar to... FIG. 2A The front-side interconnect structure 700 is similar, but it is formed on the back side of the device layer 710A. For example, as FIG. 2A The substrate 110 depicted can be partially or completely removed, and the back-side interconnect structure 800A can contact the source / drain features 82 on the back side of the device layer 710A. The back-side interconnect structure 800A may include conductive features 820 embedded in the dielectric layer 810. FIG. 2B The diagram shows a front-side interconnect structure 700A. The front-side interconnect structure 700A is similar in many respects to the front-side interconnect structure 700 and includes conductive features 730 embedded in the dielectric layer 720. In some embodiments, a semiconductor layer 900 is disposed on the side of the front-side interconnect structure 700A opposite to the device layer 710A. The semiconductor layer 900 may be undoped silicon.

[0168] FIG. 2B Depicted is a device layer 710A containing nanostructure transistors 80 instead of planar transistors 300. A single nanostructure transistor 80 can be or contain one or more N-type FETs (NFETs) or P-type FETs (PFETs) as described below. Nanostructure transistors 80 can be separated (e.g., physically and / or electrically isolated) from one another by shallow trench isolation (STI), deep trench isolation (DTI), local oxidation of silicon (LOCOS), etc.

[0169] Nanostructure transistors 80 are formed on and / or in a substrate 110 and generally contain a gate structure 200 that spans and / or encircles a semiconductor channel 22 or nanostructure. Gate structure 200 controls current flow through channel 22.

[0170] Nanostructure transistors 80 are shown containing four channels 22 that are laterally adjacent to source / drain features 82 or regions and are covered and encircled by gate structure 200. Generally, the number of channels 22 is two or more, such as three, four, or more. Based on voltages applied to gate structure 200 and source / drain features 82, gate structure 200 controls current flow out of and into source / drain features 82 through channels 22.

[0171] In some embodiments, nanostructure devices contain N-type FETs and source / drain features 82 that contain silicon phosphorous (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, combinations thereof, and the like. In some embodiments, nanostructure devices contain P-type FETs and source / drain features 82 that contain silicon germanium (SiGe), or are un-doped or formed with a dopant, such as SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or other suitable semiconductor materials. Generally, source / drain features 82 can contain any suitable semiconductor material and suitable combination of dopants.

[0172] Each channel 22 comprises a semiconductor material, such as silicon or a silicon compound, such as silicon germanium, etc. The channel 22 is nanostructured (e.g., having dimensions in the nanometer range), and each channel 22 can have an elongated shape extending along the X-axis. In some embodiments, each channel 22 has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of the channel 22 can be rectangular, circular, square, circular, elliptical, hexagonal, or a combination thereof.

[0173] In some embodiments, the length (e.g., measured along the X-axis) of the channels 22 can vary from one another, such as tapering during a fin-etching process. Each channel 22 can not have a uniform thickness (e.g., along the X-axis direction), such as a channel trimming process to increase the gate structure assembly process capability for the spaces (e.g., measured along the Z-axis direction) between the extended channels 22. For example, the middle portion of each channel 22 can be thinner than the two ends of each channel 22. Such a shape can be collectively referred to as a “dog bone” shape.

[0174] In some embodiments, the spaces between the channels 22 are in a range of about 8 nanometers to about 12 nanometers in the vertical direction. In some embodiments, the thickness (measured in the Z direction) of each channel 22 is in a range of about 5 nanometers to about 8 nanometers. In some embodiments, the width (measured in the Y direction) of each channel 22 is at least about 8 nanometers.

[0175] The gate structure 200 is disposed between and above the channels 22. In some embodiments, the gate structure 200 is disposed between and above the channels 22 that are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 comprises an interfacial layer (IL), one or more gate dielectric layers, one or more work function adjustment layers, and a metal core layer.

[0176] An interfacial layer, which can be an oxide of the material of the channel 22, is formed on the exposed regions of the channel 22. The interfacial layer promotes adhesion of the gate dielectric layer and the channel 22. In some embodiments, the interfacial layer has a thickness of about 5 angstroms to about 50 angstroms. In some embodiments, the interfacial layer has about 10 angstroms. If the interfacial layer has a thickness that is too thin, it can result in a void or an insufficient adhesion property. If the interfacial layer is too thick, it consumes gate fill capability related to threshold voltage adjustment and resistance. In some embodiments, for threshold voltage adjustment, the interfacial layer is doped with a dipole, such as lanthanum.

[0177] In some embodiments, the gate dielectric layer comprises at least one high-dielectric-constant gate dielectric material, which can be considered as a dielectric material having a higher dielectric constant than silicon oxide (k≈3.9). Examples of high-dielectric-constant dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer has a thickness of about 5 to about 100 angstroms. The gate dielectric layer can be a single layer or multiple layers formed on an interface layer.

[0178] The gate structure 200 also includes a metal core layer on the gate dielectric layer. The metal core layer may contain conductive materials such as cobalt, tungsten, ruthenium, and combinations thereof. In some embodiments, the metal core layer is or contains a compound or alloy based on cobalt, tungsten, or ruthenium, containing one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, and combinations thereof. Between channels 22, one or more work function metal layers circumferentially surround (in cross-sectional view) the metal core layer, wherein the gate dielectric layer circumferentially surrounds the work function metal layers, and wherein the interface layer circumferentially surrounds the gate dielectric layer. The gate structure 200 may also include an adhesive layer formed between one or more work function layers and the metal core layer to increase adhesion. For simplicity, the adhesive layer is not shown. FIG. 2B China specifically stated this.

[0179] The nanostructure transistor 80 may include gate spacers 41 disposed on the sidewalls of the topmost metal core layer, gate dielectric layer, and surface layer of channel 22, and internal spacers 74 disposed on the sidewalls of the interface layer and / or gate dielectric layer between channels 22. The internal spacers 74 are also disposed between channels 22. FIG. 2B In the described embodiments, the gate spacer 41 comprises two spacer layers. In some embodiments, the gate spacer 41 comprises a single spacer layer or three or more spacer layers. Each of the first and second spacer layers may comprise a dielectric material, such as a low-dielectric-constant material like SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, the second spacer layer is not present. The materials of the first and second spacer layers may be the same as or different from each other. Generally, the portion above the second spacer layer (or the first spacer layer, when the second spacer layer is absent) may be partially or completely removed to increase the aspect ratio of the opening forming the source / drain feature 82.

[0180] The source / drain features 82 on the backside of the device layer 710A can be contacted through conductive backside vias 840. The backside vias 840 can contact the conductive features 820 in one or more source / drain features 82 and the backside metal layers (e.g., "BM0," "BM1," etc.).

[0181] The phase change random access memory device 20 can be placed between two backside metal layers, for example, between a second backside metal layer (BM2) and a third or fourth backside metal layer (BM3, BM4). The conductive via 830 can extend adjacent the phase change random access memory device 20 and connect a conductive feature 820A of a metal layer on the phase change random access memory device 20 with a conductive feature 820B of a metal layer under the phase change random access memory device 20. The terms "on" and "under" in the description can be the direction of the paper and are interchangeable based on the orientation of the IC device 10A. In other words, as shown, when the backside of the IC device 10A is facing up, the conductive feature 820A is "on top of" the conductive feature 820B. FIG. 2B

[0182] In some embodiments, the conductive feature 820B is a power rail of the backside interconnect structure 800. The backside interconnect structure 800 can include at least two power rails 820B, 820C. The first power rail 820C is connected to logic devices (e.g., nanostructure transistors 80) and the second power rail 820B is connected to the phase change random access memory device 20. The first power rail 820C can have the same or smaller dimensions as the second power rail 820B. For example, the second power rail 820B used to drive the phase change random access memory device 20 can carry a higher voltage than the first power rail 820C. The larger dimensions of the second power rail 820B are beneficial to improve reliability at carrying high voltage. In some embodiments, the power rails 820B, 820C are or include W, Ru, Ir, Mo, etc.

[0183] In the embodiments described with reference to FIGS. 1A-2B the contact element 194 connecting the bit line (BL) to the drain of the transistor 260 via the first electrode layer 162 is connected to an overlying metal layer. In some embodiments, the contact element 194 is not connected to an overlying metal layer as depicted in FIG. 2A and FIG. 2B the contact element 194 is formed prior to the formation of the phase change random access memory device 20, such that the first electrode layer 162 is connected to an underlying metal layer. In such embodiments, the method described in FIG. 1E is omitted.

[0184] FIGS. 3A-3T are views of various embodiments of a phase change random access memory device 40 at different stages of assembly, in accordance with aspects of the present disclosure.​FIG. 3U This is a circuit diagram view of the phase change random access memory device 40. FIG. 4A and FIG. 4B These are illustrated cross-sectional views of various embodiments of the IC devices 10, 10A according to various aspects of this disclosure. FIG. 6 This is a flowchart of a method 2000 for forming an IC device according to various embodiments.

[0185] FIG. 6 A flowchart illustrating a method 2000 for forming an IC device or a portion thereof from a workpiece is provided according to one or more aspects of this disclosure. Method 2000 is merely an example and is not intended to limit this disclosure to the content explicitly described in method 2000. Additional operations may be provided before, during, and after method 2000, as well as additional embodiments of the method, which may replace, omit, or move some of the described operations. For simplicity, not all operations are described in detail. According to embodiments of method 2000, fragmented perspectives and / or cross-sectional views of the workpiece are combined at different stages of assembly, such as... FIGS. 3A-3T As shown, Method 2000 is explained below. To avoid any ambiguity, all figures show the X direction perpendicular to the Y direction, and the Z direction perpendicular to both the X and Y directions. It is worth noting that because the workpiece can be assembled into a semiconductor device, the workpiece can be considered a semiconductor device for the purposes of this document.

[0186] FIGS. 3A-3T In this process, a fuse 38 is formed before the transistors of the phase-change random access memory device 40 are formed. Some operations of method 2000 are similar in many ways to... FIG. 5 The method is 1000 times similar, and similar descriptions are provided for reference.

[0187] FIG. 3A In the middle, the formation and FIG. 1A The first dielectric layer 160 is similar in many respects to the first dielectric layer 360. After the first dielectric layer 360 is formed, an opening 37 is formed on the first dielectric layer 360, and a fuse 38 is formed in the opening 37. Before the first dielectric layer 360 is formed, a device layer of the IC device 10 is formed, as described in Figures 1A, 2A, and 2B above and corresponding to operation 2010 of method 2000. Then, a first portion of the interconnect structure is formed on the device layer, corresponding to operation 2020 of method 2000. In other words, the phase-change random access memory device 40 may be formed on the metal layer of the interconnect structure. The opening 37 may have an inverted triangular cross-sectional profile in the XZ plane. In some embodiments, the opening 37 is conical or pyramidal in perspective view.

[0188] exist FIGS. 3B-3EIn some embodiments, after forming the opening 37 in the first dielectric layer 360, a fuse device 38 is formed on the first dielectric layer 360 including the opening 37, corresponding to operation 2030 of method 2000. The fuse device 38 can be a phase change resistor and can include one or more of the following layers: a bottom electrode, a phase change material layer, a heating layer, a top electrode, a passivation layer (optional), an encapsulation layer (optional).

[0189] In some embodiments, the material layers forming the fuse device 38 can be blanket conformal layers deposited sequentially and following the shape of the opening 37. FIG. 3B

[0190] First, the top electrode 386 can be formed to include a transition metal nitride, such as TiN, or other suitable conductive metal, such as W. The top electrode 386 can be formed by suitable deposition methods, such as atomic layer deposition, chemical vapor deposition, and the like.

[0191] After forming the top electrode 386, a heating layer 384L is formed. The heating layer 384L can be a layer of tungsten. The tungsten layer can be formed on the top electrode 386 by suitable deposition methods, such as atomic layer deposition, chemical vapor deposition, and the like.

[0192] After forming the heating layer 384L, a phase change material layer 382L is formed. The phase change material layer 382L can be a phase change material layer and can include any of the materials described above with reference to the phase change material layer 182L. The phase change material layer 382L can be formed by suitable deposition methods, such as atomic layer deposition, chemical vapor deposition, and the like. FIG. 1H

[0193] After forming the phase change material layer 382L, a bottom electrode layer 380L is formed. The bottom electrode layer 380L can include a transition metal nitride, such as TiN, or other conductive material, such as W. The bottom electrode layer 380L can be formed by suitable deposition methods, such as atomic layer deposition, chemical vapor deposition, and the like. In some embodiments, the bottom electrode layer 380L is the same material or substantially the same material as the top electrode 386.

[0194] In some embodiments, the material layers forming the fuse device 38 can be blanket conformal layers deposited sequentially and following the shape of the opening 37. FIG. 3C As shown, a mask layer 370 is formed on the layers 380L, 382L, 384L, 386. The mask layer 370 is similar in many respects to the mask layer 170 of FIG. 2. FIG. 1D

[0195] In some embodiments, portions of the mask layer 370 on the opening 37 are removed by suitable removal methods, such as chemical mechanical polishing. After chemical mechanical polishing, the upper surface of the bottom electrode layer 380L outside the opening 37 is exposed. FIG. 3D In some embodiments, the material layers forming the fuse device 38 can be blanket conformal layers deposited sequentially and following the shape of the opening 37.

[0196] FIG. 3E ​​​​In this process, a portion of the top electrode 386 is exposed via a suitable etching method to expose the electrode contact portion 386C of the top electrode 386. For example, a patterned mask may be formed and covers the top electrode 386 and the mask layer 370, and has an opening corresponding to the electrode contact portion 386C. (See reference...) FIG. 1I The bottom electrode layer 380L, phase change material layer 382L, and heating layer 384L are exposed by patterned mask etching. The electrode contact portion 386C is exposed to form the bottom electrode 380, phase change material layer 382, ​​and heating layer 384 of the fuse device 38.

[0197] exist FIG. 3F In the process of exposing the electrode contact portion 386C, a second dielectric layer 372L is formed on the electrode contact portion 386C, the bottom electrode 380, and the masking layer 370 in the opening 37. The second dielectric layer 372L can be connected to the reference... FIG. 1A The first dielectric layer 160 is similar.

[0198] exist FIG. 3G In the process, after the second dielectric layer 372L is formed, a suitable removal method, such as chemical mechanical polishing, is used to remove a portion of the second dielectric layer 372L above the bottom electrode 380, leaving the second dielectric layer 372B on the electrode contact portion 386C. After chemical mechanical polishing, the upper surfaces of the second dielectric layer 372B, the bottom electrode 380, and the masking layer 370 can be coplanar.

[0199] exist FIG. 3H In the process of planarizing the second dielectric layer 372B, the bottom electrode 380, and the masking layer 370, an insulating layer 374 is formed on the planarized upper surface of the second dielectric layer 372B, the bottom electrode 380, and the masking layer 370. The insulating layer 374L is similar in many respects to the reference [reference material]. FIG. 1G Similar to the insulating layer 174 described herein. The insulating layer 374L provides electronic insulation and physical isolation between the fuse device 38 and the gate electrode layer 368 formed by subsequent methods.

[0200] exist FIGS. 3I-3K In this process, an oxide semiconductor channel 364 is formed on the fuse device 38, corresponding to operation 2040 of method 2000.

[0201] exist FIG. 3I An opening 35 is formed extending through the insulating layer 374. The opening 35 is extended by removing the masking layer 370. FIG. 3IIn some embodiments, the sidewalls of the insulating layer 374 and the corner regions of the bottom electrode 380 are not substantially aligned in the vertical direction. For example, the sidewalls of the insulating layer 374 are slightly recessed from the corner regions, so that at least a portion of the upper surface of the bottom electrode 380 is exposed through the opening 35. In some embodiments, the sidewalls of the insulating layer 374 and the corner regions of the bottom electrode 380 are directly aligned. The formation of the opening 35 can include a first etch that can damage the insulating layer 374, followed by a second etch that removes the masking layer 370. The first etch can be a non-isotropic etch, such as reactive ion etching or inductively coupled plasma through a patterned mask. The second etch can be non-isotropic or isotropic, such as reactive ion etching, inductively coupled plasma, wet etching, or other suitable etch that is selective to the masking layer 370 material without substantially attacking the insulating layer 374 material.

[0202] In some embodiments, the oxide semiconductor layer 364L is formed in the opening 35 and on the insulating layer 374 after the formation of the opening 35. The oxide semiconductor layer 364L can be similar in many respects to the oxide semiconductor layer 164L described with reference to FIGS. 1A-1C, and can be or include indium gallium zinc oxide or other suitable oxide semiconductor. FIG. 3J FIG. 1A In some embodiments, the oxide semiconductor layer 364L is patterned to form a channel 364 after the formation of the oxide semiconductor layer 364L. The channel 364 can include a lower portion that is lower than the upper surface of the insulating layer 374 and in contact with the fuse device 38, and an upper portion that protrudes above the insulating layer 374. The upper portion can have a width in the X-axis direction that exceeds the width of the lower portion in the X-axis direction. For example, the upper portion can partially cover the upper surface of the insulating layer 374. The lower portion can follow the shape of the opening 35. The upper portion can have the same or different shape (e.g., in a cross-sectional view in the XY plane) as the lower portion. For example, the lower portion can have a conical shape and the upper portion can have a cylindrical shape.

[0203] In some embodiments, the gate structure 36 is formed adjacent to the channel 364, corresponding to operation 2050 of the method 2000. FIG. 3K In some embodiments, the gate dielectric layer 366L and the gate conductive layer 368L are formed on the upper portion of the channel 364. The formation of the gate dielectric layer 366L and the gate conductive layer 368L can be similar in many respects to the formation of the gate dielectric layer 166L and the gate conductive layer 168L described with reference to FIGS. 1A-1C. The gate dielectric layer 366L can cover the upper surface and sidewalls of the sidewalls of the channel 364 and the upper surface of the insulating layer 374. The gate conductive layer 368L covers the gate dielectric layer 366L.

[0204] FIGS. 3L-3P In some embodiments, the gate dielectric layer 366L and the gate conductive layer 368L are formed on the upper portion of the channel 364. The formation of the gate dielectric layer 366L and the gate conductive layer 368L can be similar in many respects to the formation of the gate dielectric layer 166L and the gate conductive layer 168L described with reference to FIGS. 1A-1C. The gate dielectric layer 366L can cover the upper surface and sidewalls of the sidewalls of the channel 364 and the upper surface of the insulating layer 374. The gate conductive layer 368L covers the gate dielectric layer 366L.

[0205] In some embodiments, the gate dielectric layer 366L and the gate conductive layer 368L are formed on the upper portion of the channel 364. The formation of the gate dielectric layer 366L and the gate conductive layer 368L can be similar in many respects to the formation of the gate dielectric layer 166L and the gate conductive layer 168L described with reference to FIGS. 1A-1C. The gate dielectric layer 366L can cover the upper surface and sidewalls of the sidewalls of the channel 364 and the upper surface of the insulating layer 374. The gate conductive layer 368L covers the gate dielectric layer 366L. FIG. 3L FIG. 1C In some embodiments, the gate dielectric layer 366L and the gate conductive layer 368L are formed on the upper portion of the channel 364. The formation of the gate dielectric layer 366L and the gate conductive layer 368L can be similar in many respects to the formation of the gate dielectric layer 166L and the gate conductive layer 168L described with reference to FIGS. 1A-1C. The gate dielectric layer 366L can cover the upper surface and sidewalls of the sidewalls of the channel 364 and the upper surface of the insulating layer 374. The gate conductive layer 368L covers the gate dielectric layer 366L. ​​​

[0206] In FIG. 3M , the patterned gate conductive layer 368L and the gate dielectric layer 366L to remove portions of the gate conductive layer 368L and the gate dielectric layer 366L that overlap the electrode contact portion 386C of the top electrode 386. By removing the portions that overlap the electrode contact portion 386C, the gate conductive layer 368L' and the gate dielectric layer 366L' are formed.

[0207] In FIG. 3N , a third dielectric layer 392L is formed to cover the gate conductive layer 368L' and the insulating layer 374. The formation of the third dielectric layer 392L is similar in many respects to the formation of the first dielectric layer 160 described with reference to FIG. 1A .

[0208] In FIG. 3O , the third dielectric layer 392L is recessed and a third dielectric layer 392 is formed and the exposed portions of the gate conductive layer 368L' and the gate dielectric layer 366L' are exposed. As shown, the upper surface of the third dielectric layer 392 can be lower than the upper surfaces of the channel 364, the gate dielectric layer 366L' and the gate conductive layer 368L'. This facilitates, after the second insulating layer 393 is formed, at least a portion of the channel 364 can protrude above the second insulating layer 393 for the formation of the electrode layer 390L thereon.

[0209] In FIG. 3P , the exposed portions of the gate conductive layer 368L' and the gate dielectric layer 366L' on the third dielectric layer 392 are removed to form the gate electrode layer 368 and the gate dielectric layer 366. Subsequently, the second insulating layer 393 is formed. The second insulating layer 393 is similar in many respects to the insulating layers 174, 374 described with reference to FIGs. 1G and 3H. The second insulating layer 393 can be deposited as a conformal layer to cover the channel 364 and the third dielectric layer 392. Subsequently, portions of the second insulating layer 393 on the upper surface of the channel 364 are removed to form the structure as depicted in FIG. 3P .

[0210] In FIG. 3Q , after the second insulating layer 393 is formed, the electrode layer 390L can be formed on the surfaces of the channel 364 and the second insulating layer 393 that are exposed. The electrode layer 390L is similar in many respects to the first electrode layer 162 described with reference to FIG. 1A .

[0211] In FIG. 3R , the electrode layer 390L is patterned to form the electrode layer 390 to obtain the structure as shown. The electrode layer 390 is in contact with the upper surface of the channel 364 and can be in contact with the sidewalls of the portions of the channel 364 that protrude above the second insulating layer 393. The horizontal portions of the electrode layer 390 are on the upper surface of the second insulating layer 393.

[0212] In FIG. 3S and FIG. 3T corresponding to operation 2060 of method 2000, contact elements are formed that connect to the word lines, bit lines, and ground of the phase change random access memory device's gate structure, source / drain, and fuse device. FIG. 3U is a circuit schematic of a phase change random access memory device 40 according to various embodiments.

[0213] In FIG. 3S , a fourth dielectric layer 352 is formed over the electrode layer 390 and the second insulating layer 393. The fourth dielectric layer 352 is similar in many respects to the first dielectric layer 160 and the dielectric layer 500 described with reference to FIG. 1A and FIG. 1L .

[0214] In FIG. 3T , contact elements 394, 396, 398 are formed. The contact element 394 lands on the electrode layer 390, which can be the gate electrode of the transistor 460 including the channel 364. The contact element 396 extends through the fourth dielectric layer 352, the second insulating layer 393, the third dielectric layer 392, the insulating layer 374, and the second dielectric layer 372B, and lands on the electrode contact portion 386C of the top electrode 386, such as the ground terminal of the phase change resistor 470. The contact element 398 extends through the fourth dielectric layer 352, the second insulating layer 393, and the third dielectric layer 392, and lands on the gate electrode layer 368. The contact elements 394, 396, 398 are similar in many respects to the contact elements 194, 196, 198 described with reference to FIG. 1N .

[0215] FIG. 4A and FIG. 4B are pictorialized cross-sectional views depicting IC devices 10, 10A including a phase change random access memory device 40. The IC devices 10, 10A are similar in many respects to the IC devices 10, 10A described with reference to FIG. 2A , FIG. 2B . The IC devices 10, 10A include a phase change random access memory device 40 instead of a phase change random access memory device 20. The phase change random access memory device 40 can be placed in a front-side interconnect structure 700 or a back-side interconnect structure 800, or both.

[0216] Embodiments can provide benefits. The phase change random access memory devices 20, 40 have a ground resistor (or phase change resistor) stacked on the source / drain to reduce the area of the phase change random access memory devices 20, 40, increasing device density.

[0217] According to at least one embodiment, a vertical phase change memory device includes a device layer and an interconnect structure on the device layer, the interconnect structure including a phase change random access memory (PCRAM) device. The phase change random access memory device includes an electrode layer on the device layer, an oxide semiconductor layer on the electrode layer, a gate structure surrounding the oxide semiconductor layer, an insulating layer on the gate structure, and a phase change resistor. The phase change resistor includes a bottom electrode on the oxide semiconductor layer, a phase change layer on the bottom electrode, and a top electrode on the phase change layer. In some embodiments, the vertical phase change memory device further includes a first contact element, a second contact element, and a third contact element. The first contact element extends through the insulating layer and lands on the electrode layer, the second contact element lands on the top electrode, and the third contact element extends through the insulating layer and lands on the gate structure. In some embodiments, the phase change random access memory device further includes a spacer on sidewalls of the top electrode. In some embodiments, the spacer includes a lower spacer on an upper surface of the insulating layer and on sidewalls of the top electrode, the phase change layer, and the bottom electrode. In some embodiments, the phase change random access memory device includes a heating layer between the phase change layer and the top electrode. In some embodiments, the phase change random access memory device has a sharp profile in a cross-sectional view. In some embodiments, the phase change random access memory device has an M-shaped profile in a cross-sectional view.

[0218] According to at least one embodiment, a vertical phase change memory device includes a device layer and an interconnect structure on the device layer, the interconnect structure including a phase change random access memory (PCRAM) device. The phase change random access memory device includes a phase change resistor, an oxide semiconductor layer on a bottom electrode, a first insulating layer on the phase change resistor, a gate structure on the first insulating layer, the gate structure surrounding the oxide semiconductor layer, a second insulating layer on the gate structure, and an electrode layer on the oxide semiconductor layer above the second insulating layer, wherein the phase change resistor includes a top electrode on the device layer, a phase change layer on the top electrode, and a bottom electrode on the phase change layer. In some embodiments, the vertical phase change memory device further includes a first contact element, a second contact element, and a third contact element. The first contact element extends through the first and second insulating layers and lands on the top electrode, the second contact element lands on the electrode layer, and the third contact element extends through the second insulating layer and lands on the gate structure. In some embodiments, the interconnect structure includes a dielectric layer and an opening in the dielectric layer, and the top electrode, the bottom electrode, the phase change layer, and the oxide semiconductor layer of the phase change random access memory device all extend into the opening. In some embodiments, a second portion of the oxide semiconductor layer above the opening has a width that exceeds a first portion of the oxide semiconductor layer within the opening. In some embodiments, the phase change random access memory device includes a heating layer between the phase change layer and the top electrode. In some embodiments, the vertical phase change memory device further includes a second interconnect structure on a front side of the device layer, wherein the interconnect structure is a backside interconnect structure on a backside of the device layer opposite the front side. In some embodiments, the device layer of the vertical phase change memory device includes a stack of nanoscale channel and source / drain nanoscale transistors. The interconnect structure of the vertical phase change memory device includes a first power rail and a second power rail. The first power rail is connected with the source / drain, the second power rail is on the first power rail, the second power rail is connected with the phase change random access memory device, and the second power rail has a size that exceeds the first power rail.

[0219] According to at least one embodiment, a method of fabricating a vertical phase-change memory includes: forming a device layer on a substrate, forming a first portion of an interconnect structure on the device layer, and forming a phase-change random access memory (PCRAM) device on the first portion. Forming the PCRAM device includes: forming a semiconductor oxide layer, forming a gate structure surrounding the semiconductor oxide layer, and forming a phase-change resistor, wherein the phase-change resistor and the semiconductor oxide layer are stacked in a vertical direction. The method includes forming a second portion of the interconnect structure on the PCRAM device. In some embodiments, the phase-change resistor is formed after the formation of the semiconductor oxide layer. In some embodiments, the method of forming the phase-change resistor includes forming a bottom electrode on the semiconductor oxide layer, forming a phase-change layer on the bottom electrode, and forming a top electrode on the phase-change layer. In some embodiments, the method of forming the phase-change resistor includes forming a bottom electrode, a phase-change layer, and a top electrode having a pointed profile in cross-sectional view. In some embodiments, the method of forming the phase-change resistor includes forming a bottom electrode, a phase-change layer, and a top electrode having an M-shaped profile in cross-sectional view. In some embodiments, the method of forming the first portion of the interconnect structure is to form a first portion of a back-side interconnect structure. The method further includes forming a front-side interconnect structure before forming the first part of the back-side interconnect structure.

[0220] According to at least one embodiment, a vertical phase-change memory device includes: a substrate, a device layer on the substrate, a first portion of an interconnect structure on the device layer, and a phase-change random access memory (PCRAM) device on the first portion. The PCRAM device includes: a semiconductor oxide layer, a gate structure surrounding the semiconductor oxide layer, and a phase-change resistor, wherein the phase-change resistor and the semiconductor oxide layer are stacked in a vertical direction. The vertical phase-change memory includes a second portion of the interconnect structure on the PCRAM device. In some embodiments, the phase-change resistor includes a bottom electrode on the semiconductor oxide layer, a phase-change layer on the bottom electrode, and a top electrode on the phase-change layer.

[0221] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoint of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A perpendicular phase change memory device, comprising: Comprising: a device layer; and an interconnect structure on the device layer, the interconnect structure including a phase change random access memory device, the phase change random access memory device including: an electrode layer on the device layer; an oxide semiconductor layer on the electrode layer; a gate structure surrounding the oxide semiconductor layer; an insulating layer on the gate structure; and a phase change resistor including: a bottom electrode on the oxide semiconductor layer; a phase change layer on the bottom electrode; and a top electrode on the phase change layer.

2. The perpendicular variable change memory device of claim 1, wherein, Further comprising: a first contact element extending through the insulating layer and landing on the electrode layer; a second contact element landing on the top electrode; and a third contact element extending through the insulating layer and landing on the gate structure. wherein the phase change random access memory device has a sharp profile in cross-sectional view.

3. The perpendicular variable change memory device of claim 1, wherein, wherein the phase change random access memory device has an M-shaped profile in cross-sectional view.

4. The perpendicular variable change memory device of claim 1, wherein, Comprising:

5. A perpendicular phase change memory device, comprising: a device layer; and an interconnect structure on the device layer; the interconnect structure including a phase change random access memory device, the phase change random access memory device including: a phase change resistor including: a top electrode on the device layer; a phase change layer on the top electrode; and a bottom electrode on the phase change layer; an oxide semiconductor layer on the bottom electrode; a first insulating layer on the phase change resistor; a gate structure on the first insulating layer, the gate structure surrounding the oxide semiconductor layer; a second insulating layer on the gate structure; and an electrode layer on the oxide semiconductor layer above the second insulating layer. Further comprising:

6. The perpendicular variable change memory device of claim 5, wherein, a first contact element extending through the first and second insulating layers and landing on the top electrode; a second contact element landing on the electrode layer; and a third contact element extending through the second insulating layer and landing on the gate structure. wherein the interconnect structure includes: a dielectric layer and an opening in the dielectric layer; and 7. The perpendicular variable change memory device of claim 5, wherein, the top electrode, the bottom electrode, the phase change layer, and the oxide semiconductor layer of the phase change random access memory device all extend into the opening. Further comprising: a second interconnect structure on a front side of the device layer, wherein the interconnect structure is a backside interconnect structure on a backside of the device layer opposite the front side.

8. The perpendicular variable change memory device of claim 5, wherein, Comprising: a substrate; 9. A perpendicular phase change memory device, comprising: a device layer on the substrate; a first portion of an interconnect structure on the device layer; a phase change random access memory device on the first portion, including: an oxide semiconductor layer; a gate structure surrounding the oxide semiconductor layer; and a phase change resistor, the phase change resistor and the oxide semiconductor layer being vertically stacked, and a second portion of the interconnect structure on the phase change random access memory device. wherein the phase change resistor includes: a bottom electrode on the oxide semiconductor layer; 10. The perpendicular variable change memory device of claim 9, wherein, a phase change layer on the bottom electrode; and a top electrode on the phase change layer. ​ ​

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