IGZO bottom gate device
By using amorphous IGZO materials and optimized gate structure and insulating layer design, combined with wet and dry etching, the problems of uneven threshold distribution and insufficient stability of IGZO devices were solved, thereby improving device performance and stability.
Patent Information
- Application Number
- CN202520157222.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-01-22
AI Technical Summary
In the existing technology, when IGZO is used as a channel material for devices, there are problems such as uneven threshold distribution and insufficient stability.
Amorphous IGZO material is used as the channel layer. Combined with optimized gate structure and insulating layer design, oxide insulating medium such as hafnium oxide insulating layer is used. The process flow is optimized by combining wet and dry etching methods, and high-temperature baking is performed to remove residual water and oxygen, thereby improving the thin film properties.
This achieves a uniform distribution of the device threshold voltage, improves the device's stability and conductivity, reduces the impact of etching byproducts, and ensures the device's high performance and the normal progress of testing and packaging.
Smart Images
Figure CN223859534U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, concretely, especially relates to a IGZO bottom gate device structure. BACKGROUND
[0002] IGZO is a kind of highly N type doped semiconductor material, compared with traditional amorphous silicon film, IGZO film has the advantages of good on-state current uniformity, large band gap, transparency and high carrier mobility, and the electron mobility of IGZO reaches 2~50cm2 / V·s, is 20~50 times of traditional amorphous silicon, smaller device size can be designed at device design level, IGZO has the advantages of small leakage and low power consumption, therefore, using the chip and product made based on IGZO material, with longer endurance time, lower heat advantage.
[0003] However, at present, in the prior art, when IGZO is used as device channel material, there are still technical problems of uneven distribution of device threshold value and insufficient stability.
[0004] Therefore, how to provide an IGZO bottom gate device structure, which can overcome the above technical problems, realize the uniform distribution of device threshold voltage, improve the stability of the device, has become a technical problem to be solved by the person skilled in the art. UTILITY MODEL CONTENTS
[0005] To solve the above technical problems, the utility model provides an IGZO bottom gate device structure, which can overcome the above technical problems, ensure the high performance of the device and the normal test packaging, realize the uniform distribution of device threshold voltage, eliminate the residual water and oxygen in the device and improve the physical and chemical properties of the film, and further optimize the device performance and stability.
[0006] The technical scheme provided by the utility model is as follows:
[0007] The utility model provides an IGZO bottom gate device structure, comprising: a substrate layer structure;Gate layer structure is arranged on the substrate layer structure;Insulating layer structure is covered and arranged on the substrate layer structure and the gate layer structure;Channel layer structure is arranged on the insulating layer structure and located above the gate layer structure, and the channel layer structure is a channel layer structure of semiconductor channel material;Source electrode insulating layer structure and drain electrode insulating layer structure are arranged on the insulating layer structure, the source electrode insulating layer structure is arranged at one end of the channel layer structure, and the drain electrode insulating layer structure is arranged at the other end of the channel layer structure;The insulating layer structure is provided with gate contact opening insulating layer structure, and the gate contact opening insulating layer structure is communicated to the surface of the gate layer structure.
[0008] Further, in a preferred mode of the utility model, the channel layer structure is specifically a channel layer structure of amorphous IGZO material.
[0009] Further, in a preferred mode of the utility model, the insulating layer structure is specifically an oxide insulating medium insulating layer structure.
[0010] Further, in a preferred mode of the utility model, the insulating layer structure is specifically a hafnium oxide insulating layer structure.
[0011] Further, in a preferred mode of the utility model, the substrate layer structure is specifically a silicon oxide substrate layer structure.
[0012] Further, in a preferred mode of the utility model, the gate contact hole insulating layer structure is located above the gate layer structure.
[0013] Further, in a preferred mode of the utility model, the gate layer structure comprises: a gate main body insulating layer structure, a gate connecting section insulating layer structure extending from the gate main body insulating layer structure.
[0014] The gate contact hole insulating layer structure is located above the gate main body insulating layer structure, and the shape area of the gate main body insulating layer structure on the vertical projection plane is greater than the opening shape area of the gate contact hole insulating layer structure.
[0015] Further, in a preferred mode of the utility model, the axis direction of the gate connecting section insulating layer structure is perpendicular to the length direction of the channel layer structure.
[0016] Further, in a preferred mode of the utility model, the source electrode insulating layer structure and the drain electrode insulating layer structure are arranged opposite the axis direction of the gate connecting section insulating layer structure.
[0017] Further, in a preferred mode of the utility model, the thickness value of the gate layer structure is less than 100 nm.
[0018] The thickness value of the insulating layer structure is less than 40 nm.
[0019] The thickness value of the source electrode insulating layer structure and the drain electrode insulating layer structure is less than 150 nm.
[0020] Further, in a preferred mode of the utility model, the thickness value of the gate layer structure is 40-80 nm.
[0021] The thickness value of the insulating layer structure is 10-35 nm.
[0022] The thickness of the source electrode insulation layer structure and the drain electrode insulation layer structure is 80-120nm.
[0023] The utility model provides a kind of IGZO bottom gate device structure, comprising: substrate layer structure;Gate layer structure is arranged on the substrate layer structure;Insulation layer structure is covered and arranged on the substrate layer structure and the gate layer structure;Channel layer structure is arranged on the insulation layer structure, and located above the gate layer structure, the channel layer structure is the channel layer structure of semiconductor channel material;Source electrode insulation layer structure and drain electrode insulation layer structure are arranged on the insulation layer structure, the source electrode insulation layer structure is erected in one end of the channel layer structure, and the drain electrode insulation layer structure is erected in the other end of the channel layer structure;The insulation layer structure is provided with gate contact hole insulation layer structure, and the gate contact hole insulation layer structure is communicated to the surface of the gate layer structure, and the technical scheme provided by the utility model can help to realize the uniform distribution of device threshold voltage, and improve the stability of device structure relative to prior art. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can be obtained according to these drawings without creative labor.
[0025] Figure 1 IGZO bottom gate device main section view schematic diagram provided for the embodiment of the utility model is provided;
[0026] Figure 2 IGZO bottom gate device side section view schematic diagram provided for the embodiment of the utility model is provided;
[0027] Figure 3 The structure of gate layer and channel layer is provided for the embodiment of the utility model and the structure schematic diagram is provided;
[0028] Figure 4 The structure of gate layer and channel layer is provided for the embodiment of the utility model and the structure schematic diagram is provided;
[0029] Figure 5 IGZO bottom gate device top view schematic diagram provided for the embodiment of the utility model. DETAILED DESCRIPTION
[0030] In order to make the technical scheme of the present application better understood by those skilled in the art, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.
[0031] It should be noted that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or indirectly disposed on the other element; when an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0032] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "first", "second", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the drawings shown, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0033] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple", "several" is two or more, unless otherwise explicitly specified.
[0034] It should be understood that the structures, proportions, sizes, etc. shown in the drawings of the present application are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and do not define the limiting conditions for the implementation of the present application, and therefore do not have technical substantive significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects that can be produced by the present application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present application.
[0035] As Figures 1 to 5The utility model provides a kind of IGZO bottom gate device structure, it specifically includes: substrate layer structure 1;Gate layer structure 2 being arranged on the substrate layer structure 1;Insulating layer structure 3 is covered and arranged on the substrate layer structure 1 and the gate layer structure 2;Channel layer structure 4 is arranged on the insulating layer structure 3, and located above the gate layer structure 2, the channel layer structure 4 is the channel layer structure of semiconductor channel material;Source electrode 501 and drain electrode 502 are arranged on the insulating layer structure 3, the source electrode 501 is arranged in one end of the channel layer structure 4, and the drain electrode 502 is arranged in the other end of the channel layer structure 4;The insulating layer structure 3 is provided with gate contact opening 301, the gate contact opening 301 is communicated to the surface of the gate layer structure 2, and the technical scheme provided by the utility model can help to realize the uniform distribution of device threshold voltage, and the stability of device structure is improved compared with prior art.
[0036] The technical scheme of the utility model is specifically described in connection with embodiments as follows:
[0037] Specifically, in the embodiment of the utility model, the channel layer structure 4 is specifically the channel layer structure of amorphous IGZO material.
[0038] Specifically, in the embodiment of the utility model, the insulating layer structure 3 is specifically oxide insulating medium insulating layer structure.
[0039] Specifically, in the embodiment of the utility model, the insulating layer structure 3 is specifically hafnium oxide insulating layer structure.
[0040] In the embodiment of the utility model, oxide insulating medium, especially hafnium oxide insulating layer, has excellent insulating performance and chemical stability, can further reduce the influence of water and oxygen on IGZO channel layer compared with prior art, and improve the reliability and stability of device.
[0041] Specifically, in the embodiment of the utility model, the substrate layer structure 1 is specifically silicon oxide substrate layer structure.
[0042] Specifically, in the embodiment of the utility model, the gate contact opening 301 is located above the gate layer structure 2.
[0043] In the embodiment of the utility model, source electrode and drain electrode are arranged in two ends of channel layer respectively, and are arranged opposite to gate connection section axial direction, compared with prior art, current can be uniformly flowed in channel layer, and the conductivity of device is further improved.
[0044] Specifically, in the embodiment of the utility model, the gate layer structure 2 includes: gate main body 201, the gate connecting section 202 that extends from the gate main body 201;
[0045] The gate contact hole 301 is located above the gate main body 201, the shape area of the gate main body 201 on the vertical projection plane is greater than the opening shape area of the gate contact hole 301, in the embodiment of the utility model, the flexibility and reliability of gate control are improved by optimizing the gate structure.
[0046] Specifically, in the embodiment of the utility model, the axis direction of the gate connecting section 202 is perpendicular to the length direction of the channel layer structure 4.
[0047] Specifically, in the embodiment of the utility model, the source electrode 501 and the drain electrode 502 are arranged opposite the axis direction of the gate connecting section 202.
[0048] Specifically, in the embodiment of the utility model, the thickness value of the gate layer structure 2 is less than 100nm;
[0049] The thickness value of the insulating layer structure 3 is less than 40nm;
[0050] The thickness value of the source electrode 501 and drain electrode 502 is less than 150nm.
[0051] More specifically, in a preferred mode of the utility model, the thickness value of the gate layer structure is 40~80nm;
[0052] The thickness value of the insulating layer structure is 10~35nm;
[0053] The thickness value of the source electrode insulating layer structure and drain electrode insulating layer structure is 80~120nm.
[0054] To elaborate further, IGZO is a highly N-type doped semiconductor material, a type of field-effect transistor. Compared to traditional amorphous silicon thin films, IGZO films offer advantages such as better on-state current uniformity, a larger bandgap, transparency, and higher carrier mobility. IGZO's electron mobility reaches 2–50 cm² / V·s, which is 20–50 times that of traditional amorphous silicon, allowing for smaller device sizes in device design. IGZO also boasts low leakage current and low power consumption, resulting in chips and products made from IGZO materials that offer longer battery life and lower heat generation. Furthermore, IGZO-related manufacturing processes are relatively simple and low-cost, and are compatible with traditional silicon-based processes. However, the existing technology has the following technical problems: when IGZO is used as a device channel material, the device threshold distribution is uneven and the threshold is generally negative; conventional dry and wet etching techniques often result in secondary deposition of etching byproducts when etching hafnium oxide, which affects subsequent device testing and packaging; IGZO is extremely sensitive to water and oxygen and is prone to performance instability in atmospheric environments.
[0055] Specifically, in the embodiment of the utility model, using silicon oxide piece, using double layer glue technology exposure need to peel off the gate layer, then using electron beam equipment deposit gate metal (titanium + palladium), thickness need to control within 100nm can, after coating film is completed, put into stripping solution and remove photoresist layer and metal, put the device of gate coating film into atomic layer deposition equipment, deposit hafnium oxide film, need to control within 40nm, after hafnium oxide dielectric layer growth is completed, put into magnetron sputtering coating film equipment, whole piece carries out IGZO coating film, using gas is AR2+O2, AR2 flow is at 40~80SCCM, O2 flow is at 0.5~2SCCM can. After coating film is completed, using double layer glue technology carries out patterning on IGZO, after patterning is completed, using dilute hydrochloric acid solution to wet etch IGZO, only keep device channel part, using double layer glue technology exposure need to peel off the source electrode metal and drain electrode metal layer, then using electron beam equipment deposit source electrode and drain electrode metal (titanium + gold) after put into ICP etching equipment, thickness need to control within 150nm can, after coating film is completed, put into stripping solution and remove photoresist layer and metal, then using double layer glue technology exposure the part that gate metal needs to expose, using dilute hydrofluoric acid solution to wet etch hafnium oxide dielectric layer on gate electrode, after hydrofluoric acid wet etching, put into ICP etching equipment, using fluorine-based gas combination to dry etching by-product and a small amount of residual hafnium oxide produced by wet etching, etching time control is within 30S-120S, etching power can be controlled between 20W-60W, after device fabrication, using the heating plate to the whole wafer high-temperature baking, remove the water and oxygen remaining in the device in the processing process and eliminate defects, temperature control is between 200~300 degrees Celsius, time control is within 30~60MIN can.
[0056] Compared with the prior art, the IGZO bottom gate device structure provided by the embodiments of the present application adopts amorphous IGZO material as the channel layer, combines the optimized gate structure and insulating layer design, improves the conductivity and stability of the device, realizes uniform distribution of the threshold voltage of the device, adjusts the threshold value to a smaller positive bias value, reduces the problem of negative bias distribution, adopts the method of combining wet etching and dry etching, reduces the byproduct deposition phenomenon during hafnium oxide etching, ensures high performance of the device and normal testing and packaging, uses oxide insulating medium as the insulating layer, strictly controls the material thickness and process optimization, improves the reliability of the device, performs high-temperature baking treatment after device processing, removes residual water and oxygen in the device, improves the physical and chemical properties of the thin film, and further improves the device performance and stability.
[0057] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An IGZO bottom-gate device, characterized by, The IGZO bottom-gate device comprises: a substrate layer structure (1); a gate layer structure (2) arranged on the substrate layer structure (1); an insulating layer structure (3) arranged on the substrate layer structure (1) and the gate layer structure (2); a channel layer structure (4) arranged on the insulating layer structure (3) and above the gate layer structure (2), wherein the channel layer structure (4) is specifically a channel layer structure of a semiconductor channel material; a source electrode (501) and a drain electrode (502) arranged on the insulating layer structure (3), wherein the source electrode (501) is arranged on one end of the channel layer structure (4), and the drain electrode (502) is arranged on the other end of the channel layer structure (4); the insulating layer structure (3) is provided with a gate contact opening (301) which is communicated to the surface of the gate layer structure (2).
2. The IGZO bottom-gate device of claim 1, wherein, The channel layer structure (4) is specifically a channel layer structure of amorphous IGZO material.
3. The IGZO bottom-gate device of claim 1, wherein, The insulating layer structure (3) is specifically an insulating layer structure of oxide insulating medium.
4. The IGZO bottom-gate device according to claim 3, wherein the insulating layer structure (3) is specifically a hafnium oxide insulating layer structure.
5. The IGZO bottom-gate device according to claim 1, wherein the substrate layer structure (1) is specifically a silicon oxide substrate layer structure.
6. The IGZO bottom-gate device according to any one of claims 1 to 5, wherein the gate contact opening (301) is located above the gate layer structure (2).
7. The IGZO bottom-gate device according to claim 6, wherein the gate layer structure (2) comprises a gate body (201) and a gate connecting segment (202) extending from the gate body (201); the gate contact opening (301) is located above the gate body (201); and the shape area of the gate body (201) in a vertical projection plane is greater than the opening shape area of the gate contact opening (301).
8. The IGZO bottom-gate device according to claim 7, wherein the length direction of the channel layer structure (4) is perpendicular to the axis direction of the gate connecting segment (202).
9. The IGZO bottom-gate device according to claim 7, wherein the source electrode (501) and the drain electrode (502) are arranged opposite to the axis direction of the gate connecting segment (202).
10. The IGZO bottom-gate device according to any one of claims 1 to 5, wherein the thickness value of the gate layer structure (2) is less than 100 nm; the thickness value of the insulating layer structure (3) is less than 40 nm; the thickness value of the source electrode (501) and the drain electrode (502) is less than 150 nm.