Semiconductor device

Abstract

The utility model provides a semiconductor device, and relates to the technical field of micro electro mechanical manufacturing, the semiconductor device comprises a glass substrate, a heightening layer, a semiconductor layer and a grid electrode, the heightening layer is located at one side of the glass substrate; a partial region of the semiconductor layer is located on one side, far away from the substrate, of the heightening layer, the semiconductor layer comprises a first semiconductor pattern and a second semiconductor pattern, and orthographic projections of the first semiconductor pattern and the second semiconductor pattern on the glass substrate have an overlapping region; the gate is located at one side of the semiconductor layer away from the glass substrate; the orthographic projections of the side surface of the heightening layer, the overlapping region and the grid electrode on the glass substrate are at least partially overlapped; the semiconductor device is good in performance and high in integration level.

Description

Technical Field

[0001] This application relates to the field of microelectromechanical manufacturing, and more particularly to a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor technology, the requirements for the performance and integration of semiconductor devices are becoming increasingly stringent. In existing semiconductor device structures, optimizing the layout of each layer to improve device performance and reduce costs has become a key research focus. Currently common semiconductor device structures still have shortcomings in some aspects; for example, interactions between different film layers may lead to signal interference, or the structural design may not be conducive to further improving integration.

[0003] This application aims to provide a novel semiconductor device structure to solve the aforementioned problems existing in related technologies. Utility Model Content

[0004] This application provides a semiconductor device designed to improve the performance and integration of semiconductor devices through a unique structural design.

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a semiconductor device, the semiconductor device comprising:

[0007] Glass substrate;

[0008] A padding layer is located on one side of the glass substrate;

[0009] A semiconductor layer, a portion of which is located on the side of the pad layer away from the glass substrate, the semiconductor layer including a first semiconductor pattern and a second semiconductor pattern, the orthographic projections of the first semiconductor pattern and the second semiconductor pattern on the glass substrate having an overlapping area;

[0010] The gate is located on the side of the semiconductor layer away from the glass substrate;

[0011] Wherein, the side surface of the pad layer, the overlapping area, and the orthogonal projection of the gate onto the glass substrate at least partially overlap.

[0012] In some semiconductor devices provided in this application, the pad layer includes a first side, a second side, and a first surface on the side away from the glass substrate, wherein the first surface connects the first side and the second side;

[0013] The first semiconductor pattern covers the first surface, the first side surface and the second side surface, and extends onto the glass substrate on a side of the first side surface away from the second side surface; and the second semiconductor pattern covers a partial region of the first surface and a portion of the first semiconductor pattern on the second side surface, and extends onto the glass substrate on a side of the second side surface away from the first side surface.

[0014] The gate covers at least a partial region of the first surface and the second side surface.

[0015] In some semiconductor devices provided by the present application, the first semiconductor pattern and the second semiconductor pattern directly contact at the position of the second side surface.

[0016] In some semiconductor devices provided by the present application, the semiconductor device further comprises a first protective layer and a second protective layer, the first protective layer covers a partial region of the first semiconductor pattern, and the second protective layer covers the second semiconductor pattern.

[0017] The first protective layer and the second protective layer contact and connect at the position of the first surface, and the orthographic projections of the first protective layer and the second protective layer on the glass substrate overlap.

[0018] In some semiconductor devices provided by the present application, the first protective layer and the second semiconductor pattern contact at the position of the first surface, and the second protective layer covers the second semiconductor pattern and a partial region of the first protective layer on the first surface.

[0019] In some semiconductor devices provided by the present application, the gate covers the second side surface and an overlapping position of the first protective layer and the second protective layer.

[0020] In some semiconductor devices provided by the present application, the material of the first semiconductor pattern is carbon nanotube, and the material of the second semiconductor pattern is metal oxide.

[0021] In some semiconductor devices provided by the present application, the first protective layer comprises a first sub-layer and a second sub-layer, and the second sub-layer is located on a side of the first sub-layer away from the first semiconductor pattern.

[0022] In some semiconductor devices provided by the present application, the material of the first sub-layer comprises rare earth oxide, the material of the second sub-layer comprises aluminum oxide, and the material of the second protective layer comprises at least one of aluminum oxide and hafnium oxide.

[0023] In some semiconductor devices provided by the present application, the material of the first semiconductor pattern is metal oxide, and the material of the second semiconductor pattern is carbon nanotube.

[0024] In some semiconductor devices provided by the present application, the second protective layer comprises a first sub-layer and a second sub-layer, and the second sub-layer is located on the side of the first sub-layer away from the second semiconductor pattern.

[0025] In some semiconductor devices provided by the present application, the material of the first sub-layer comprises rare earth oxide, and the material of the second sub-layer comprises aluminum oxide; and the material of the first protective layer comprises at least one of aluminum oxide and hafnium oxide.

[0026] In some semiconductor devices provided by the present application, the semiconductor device further comprises a passivation layer and a source-drain conductive layer, the passivation layer is located on the side of the gate layer away from the glass substrate, and the passivation layer covers the gate layer, the first protective layer and the second protective layer.

[0027] The source-drain conductive layer is located on the side of the passivation layer away from the glass substrate, and the source-drain conductive layer comprises a source electrode and a drain electrode, wherein one of the source electrode and the drain electrode is electrically connected to the first semiconductor pattern, and the other of the source electrode and the drain electrode is electrically connected to the second semiconductor pattern.

[0028] In some semiconductor devices provided by the present application, the second side surface comprises at least one of a plane, a curved surface, and a bending surface formed by a plurality of planes.

[0029] In some semiconductor devices provided by the present application, the second side surface is in a stepped shape along a cross section parallel to the normal direction of the glass substrate.

[0030] In some semiconductor devices provided by the present application, the material of the cushion layer comprises at least one of silicon nitride, silicon oxide or silicon oxynitride.

[0031] In a second aspect, embodiments of the present application provide a method for manufacturing a semiconductor device, applied to manufacture the semiconductor device of any one of the first aspect, the method comprising:

[0032] providing a glass substrate;

[0033] forming a cushion layer on the glass substrate; the cushion layer comprises a first side surface, a second side surface, and a first surface away from the glass substrate, the first surface connecting the first side surface and the second side surface;

[0034] forming a first semiconductor pattern on the elevation layer, wherein the first semiconductor pattern covers the first surface, the first side surface and the second side surface and extends to the glass substrate on a side of the first side surface away from the second side surface;

[0035] forming a second semiconductor pattern on the elevation layer, wherein the second semiconductor pattern covers a partial area of the first surface and a part of the first semiconductor pattern on the second side surface and extends to the glass substrate on a side of the second side surface away from the first side surface;

[0036] forming a gate electrode covering the second side surface and a partial area of the first surface.

[0037] The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a glass substrate, an elevation layer, a semiconductor layer and a gate electrode. The elevation layer is located on one side of the glass substrate. A partial area of the semiconductor layer is located on a side of the elevation layer away from the substrate. The semiconductor layer comprises a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern have an overlapping area in orthographic projection on the glass substrate. The gate electrode is located on a side of the semiconductor layer away from the glass substrate. The side of the elevation layer, the overlapping area and the gate electrode at least partially overlap in orthographic projection on the glass substrate.

[0038] Through the structural design of the application, firstly, the signal interference between different film layers in the semiconductor device can be effectively reduced. For example, by setting the glass substrate, the influence of the silicon substrate on the channel of the semiconductor device in the related art is eliminated, the parasitic capacitance is reduced, and thus the response speed of the device is improved. Secondly, by setting the elevation layer and the overlapping area of the side of the elevation layer, the first semiconductor pattern and the second semiconductor pattern, and the gate electrode in orthographic projection on the glass substrate at least partially overlap, the tunneling area of the semiconductor device is located on the side of the elevation layer, the area of the tunneling area is greatly increased, the tunneling probability of the semiconductor device is improved, and thus the tunneling current of the semiconductor device is improved. In addition, after the elevation layer is set, the channel is set on the side of the elevation layer, the projection area on the glass substrate is unchanged, and the channel length is improved. Therefore, the integration of the semiconductor device is improved, and it is possible to realize a smaller and higher performance semiconductor device.

[0039] The above description is only a summary of the technical scheme of the application. In order to more clearly understand the technical means of the application, the specific embodiments of the application can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following specific embodiments of the application are described. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without any creative effort.

[0041] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor device is provided for the embodiments of the present application.

[0042] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device is provided for the embodiments of the present application. Figure 1 A schematic diagram of a cross-sectional structure along the A1A2 direction is provided for the embodiments of the present application.

[0043] Figures 3-5 A schematic diagram of a cross-sectional structure of a semiconductor device is provided for the embodiments of the present application.

[0044] Figure 6 A schematic diagram of an off-state energy level of a semiconductor device is provided for the embodiments of the present application.

[0045] Figure 7 A schematic diagram of an on-state energy level of a semiconductor device is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of the present application.

[0047] Unless otherwise required by the context, the term "comprises" is to be interpreted as open, inclusive, meaning "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that the specific feature, structure, material or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are partially referred to as "first", "second", etc. only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0049] The terms "parallel", "perpendicular", and "same" used in the embodiments of the present application include not only the strict "parallel", "perpendicular", and "same", but also "approximately parallel", "approximately perpendicular", and "approximately same" with a certain error, which, taking into account the measurement and the error related to the measurement of a specific quantity (for example, the limitation of the measurement system), represents the acceptable deviation range for a specific value determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value. "At least one" means one or more, and "a plurality of" means at least two.

[0050] The "same layer" in the embodiments of the present application refers to the relationship between a plurality of film layers formed by the same material after the same step (for example, one patterning process). Here, "same layer" does not always mean that the thicknesses of the plurality of film layers are the same or that the heights of the plurality of film layers in a cross-sectional view are the same. The polygons in the present specification are not strictly polygons, but can be approximately triangular, parallelogram, trapezoidal, pentagonal, or hexagonal, and there can be some small deformations due to tolerances.

[0051] In the present specification, "electrically connected" and "coupled" include the case where the constituent elements are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of an electrical signal between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0052] With the rapid development of semiconductor technology, the performance requirements for semiconductor devices are becoming increasingly stringent, especially in terms of power consumption control and integration improvement. In CMOS (Complementary Metal Oxide Semiconductor) circuits, reducing power consumption is one of the key research directions, and tunneling field effect transistors, which can reduce sub-threshold swing and effectively reduce power consumption, have become an important research branch in this field.

[0053] Traditionally, silicon materials are widely used in semiconductor devices, but as technology evolves, their limitations gradually emerge. In contrast, glass materials exhibit many unique advantages. Glass is low in cost, can be made in large areas, and has good optical transmittance, especially at high frequencies, with low dielectric loss, which has a significant advantage in photonic chip applications, especially in optoelectronic hybrid chip applications. Therefore, developing glass-based active devices has become an important trend in the semiconductor field.

[0054] In addition to the advantages in cost and optical properties, similar to SOI (Silicon-On-Insulator) technology, glass substrate also has the following advantages: first, using glass substrate does not need to be N / P well doped, which effectively reduces the influence of random doping fluctuation on threshold voltage, thereby significantly increasing the stability of the device. Second, glass substrate eliminates the influence of the substrate on the channel, greatly reduces the parasitic capacitance, and can greatly improve the response speed of the device. Combined with the low loss characteristics of glass itself, in high frequency application scenarios, glass-based semiconductor devices have more advantages than traditional devices, and the cost is lower than SOI, and it is easier to realize large-area production.

[0055] Based on this, the application provides a new type of glass-based semiconductor device and a preparation method thereof. The semiconductor device and the preparation method thereof provided by the application will be specifically introduced and described below with reference to the drawings.

[0056] The embodiment of the application provides a semiconductor device, which combines Figure 1 and Figure 2 As shown in the drawings, the semiconductor device comprises:

[0057] a glass substrate 1;

[0058] a pad layer 2 located on one side of the glass substrate 1;

[0059] a semiconductor layer, part of the semiconductor layer is located on the side of the pad layer 2 away from the glass substrate 1, and the semiconductor layer comprises a first semiconductor pattern 3 and a second semiconductor pattern 5, and the first semiconductor pattern 3 and the second semiconductor pattern 5 have an overlapping area in the orthographic projection on the glass substrate 1;

[0060] a gate 7 located on the side of the semiconductor layer away from the glass substrate 1;

[0061] wherein the side surface of the pad layer 2, the overlapping area of the orthographic projection of the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1, and the orthographic projection of the gate 7 on the glass substrate 1 at least partially overlap. Figure 2 For Figure 1 a schematic diagram of the cross-sectional structure along the A1A2 direction.

[0062] The semiconductor device of the application comprises a glass substrate 1, a pad layer 2, a semiconductor layer (comprising a first semiconductor pattern 3 and a second semiconductor pattern 5), and a gate 7. The glass substrate 1 serves as the basic support structure of the entire device, and its characteristics such as low cost, large-area production, and low dielectric loss at high frequency lay the foundation for improving the performance of the device.

[0063] Exemplarily, the glass substrate 1 can be made of high-purity, low-impurity borosilicate glass material, which has excellent flatness and chemical stability, and can provide a stable and reliable support foundation for the entire semiconductor device.

[0064] The elevation layer 2 can also be referred to as a medium layer, which is made of organic or inorganic insulating material. By arranging the elevation layer 2, part of the semiconductor layer is located on the side of the elevation layer 2 away from the glass substrate 1, and the size (such as length and / or area) of the channel in the semiconductor layer can be increased by the elevation layer 2.

[0065] Exemplarily, the elevation layer 2 can be a single-layer film structure; or the elevation layer 2 can include at least two film layers stacked together; and the specific number of film layers can be determined according to the material and design thickness of the elevation layer 2.

[0066] Exemplarily, the material of the elevation layer 2 can be selected from silicon nitride, silicon oxide, silicon oxynitride, silicon nitride / silicon oxide, silicon nitride / silicon oxynitride, or silicon oxide / silicon oxynitride.

[0067] The area of the overlapping region of the orthographic projection of the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 can be adjusted by adjusting the shape and height of the elevation layer 2.

[0068] Exemplarily, the material of one of the first semiconductor pattern 3 and the second semiconductor pattern 5 is carbon nanotube, and the material of the other is metal oxide (such as indium gallium zinc oxide).

[0069] It should be noted that the above semiconductor device is a heterojunction tunnel transistor, which is a transistor based on quantum tunneling effect and heterojunction structure. In this transistor, the heterojunction formed by different semiconductor materials is used to control the tunneling process of electrons.

[0070] Quantum tunneling effect refers to the fact that microscopic particles such as electrons have a certain probability of passing through a potential barrier with higher energy than themselves. The existence of heterojunction can adjust the probability and difficulty of electron tunneling by changing the energy band structure and electric field distribution, thereby realizing the control of the on and off states of the transistor to achieve circuit functions such as amplification and switching.

[0071] The gate 7 is arranged on the side of the semiconductor layer away from the glass substrate 1, and is used to control the tunneling behavior of electrons and form a conductive channel between the source and the drain.

[0072] In the exemplary embodiments, the at least partially overlapping of the overlapping area of the normal projection of the side surface of the pad layer 2, the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 and the normal projection of the gate 7 on the glass substrate 1 means that there is an overlapping area of the normal projection of the side surface of the pad layer 2, the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 and the normal projection of the gate 7 on the glass substrate 1, but the area and size of the overlapping area of the three are not limited.

[0073] For example, the overlapping area of the normal projection of the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 and the side surface of the pad layer 2 is completely overlapped, and the gate 7 covers the overlapping area of the normal projection of the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 and the side surface of the pad layer 2. Wherein, "cover" means to cover one object with another object, so that the covered object is not exposed; it can be understood that the area of the gate 7 can be greater than or equal to the area of the overlapping area of the normal projection of the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 and the area of the side surface of the pad layer 2.

[0074] As shown in Figure 1 , through the structural design of the present application, first, the signal interference between different film layers in the semiconductor device can be effectively reduced, for example, by providing the glass substrate 1, the influence of the silicon substrate on the channel of the semiconductor device in the related art is eliminated, the parasitic capacitance is reduced, and the response speed of the device is improved; second, by providing the pad layer 2, and by providing the at least partially overlapping of the overlapping area of the side surface of the pad layer 2, the first semiconductor pattern 3 and the second semiconductor pattern 5 on the glass substrate 1 and the normal projection of the gate 7 on the glass substrate 1, the tunneling region of the semiconductor device is located at the side surface of the pad layer 2, which greatly increases the area of the tunneling region and improves the tunneling probability of the semiconductor device, thereby improving the tunneling current of the semiconductor device; in addition, after the pad layer 2 is provided, the channel is arranged at the side surface of the pad layer 2, and the projection area on the glass substrate 1 is unchanged, the channel length is improved, which is beneficial to the design of small-size semiconductor devices and improves the integration of semiconductor devices, and provides the possibility for realizing smaller and higher-performance semiconductor devices.

[0075] Wherein, the channel of the heterojunction tunneling transistor refers to the region between the source and the drain in the transistor, which provides a transmission path for the carriers (electrons or holes).

[0076] In some semiconductor devices provided by the present application, as shown in Figure 2 or Figure 3 , the pad layer 2 comprises a first side surface C1, a second side surface C2 and a first surface B1 away from the glass substrate 1, and the first surface B1 connects the first side surface C1 and the second side surface C2.

[0077] The first semiconductor pattern 3 covers the first surface B1, the first side surface C1 and the second side surface C2, and extends onto the glass substrate 1 on the side of the first side surface C1 away from the second side surface C2; the second semiconductor pattern 5 covers a partial region of the first surface B1 and a portion of the first semiconductor pattern 3 located on the second side surface C2, and extends onto the glass substrate 1 on the side of the second side surface C2 away from the first side surface C1; the gate 7 covers at least a partial region of the first surface B1 and the second side surface C2.

[0078] Here, whether the first side surface C1 and the second side surface C2 are planar is not limited, and for example, at least one of the first side surface C1 and the second side surface C2 can include a planar surface, a curved surface, a combination of multiple planar surfaces, a combination of multiple curved surfaces, or a combination of a planar surface and a curved surface.

[0079] The gate 7 covering at least a partial region of the first surface B1 and the second side surface C2 can include the following cases:

[0080] The first case: as shown in FIG. 1, the gate 7 covers a partial region of the first surface B1 and the second side surface C2; Figure 2

[0081] The second case: the gate 7 covers the first surface B1 and the second side surface C2.

[0082] In the examples of the present application, by setting the gate 7 to cover at least a partial region of the first surface B1 and the second side surface C2, the gate 7 can better control the tunneling behavior of electrons and form a conductive channel between the source and the drain.

[0083] In some semiconductor devices provided by the present application, as shown in FIG. 2, the first semiconductor pattern 3 and the second semiconductor pattern 5 directly contact at the position of the second side surface C2. Figure 2

[0084] In the embodiments of the present application, the tunneling position of the semiconductor device is located at the contact region of the first semiconductor pattern 3 and the second semiconductor pattern 5.

[0085] In some semiconductor devices provided by the present application, as shown in FIG. 3 or FIG. 4, the semiconductor device further includes a first protective layer 4 and a second protective layer 6, the first protective layer 4 covers a partial region of the first semiconductor pattern 3, and the second protective layer 6 covers the second semiconductor pattern 5; Figure 2 Figure 3 The first protective layer 4 and the second protective layer 6 contact and connect at the position of the first surface B1, and the orthographic projections of the first protective layer 4 and the second protective layer 6 on the glass substrate 1 overlap.

[0086] The first protective layer 4 and the second protective layer 6 contact and connect at the position of the first surface B1, and the orthographic projections of the first protective layer 4 and the second protective layer 6 on the glass substrate 1 overlap.

[0087] ​​​The first protective layer 4 covers part of the first semiconductor pattern 3 can include the following cases:

[0088] First, the first protective layer 4 covers the first side surface C1 of the first semiconductor pattern 3.

[0089] Second, as shown in the figure, the first protective layer 4 covers part of the first surface B1 and the first side surface C1 of the first semiconductor pattern 3. Figure 2

[0090] Third, the first protective layer 4 covers the first surface B1 and the first side surface C1 of the first semiconductor pattern 3.

[0091] The first protective layer 4 and the second protective layer 6 are used to isolate the semiconductor layer from the gate 7, so as to avoid direct contact between the semiconductor layer and the gate 7.

[0092] In some semiconductor devices provided by the present application, as shown in the figure, the first protective layer 4 and the second semiconductor pattern 5 are in contact at the position of the first surface B1, and the second protective layer 6 covers the second semiconductor pattern 5 and part of the first protective layer 4 on the first surface B1. Figure 2

[0093] Among them, the first protective layer 4 and the second semiconductor pattern 5 are in contact at the position of the first surface B1, which protects the side surface of the second semiconductor pattern 5, and then the second protective layer 6 covers the second semiconductor pattern 5 and part of the first protective layer 4 on the first surface B1, realizing all-round protection of the first semiconductor pattern 3 and the second semiconductor pattern 5.

[0094] It should be noted that the second protective layer 6 also extends to cover part of the first protective layer 4 on the first surface B1, so that the first protective layer 4 and the second protective layer 6 have an overlapping projection on the glass substrate 1, so that the first protective layer 4 and the second protective layer 6 can avoid appearing gaps at the connection position of the first surface B1 when the process is unstable, and avoid chemical liquid or gas from drilling into the semiconductor layer from the gap to cause corrosion and damage to the semiconductor layer in the subsequent process.

[0095] In some semiconductor devices provided by the present application, as shown in the figure, the gate 7 covers the second side surface C2 and the overlapping position of the first protective layer 4 and the second protective layer 6. Figure 2

[0096] ​​​In the present application, by setting the gate electrode 7 to cover the second side surface C2 and the overlapping position of the first protective layer 4 and the second protective layer 6, the gate electrode 7 can cover the region where the first semiconductor pattern 3 and the second semiconductor pattern 5 contact as much as possible. In this way, when electron tunneling occurs between the first semiconductor pattern 3 and the second semiconductor pattern 5, the gate electrode 7 can better control the tunneling current and form a conductive channel between the source electrode 9 and the drain electrode 10 to generate channel current.

[0097] In some semiconductor devices provided in the present application, as shown in Figure 2 The material of the first semiconductor pattern 3 is carbon nanotube (CNT), and the material of the second semiconductor pattern 5 is metal oxide.

[0098] Carbon nanotube has a unique one-dimensional structure and excellent electrical properties such as high carrier mobility and good conductivity, which provides a guarantee for the high-performance operation of the semiconductor device. In the preparation of the first semiconductor pattern 3, carbon nanotube material can be grown by pulling or immersion method.

[0099] In the case of using the pulling method to prepare carbon nanotube, the preparation process is briefly described as follows: first, immerse the pretreated substrate (such as an Ar plasma treated glass substrate) into the dispersed carbon nanotube solution. Then, slowly pull the substrate at a precisely controlled speed, and repeat this process multiple times. During the pulling process, the carbon nanotubes in the carbon nanotube solution continuously deposit on the substrate surface to form a carbon nanotube film.

[0100] In the case of using the immersion method to prepare carbon nanotube, the preparation process is briefly described as follows: place the pretreated substrate in a container containing carbon nanotube solution and let it stand for a period of time. Carbon nanotubes gradually adsorb on the substrate surface. Then, use organic solvents such as toluene for cleaning and baking to remove the attached organic dispersing substances and increase the adhesion of carbon nanotubes to the substrate, finally forming a carbon nanotube film meeting the electrical performance requirements.

[0101] The material of the second semiconductor pattern 5 is metal oxide, for example, the metal oxide is indium gallium zinc oxide (IGZO). Indium gallium zinc oxide has high electron mobility, good transparency and stability. Physical vapor deposition (PVD) method can be used to deposit IGZO at a specific temperature, pressure and gas atmosphere, and then patterned to form the second semiconductor pattern; or, sputtering method can be used to deposit IGZO, and then etching method can be used for patterning.

[0102] It should be noted that, when the first semiconductor pattern 3 is prepared on the glass substrate 1, the material of the first semiconductor pattern 3 is carbon nanotube, and since the first semiconductor pattern 3 is prepared on the glass substrate 1 without N / P trap doping, the problems of poor electrical stability and poor doping uniformity caused by doping in the carbon nanotube are largely avoided.

[0103] In some semiconductor devices provided by the present application, for Figure 2 In the semiconductor device structure shown in the figure, the first protective layer 4 includes a first sub-layer 41 and a second sub-layer 42, and the second sub-layer 42 is located on the side of the first sub-layer 41 away from the first semiconductor pattern 3.

[0104] In some semiconductor devices provided by the present application, for Figure 2 In the semiconductor device structure shown in the figure, the material of the first sub-layer 41 includes rare earth oxide, and the material of the second sub-layer 42 includes aluminum oxide; and the material of the second protective layer 3 includes at least one of aluminum oxide and hafnium oxide.

[0105] For example, the above-mentioned rare earth oxide can include yttrium oxide (Y2O3).

[0106] Yttrium oxide has a melting point as high as 2410℃ and stable chemical properties, which makes it a substrate material or protective coating in high-temperature environments. In the high-temperature process steps of semiconductor manufacturing, such as epitaxial growth, it can maintain structural integrity and prevent erosion by other substances, ensuring the stability of semiconductor devices in complex manufacturing processes. In addition, yttrium oxide has a high dielectric constant, which can effectively regulate the behavior of electrons in the channel when placed between the gate 7 and the semiconductor layer, improving the switching speed of the transistor and reducing power consumption, thereby improving the overall performance of the semiconductor device.

[0107] In this method, the P region uses a narrow-bandgap CNT material, and the I region and the N region use a wide-bandgap IGZO material. This method does not require doping, avoiding the high-temperature activation process, and is more likely to form a sudden junction compared to tunneling transistors that require doping, thereby improving the tunneling probability.

[0108] It should also be noted that yttrium oxide has a specific crystal structure, and the arrangement of atoms in its lattice affects the distribution of electrons and the energy level state. In this structure, there are some energy states that allow holes to form and move relatively easily. From the perspective of energy band theory, there is a certain band gap between the valence band and the conduction band of yttrium oxide. When excited by external factors, electrons in the valence band may be excited to the conduction band, leaving holes in the valence band. These holes have a certain migration ability and can participate in the process of conduction, exhibiting hole injection characteristics.

[0109] When yttrium oxide is used as a protective layer covering the carbon nanotube material, due to the hole injection property of yttrium oxide, the carbon nanotube material (a narrow band gap material) exhibits P region doping characteristics. Of course, for indium gallium zinc oxide (IGZO) material, oxygen vacancy defects in the indium gallium zinc oxide can be increased by means of plasma treatment (for example, H Plasma) to exhibit N region doping characteristics.

[0110] Aluminum oxide can be used to cover the yttrium oxide surface due to its high temperature resistance (melting point up to 2050℃), low thermal conductivity, large insulation resistance and other characteristics, and can be used as a protective layer together with the yttrium oxide to protect the semiconductor layer.

[0111] Hafnium oxide (HfO2) is an electrical insulator with a band gap of 5.3-5.7eV, which can be used to make insulation layers in electronic devices. In addition, its melting point is as high as 2780-2920K, and it has good thermal stability, which can be used as a substrate material or protective coating in high temperature environments.

[0112] In some semiconductor devices provided by the present application, as shown in Figure 2 , the second protective layer 6 (for example, including at least one of aluminum oxide and hafnium oxide) can be selected from a material with a dielectric constant between 6 and 20 (high-k), for example, at least one of aluminum oxide and hafnium oxide, and its thickness is controlled between 5 and 10nm. In this way, the control ability of the gate 7 on the channel can be increased.

[0113] In some semiconductor devices provided by the present application, as shown in Figure 3 , the material of the first semiconductor pattern 3 is a metal oxide, and the material of the second semiconductor pattern 5 is a carbon nanotube.

[0114] Among them, the metal oxide can be indium gallium zinc oxide (IGZO), and the introduction of indium gallium zinc oxide (IGZO) and carbon nanotube can refer to the description in the foregoing, which will not be repeated here.

[0115] In some semiconductor devices provided by the present application, as shown in Figure 3 , the second protective layer 6 includes a first sub-layer 61 and a second sub-layer 62, and the second sub-layer 62 is located on the side of the first sub-layer 61 away from the second semiconductor pattern 5.

[0116] According to the foregoing embodiments, it can be understood that the protective layer with two sub-layers is arranged on the carbon nanotube material to ensure the high temperature resistance and electrical stability of the carbon nanotube material.

[0117] In some semiconductor devices provided by the present application, in Figure 3 , the material of the first sub-layer 61 includes a rare earth oxide, for example, yttrium oxide, and the material of the second sub-layer 62 includes aluminum oxide; the material of the first protective layer 4 includes at least one of aluminum oxide and hafnium oxide.

[0118] wherein, in Figure 3 the material of the first protective layer 4 can be selected from a material with a dielectric constant between 6 and 20, for example at least one of aluminum oxide and hafnium oxide, and the thickness thereof is controlled to be between 5 and 10 nm. In this way, the control ability of the gate 7 on the channel can be increased.

[0119] It is to be noted that yttrium oxide has a specific crystal structure, and the arrangement of atoms in the crystal lattice thereof affects the distribution of electrons and the energy level state. In this structure, there are some energy states in which holes can be relatively easily formed and moved. From the perspective of energy band theory, there is a certain band gap between the valence band and the conduction band of yttrium oxide. When excited by external factors, the electrons in the valence band can be excited to the conduction band, thereby leaving holes in the valence band. These holes have a certain migration ability and can participate in the process of conduction, thereby exhibiting hole injection characteristics. When yttrium oxide is used as a protective layer covering the carbon nanotube material, the carbon nanotube material exhibits P-type doping characteristics due to the hole injection characteristics of yttrium oxide. Of course, for indium gallium zinc oxide (IGZO) material, the oxygen vacancy defects in the indium gallium zinc oxide can be increased by means of plasma treatment (for example, H Plasma) to exhibit N-type doping characteristics.

[0120] In some semiconductor devices provided by the present application, as shown in Figure 2 and Figure 3 the semiconductor device further comprises a passivation layer 8 and a source-drain conductive layer, the passivation layer 8 is located on the side of the gate layer 7 away from the glass substrate 1, and the passivation layer 8 covers the gate layer 7, the first protective layer 4 and the second protective layer 6.

[0121] The source-drain conductive layer is located on the side of the passivation layer 8 away from the glass substrate 1, and the source-drain conductive layer comprises a source electrode 9 and a drain electrode 10, wherein one of the source electrode 9 and the drain electrode 10 is electrically connected to the first semiconductor pattern 5, and the other of the source electrode 9 and the drain electrode 10 is electrically connected to the second semiconductor pattern 3.

[0122] The passivation layer 8 can be made of an insulating material, for example, an organic insulating material or an inorganic insulating material. The organic insulating material can include resin, and the inorganic insulating material can be silicon nitride, silicon oxide or silicon oxynitride.

[0123] The source-drain conductive layer needs to be made of a material with a high work function, for example, titanium / palladium (Ti / Pd) in a stacked arrangement. In this way, when one of the source electrode or the drain electrode is electrically connected to the carbon nanotube material, the carbon nanotube can further exhibit P-type characteristics, thereby improving the electrical characteristics of the semiconductor device.

[0124] In some semiconductor devices provided by the present application, as shown in Figures 2-5As shown, the second side surface C2 includes at least one of a flat surface, a curved surface, and a bent surface formed by a plurality of flat surfaces.

[0125] In some semiconductor devices provided by the present application, as shown in Figure 4 or Figure 5 As shown, the second side surface C2 is stepped along a cross section parallel to the normal direction of the glass substrate 1.

[0126] In the embodiments of the present application, since the heterojunction tunneling region of the semiconductor device is arranged on the second side surface C2 of the elevation layer 2, by arranging the second side surface C2 to be stepped along a cross section parallel to the normal direction of the glass substrate 1, as shown in the structure of Figure 4 As shown in the structure of

[0127] In some semiconductor devices provided by the present application, the material of the elevation layer 2 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0128] The semiconductor device provided by the embodiments of the present application is a heterojunction tunneling transistor, wherein the core structure of the heterojunction tunneling transistor is a heterojunction, i.e., a junction formed by two different semiconductor materials with different band gaps, for example, the first semiconductor pattern and the second semiconductor pattern form a heterojunction; in the heterojunction tunneling transistor, electrons do not pass through the barrier by diffusion and other methods as in traditional transistors, but use quantum tunneling effect to make tunneling occur at the contact interface of the first semiconductor pattern and the second semiconductor pattern.

[0129] The electron mobility in the heterojunction tunneling transistor is usually higher than that in the homojunction tunneling transistor. This is because the two materials in the heterojunction have different electron structures, and the electron can take advantage of the electron structures of the two materials when passing through the heterojunction, thereby improving the electron mobility. In addition, the barrier width of the heterojunction is smaller, which increases the probability of carrier tunneling, which means that it is beneficial to increase the size of the tunneling current and improve the tunneling current.

[0130] Next, taking the structure shown in Figure 2 as an example, the tunneling mechanism of the above-mentioned heterojunction transistor will be described in conjunction with the drawings:

[0131] When the transistor is working, a voltage of 3 is applied to the drain, and no voltage is applied to the gate 7, as shown in Figure 6As shown, in the region where the first semiconductor pattern and the second semiconductor pattern are in contact (for example, the region where the carbon nanotube CNT is in contact with the IGZO), a downward-bent energy band is generated, and the CNT valence band electrons cannot tunnel to the conduction band of the IGZO, at this time, no tunneling current is generated. When the gate 7 applies a forward voltage, as shown Figure 7 As shown, the IGZO energy band moves downward, when the IGZO conduction band Ec is substantially level with the CNT valence band Ev, the electrons of the CNT valence band Ev begin to tunnel to the IGZO conduction band Ec, at this time, the tunneling current begins to be generated, and with the increase of the gate 7 voltage, the tunneling current begins to increase continuously.

[0132] The conventional tunneling device is point tunneling, that is, the tunneling region is concentrated at the contact point of the P region and the I region channel. The semiconductor device proposed in the present application increases a pad layer 2 for heightening under the channel, and the thickness of the pad layer 2 can be adjusted according to the needs. The tunneling region is the inclined surface region (side surface region) of the pad layer 2, that is, line tunneling, so that the tunneling area can be effectively increased.

[0133] Because quantum tunneling is a very fast process, the heterojunction tunneling transistor has extremely short switching time and can realize high-speed signal processing and data transmission, which has great advantages in high-frequency and high-speed circuit applications, such as in the fields of high-speed communication, radar, etc., which can be used to improve the signal processing speed and bandwidth.

[0134] Compared with the conventional transistor, the heterojunction tunneling transistor can work at a lower voltage under the same working frequency, thereby reducing the power consumption. This is very important for portable electronic devices, large-scale integrated circuits and other application scenarios with strict requirements on power consumption, which helps to prolong the battery life and improve the integration of chips.

[0135] Because the heterojunction tunneling transistor has high sensitivity to small changes in input signals, it can accurately detect and amplify weak signals. It has unique application value in the fields of sensors and weak signal detection, for example, it can be used in biological sensors to detect the weak signal changes of biological molecules, or in radio frequency receiving circuits to improve the detection ability of weak radio frequency signals.

[0136] The embodiment of the present application provides a preparation method of a semiconductor device, which is applied to the preparation of the semiconductor device as described above, and the method comprises the following steps:

[0137] S1, providing a glass substrate 1;

[0138] S2, forming a pad layer 2 on the glass substrate 1; the pad layer 2 comprises a first side surface C1, a second side surface C2, and a first surface B1 away from one side of the glass substrate 1, and the first surface B1 is connected with the first side surface C1 and the second side surface C2;

[0139] It is not limited herein whether the first side surface C1 and the second side surface C2 are planar. For example, at least one of the first side surface C1 and the second side surface C2 can include a planar surface, a curved surface, a combination of multiple planar surfaces, a combination of multiple curved surfaces, or a combination of a planar surface and a curved surface.

[0140] S3, forming a first semiconductor pattern 3 on the elevation layer 2, the first semiconductor pattern 3 covering the first surface B1, the first side surface C1 and the second side surface C2 and extending to the glass substrate 1 on the side of the first side surface C1 away from the second side surface C2;

[0141] In actual applications, after the first semiconductor pattern 3 is formed, a first protective layer 4 can be formed on the first semiconductor pattern 3, the first protective layer 4 covering part of the first semiconductor pattern 3,

[0142] S4, forming a second semiconductor pattern 5 on the elevation layer 2, wherein the second semiconductor pattern 5 covers part of the first surface B1 and part of the first semiconductor pattern 3 on the second side surface C2 and extends to the glass substrate 1 on the side of the second side surface C2 away from the first side surface C1;

[0143] After the second semiconductor pattern 5 is formed, a second protective layer 6 can be formed, the first protective layer 4 and the second semiconductor pattern 5 being in contact at the position of the first surface B1, and the second protective layer 6 covering the second semiconductor pattern 5 and part of the first protective layer 4 on the first surface B1.

[0144] It should be noted that the second protective layer 6 also extends to cover part of the first protective layer 4 on the first surface B1, so that the first protective layer 4 and the second protective layer 6 have an overlapping projection on the glass substrate 1. In this way, when the process is unstable, a gap can be avoided at the connection position of the first protective layer 4 and the second protective layer 6 on the first surface B1, and chemical liquids or gases can be prevented from drilling into the semiconductor layer from the gap to cause corrosion and damage to the semiconductor layer in subsequent processes.

[0145] S5, forming a gate 7, the gate 7 covering at least part of the first surface B1 and the second side surface C2. For example, as shown in Figure 2 the gate 7 covers the second side surface C2 and the overlapping position of the first protective layer 4 and the second protective layer 6.

[0146] For example, as shown in Figure 1As shown, the semiconductor device prepared by the preparation method of the present application can effectively reduce the signal interference between different film layers inside the semiconductor device. For example, by arranging the glass substrate 1, the influence of the silicon substrate on the channel of the semiconductor device in the related art is eliminated, the parasitic capacitance is reduced, and thus the response speed of the device is improved. Secondly, by arranging the raised layer 2 and arranging the overlap area of the side surface of the raised layer 2, the first semiconductor pattern 3 and the second semiconductor pattern 5, and the orthographic projection of the gate 7 on the glass substrate 1 at least partially overlaps, so that the tunneling area of the semiconductor device is located at the side surface of the raised layer 2, which greatly increases the area of the tunneling area and improves the tunneling probability of the semiconductor device, thereby improving the tunneling current of the semiconductor device. In addition, after the raised layer 2 is arranged, the channel length is increased under the condition that the projection area on the glass substrate 1 is unchanged because the channel is arranged at the side surface of the raised layer 2. Therefore, it is beneficial to the design of small-size semiconductor devices and improves the integration of the semiconductor device, which provides the possibility for realizing smaller and higher-performance semiconductor devices.

[0147] The specific preparation method of the semiconductor device will be described below taking the structure shown in the figure as an example. Figure 2

[0148] 1. Form a raised layer 2 on a glass substrate 1, wherein the material of the raised layer 2 can be silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride.

[0149] 2. Grow carbon nanotube (CNT) material by pulling or immersion method, and then etch to form a patterned first semiconductor pattern 3.

[0150] 3. Form a yttrium oxide sublayer and an aluminum oxide sublayer on the carbon nanotube (first semiconductor pattern 3), wherein the first protective layer 4 includes the yttrium oxide sublayer and the aluminum oxide sublayer, the yttrium oxide sublayer covers the carbon nanotube material, and the aluminum oxide sublayer covers the yttrium oxide sublayer.

[0151] 4. Form an IGZO thin film by sputtering process (Sputter) and patternize to obtain a second semiconductor pattern 5; the IGZO covers the part of the carbon nanotube located at the second side surface of the raised layer 2.

[0152] 5. Form a second protective layer 6 on the IGZO.

[0153] In order to increase the control ability of the gate on the channel, the second protective layer 6 can use a high dielectric constant (≥6) material, for example, aluminum oxide (Al2O3) or hafnium oxide (HfO2); the thickness thereof can be as small as possible, for example, 5-10 nm.

[0154] 6. Form a gate, wherein the material of the gate can be at least one of metal, for example, copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti).​

[0155] 7. Forming a passivation layer 8 to isolate the gate 7 and the source / drain conductive layer;

[0156] 8. Forming a source / drain conductive layer; the source / drain conductive layer includes a source 9 and a drain 10.

[0157] It should be noted that the semiconductor device described above can also include other structures and components, and the manufacturing method thereof can also include other steps and processes. The present description only describes the structures and manufacturing methods related to the invention points, and the other structures and manufacturing methods thereof can be referred to the description in the related art.

[0158] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a glass substrate; a spacer layer on one side of the glass substrate; a semiconductor layer, a part of the semiconductor layer is on the side of the spacer layer away from the glass substrate, the semiconductor layer comprises a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern have an overlapping area in the orthographic projection on the glass substrate; a gate on the side of the semiconductor layer away from the glass substrate; wherein the orthographic projection of the side of the spacer layer, the overlapping area and the gate on the glass substrate at least partially overlaps.

2. The semiconductor device of claim 1, wherein The spacer layer comprises a first side, a second side and a first surface on the side away from the glass substrate, the first surface connects the first side and the second side; The first semiconductor pattern covers the first surface, the first side and the second side and extends to the glass substrate on the side of the first side away from the second side; the second semiconductor pattern covers a part of the first surface and a part of the first semiconductor pattern on the second side and extends to the glass substrate on the side of the second side away from the first side; The gate covers at least a part of the first surface and the second side.

3. The semiconductor device of claim 2, wherein, The first semiconductor pattern and the second semiconductor pattern directly contact at the position of the second side.

4. The semiconductor device of claim 3, wherein The semiconductor device further comprises a first protective layer and a second protective layer, the first protective layer covers a part of the first semiconductor pattern, and the second protective layer covers the second semiconductor pattern; The first protective layer and the second protective layer contact and connect at the position of the first surface, and the orthographic projection of the first protective layer and the second protective layer on the glass substrate has an overlapping area.

5. The semiconductor device of claim 4, wherein, The first protective layer and the second semiconductor pattern contact at the position of the first surface, and the second protective layer covers the second semiconductor pattern and a part of the first protective layer on the first surface.

6. The semiconductor device of claim 5, wherein, The gate covers the second side and the overlapping position of the first protective layer and the second protective layer.

7. The semiconductor device of claim 6, wherein, The first protective layer comprises a first sub-layer and a second sub-layer, and the second sub-layer is on the side of the first sub-layer away from the first semiconductor pattern.

8. The semiconductor device of claim 6, wherein, The second protective layer comprises a first sub-layer and a second sub-layer, and the second sub-layer is on the side of the first sub-layer away from the second semiconductor pattern.

9. The semiconductor device according to claim 7 or 8, wherein The semiconductor device further comprises a passivation layer and a source-drain conductive layer, the passivation layer is on the side of the gate layer away from the glass substrate, and the passivation layer covers the gate layer, the first protective layer and the second protective layer; The source-drain conductive layer is on the side of the passivation layer away from the glass substrate, and the source-drain conductive layer comprises a source and a drain, one of the source and the drain is electrically connected with the first semiconductor pattern, and the other of the source and the drain is electrically connected with the second semiconductor pattern.

10. The semiconductor device of claim 2, wherein The second side comprises at least one of a plane, a curved surface and a bending surface formed by a plurality of planes.

11. The semiconductor device of claim 10, wherein, The second side surface is stepped in a cross section parallel to a normal direction of the glass substrate.

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