Display device

Abstract

A display device includes: a light emitting element; and an encapsulation layer on the light emitting element, in which the encapsulation layer includes a first encapsulation layer, a second encapsulation layer on the first encapsulation layer, a third encapsulation layer on the second encapsulation layer, and a fourth encapsulation layer on the third encapsulation layer, and in which the third encapsulation layer includes a void.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0028879, filed on February 28, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Some aspects of embodiments of this disclosure relate to a display device and a method of manufacturing the display device. Background Technology

[0004] With the development of information technology, display devices, as the connection medium between users and information, are becoming increasingly important.

[0005] A display device may include a light-emitting element and an encapsulation layer. The encapsulation layer can cover the light-emitting element and relatively reduce the risk of impurities (e.g., moisture) penetrating into the display device from the outside. Accordingly, when the encapsulation layer is not properly formed, the defect rate of the display device may increase.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Utility Model Content

[0007] Some aspects of embodiments of this disclosure include a display device that can relatively reduce the defect rate and a method of manufacturing the display device.

[0008] A display device according to some embodiments of the present disclosure may include: a light-emitting element; and an encapsulation layer on the light-emitting element. According to some embodiments, the encapsulation layer may include a first encapsulation layer, a second encapsulation layer on the first encapsulation layer, a third encapsulation layer on the second encapsulation layer, and a fourth encapsulation layer on the third encapsulation layer, and the third encapsulation layer may include gaps.

[0009] According to some embodiments, the second encapsulation layer may include organic materials, and the first, third, and fourth encapsulation layers may include inorganic materials.

[0010] According to some embodiments, the second encapsulation layer may include: a base portion; and a protrusion that protrudes from the base portion in the normal direction of the plane on which the display device is disposed.

[0011] According to some embodiments, the display device may further include an opening adjacent to a protrusion.

[0012] According to some embodiments, the second encapsulation layer may include an upper surface having uneven portions.

[0013] According to some embodiments, at least a portion of the third encapsulation layer can be within the opening, and the void is within the opening.

[0014] According to some embodiments, the third encapsulation layer can have a density that is higher than or equal to a density of the fourth encapsulation layer.

[0015] According to some embodiments, the fourth encapsulation layer can have a thickness that is greater than a thickness of the third encapsulation layer.

[0016] According to some embodiments, the third encapsulation layer can have a thickness of about to about .

[0017] According to some embodiments, the third encapsulation layer that overlaps the side surface of the protrusion can have a non-uniform thickness.

[0018] According to some embodiments, the first encapsulation layer can be in contact with the second encapsulation layer, the second encapsulation layer can be in contact with the third encapsulation layer, and the third encapsulation layer can be in contact with the fourth encapsulation layer.

[0019] According to some embodiments, the fourth encapsulation layer can not fill into the void.

[0020] A method of manufacturing a display device according to some embodiments of the disclosure can include forming a light emitting element layer; and forming an encapsulation layer on the light emitting element layer. According to some embodiments, forming the encapsulation layer can include forming a first encapsulation layer; forming a second encapsulation layer on the first encapsulation layer; forming a third encapsulation layer on the second encapsulation layer; and forming a fourth encapsulation layer on the third encapsulation layer, and forming the third encapsulation layer can include forming a void in the third encapsulation layer.

[0021] According to some embodiments, the second encapsulation layer can include an organic material, the first encapsulation layer, the third encapsulation layer, and the fourth encapsulation layer can include an inorganic material. According to some embodiments, the first encapsulation layer can be in contact with the second encapsulation layer, the second encapsulation layer can be in contact with the third encapsulation layer, and the third encapsulation layer can be in contact with the fourth encapsulation layer.

[0022] According to some embodiments, forming the second encapsulation layer can include forming a base encapsulation layer on the first encapsulation layer; disposing a mask on the base encapsulation layer; and exposing the base encapsulation layer to a plasma. According to some embodiments, at least a portion of an upper surface of the base encapsulation layer can be etched by the plasma.

[0023] According to some embodiments, the base encapsulation layer can be etched by the plasma to form the protrusion and the opening.

[0024] According to some embodiments, the base encapsulation layer can be etched by the plasma such that an upper surface of the second encapsulation layer has a non-flat portion.

[0025] According to some embodiments, the voids can be within the openings.

[0026] According to some embodiments, forming the third encapsulation layer can include depositing the third encapsulation layer on the second encapsulation layer, and the third encapsulation layer can be deposited at different rates in some regions compared to other regions.

[0027] According to some embodiments, the third encapsulation layer can have a thickness of about to about . BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, included to provide a further understanding of the embodiments according to the disclosure and are incorporated in and constitute a part of this specification, illustrate aspects of some embodiments of the disclosure and together with the description serve to explain aspects of some embodiments of the disclosure.

[0029] Figure 1 is a plan view schematically illustrating a display device according to some embodiments.

[0030] Figure 2 is a cross-sectional view schematically illustrating a display device according to some embodiments.

[0031] Figure 3 is a cross-sectional view schematically illustrating an encapsulation layer according to some embodiments.

[0032] Figure 4 is an enlarged schematic cross-sectional view of a region "S" of Figure 3 .

[0033] Figure 5 is a flowchart illustrating aspects of a method of manufacturing a display device according to some embodiments.

[0034] Figure 6 is a cross-sectional view schematically illustrating a method of manufacturing a display device according to further details of operations S100 and S200.

[0035] Figure 7 is a flowchart illustrating further details of operation S300 of Figure 5 .

[0036] Figures 8 to 13 is a cross-sectional view schematically illustrating aspects of a method of manufacturing a display device according to some embodiments. DETAILED DESCRIPTION

[0037] Since the present disclosure allows various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the scope of the embodiments according to the present disclosure to a particular mode of practice, and it is to be appreciated that all changes, equivalents, and substitutes not departing from the spirit and technical scope of the present disclosure are encompassed in the present disclosure.

[0038] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the scope of the present disclosure. Similarly, a second element could be termed a first element. In the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0039] It will be further understood that the terms "comprises", "comprising", "includes" and "including", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. In addition, when a first part "is on" a second part, the first part can not only be "directly on" the second part, but a third part can be interposed therebetween. Also, in the present disclosure, when a first part is formed on a second part, the direction on which the first part is formed is not limited to the upward direction of the second part, but can include the side or downward direction of the second part. Conversely, when a first part "is under" a second part, the first part can not only be "directly under" the second part, but a third part can be interposed therebetween.

[0040] The present disclosure relates to a display device and a method of manufacturing the same. Hereinafter, the display device and the method of manufacturing the same according to embodiments will be described with reference to the accompanying drawings.

[0041] Figure 1 is a plan view schematically illustrating a display device according to some embodiments.

[0042] Referring to Figure 1The display device DD can be configured to emit light. The display device DD can include a light emitting element. According to some embodiments, the display device DD can be a device that displays a moving image (e.g., a video image) or a still image (e.g., a static image). The display device DD can be used as a display screen for various electronic devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs). However, the application field of the display device DD is not limited to the specific examples listed above.

[0043] The display device DD can be formed in the form of a rectangular flat plate having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. A corner portion where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a curvature (e.g., a set or predetermined curvature), or can be formed at a right angle. The planar shape of the display device DD is not limited to a square shape or a rectangular shape, and can be formed into other polygonal shapes, irregular shapes, or arcuate shapes such as a circular shape or an elliptical shape. The display device DD can be formed to be flat, but embodiments according to the present disclosure are not limited thereto. For example, the display device DD can include curved portions formed at left and right ends and having a constant curvature or a varying curvature. In addition, the display device DD can be flexible such that it can be bent, folded, folded, or rolled. For example, according to some embodiments, the display device DD can be a flexible display device.

[0044] In the present disclosure, the first direction DR1 can be a row direction of the pixels PXL and can be a "horizontal" direction. The second direction DR2 can be a column direction of the pixels PXL. The third direction DR3 can be a display direction of the display device DD or a normal direction of a plane in which the base substrate layer BSL is disposed.

[0045] The display device DD can include a display area DA and a non-display area NDA. The non-display area NDA can refer to an area other than the display area DA. The non-display area NDA can surround at least a portion of the display area DA.

[0046] The display area DA can refer to an area in which the pixels PXL are disposed. The non-display area NDA can refer to an area in which the pixels PXL are not disposed. A driving circuit unit, a wiring, and a pad connected to the pixels PXL of the display area DA can be disposed in the non-display area NDA.

[0047] According to some embodiments, a pixel PXL (or a sub-pixel SPX) can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. At least one first sub-pixel SPX1, at least one second sub-pixel SPX2, and at least one third sub-pixel SPX3 can form one pixel unit capable of emitting light of various colors. Figure 1 An example in which each pixel PXL includes three sub-pixels SPX1, SPX2, and SPX3 (i.e., a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3) is illustrated, but embodiments of the present specification are not limited thereto.

[0048] According to some embodiments, a pixel PXL (or a sub-pixel SPX) can be arranged according to a stripe or However, the present disclosure is not necessarily limited thereto.

[0049] A first sub-pixel SPX1 can emit first light, a second sub-pixel SPX2 can emit second light, and a third sub-pixel SPX3 can emit third light. Here, the first light can be light in a red color band, the second light can be light in a green color band, and the third light can be light in a blue color band. The red color band can be a band of 600 nm to 750 nm (or approximately 600 nm to 750 nm), the green color band can be a band of 480 nm to 560 nm (or approximately 480 nm to 560 nm), and the blue color band can be a band of 370 nm to 460 nm (or approximately 370 nm to 460 nm), but embodiments of the present specification are not limited thereto.

[0050] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can include a light-emitting element that emits light, and can include an inorganic light-emitting element including an inorganic semiconductor or an organic light-emitting element. The present disclosure is not limited to a specific example. Hereinafter, for convenience of description, a description will be made based on an embodiment in which each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 includes an organic light-emitting element.

[0051] Figure 2 FIG. 1 is a schematic cross-sectional view illustrating a display device according to some embodiments.

[0052] The display device DD can include a base layer BSL, a pixel circuit layer PCL, and a display element layer DPL.

[0053] The base layer BSL can provide an area in which the pixel circuit layer PCL and the display element layer DPL are disposed. The base layer BSL can form (or constitute) a base member of the pixel PXL. The base layer BSL can be a rigid substrate or a film or a flexible substrate or a film, but embodiments according to the present disclosure are not limited to a specific example.

[0054] A pixel circuit layer PCL can be disposed on the base layer BSL. The pixel circuit layer PCL can include a buffer film BFL, a transistor TR, a gate insulating film GI, a first interlayer insulating film ILD1, a second interlayer insulating film ILD2, a connection pattern BCP, a power line PLL, a passivation film PSV, and a contact portion CNT.

[0055] The buffer film BFL can be disposed on the base layer BSL. The buffer film BFL can prevent or relatively reduce diffusion of impurities or contaminants from the outside. The buffer film BFL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and a metal oxide such as aluminum oxide (AlO x ).

[0056] The transistor TR can be a thin film transistor. According to some embodiments, the transistor TR can be a driving transistor. The transistor TR can be electrically connected to the light emitting element. The transistor TR can be electrically connected to the connection pattern BCP.

[0057] The transistor TR can include an active layer ACT, a first transistor electrode TE1, a second transistor electrode TE2, and a gate electrode GE.

[0058] The active layer ACT can refer to a semiconductor layer. The active layer ACT can be disposed on the buffer film BFL. The active layer ACT can include at least one of polysilicon (e.g., low temperature polysilicon (LTPS)), amorphous silicon, and oxide semiconductor.

[0059] The active layer ACT can include a first contact region in contact with the first transistor electrode TE1 and a second contact region in contact with the second transistor electrode TE2. The first and second contact regions can be semiconductor patterns doped with impurities. A region between the first and second contact regions can be a channel region. The channel region can be an intrinsic semiconductor pattern that is not doped with impurities.

[0060] The gate electrode GE can be disposed on the gate insulating film GI. A position of the gate electrode GE can correspond to a position of the channel region of the active layer ACT. For example, the gate electrode GE can be disposed on the channel region of the active layer ACT with the gate insulating film GI interposed therebetween.

[0061] The gate insulating film GI can be disposed on the active layer ACT. The gate insulating film GI can include an inorganic material. According to one example, the gate insulating film GI can include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y) and aluminum oxide (AlO x ).

[0062] The first interlayer insulating film ILD1 can be provided on the gate electrode GE. Like the gate insulating film GI, the first interlayer insulating film ILD1 can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ).

[0063] The first transistor electrode TE1 and the second transistor electrode TE2 can be provided on the first interlayer insulating film ILD1. The first transistor electrode TE1 can penetrate the gate insulating film GI and the first interlayer insulating film ILD1 to contact the first contact region of the active layer ACT, and the second transistor electrode TE2 can penetrate the gate insulating film GI and the first interlayer insulating film ILD1 to contact the second contact region of the active layer ACT. According to one example, the first transistor electrode TE1 can be a drain electrode, and the second transistor electrode TE2 can be a source electrode, but the present disclosure is not limited thereto.

[0064] The second interlayer insulating film ILD2 can be provided on the first transistor electrode TE1 and the second transistor electrode TE2. Like the first interlayer insulating film ILD1 and the gate insulating film GI, the second interlayer insulating film ILD2 can include an inorganic material. The inorganic material can include at least one of the materials that constitute the first interlayer insulating film ILD1 and / or the gate insulating film GI, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ).

[0065] The connection pattern BCP can be provided on the second interlayer insulating film ILD2. The connection pattern BCP can be connected to the first transistor electrode TE1 through a contact hole that penetrates the second interlayer insulating film ILD2. The connection pattern BCP can be electrically connected to the first electrode ELT1 through a contact portion CNT formed in the passivation film PSV.

[0066] The power supply line PLL can be provided on the second interlayer insulating film ILD2. The power supply line PLL can be electrically connected to the second electrode ELT2 through another contact portion formed in the passivation film PSV.

[0067] The passivation film PSV can be disposed on the second interlayer insulating film ILD2. The passivation film PSV can cover the connection pattern BCP and the power supply line PLL. The passivation film PSV can be provided in the form including an organic insulating film, an inorganic insulating film, or an organic insulating film disposed on an inorganic insulating film, but the present disclosure is not limited thereto. According to some embodiments, a contact portion CNT connected to a region of the connection pattern BCP and another contact portion connected to a region of the power supply line PLL can be formed in the passivation film PSV.

[0068] The display element layer DPL can be disposed on the pixel circuit layer PCL. The display element layer DPL can include the first electrode ELT1, the light emitting portion LD, the pixel definition layer PDL, the second electrode ELT2, and the encapsulation layer TFE. The light emitting element can include the first electrode ELT1, the light emitting portion LD, and the second electrode ELT2.

[0069] According to some embodiments, the light emitting portion LD can be disposed in a region defined by the pixel definition layer PDL. One side of the light emitting portion LD can be connected to the first electrode ELT1, and the other side of the light emitting portion LD can be connected to the second electrode ELT2.

[0070] Here, the first electrode ELT1 can be an anode electrode for the light emitting element, and the second electrode ELT2 can be a common electrode (or a cathode electrode) for the light emitting element. According to some embodiments, the first electrode ELT1 and the second electrode ELT2 can include a conductive material. For example, the first electrode ELT1 can include a conductive material having a reflective property, and the second electrode ELT2 can include a transparent conductive material, but embodiments according to the present disclosure are not necessarily limited thereto.

[0071] According to some embodiments, the light emitting portion LD can have a multi-layer thin film structure including a light generating layer. The light emitting portion LD can have a hole injection layer injecting holes, a hole transport layer having excellent hole transport properties and suppressing movement of electrons that are not recombined in the light generating layer to increase the chance of recombination of holes and electrons, a light generating layer emitting light by recombination of the injected electrons and holes, a hole blocking layer suppressing movement of holes that are not recombined in the light generating layer, an electron transport layer for smoothly transporting electrons to the light generating layer, and an electron injection layer injecting electrons. The light emitting element can emit light based on an electrical signal provided from the first electrode ELT1 and the second electrode ELT2.

[0072] The pixel definition layer PDL can define a position at which the light emitting portion LD implemented with an organic light emitting diode is disposed. The pixel definition layer PDL can include an organic material. According to one example, the pixel definition layer PDL can include at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin, but embodiments according to the present disclosure are not limited thereto.

[0073] An encapsulation layer TFE can be disposed on the second electrode ELT2. The encapsulation layer TFE can relatively reduce a step difference generated by the light emitting part LD and the pixel definition layer PDL. The encapsulation layer TFE can include a plurality of insulating films covering the light emitting element.

[0074] The encapsulation layer TFE according to some embodiments of the disclosure can increase the reliability of the display device DD (e.g., can relatively reduce the defect rate of the display device DD). For example, the encapsulation layer TFE can relatively reduce the risk of cracks growing within the encapsulation layer TFE, and mitigate stress applied to the encapsulation layer TFE when the display device DD is bent.

[0075] Details regarding the encapsulation layer TFE will be described later with reference to Figure 3 and Figure 4

[0076] Figure 3 is a schematic cross-sectional view of an encapsulation layer according to some embodiments. Figure 4 is a schematic cross-sectional view of an area S of Figure 3

[0077] With reference to Figure 3 and Figure 4 , the encapsulation layer TFE can include a multi-layer structure. For example, the encapsulation layer TFE can include a first encapsulation layer TFE1, a second encapsulation layer TFE2, a third encapsulation layer TFE3, and a fourth encapsulation layer TFE4. According to some embodiments, the encapsulation layer TFE can have a structure in which the first encapsulation layer TFE1, the second encapsulation layer TFE2, the third encapsulation layer TFE3, and the fourth encapsulation layer TFE4 are sequentially stacked on the second electrode ELT2.

[0078] The first encapsulation layer TFE1 can be disposed on the second electrode ELT2. The first encapsulation layer TFE1 can completely cover the second electrode ELT2.

[0079] The first encapsulation layer TFE1 can have a flat surface. For example, the upper surface of the first encapsulation layer TFE1 can be flat. Hereinafter, in the disclosure, the upward direction can be defined as the third direction DR3. The upper surface of the first encapsulation layer TFE1 can be a surface in contact with the second encapsulation layer TFE2.

[0080] The first encapsulation layer TFE1 can have a substantially uniform thickness. The first encapsulation layer TFE1 can have a thickness thinner than that of the second encapsulation layer TFE2. The first encapsulation layer TFE1 can have a thickness thinner than that of the fourth encapsulation layer TFE4.

[0081] The first encapsulation layer TFE1 can include an inorganic material. For example, the first encapsulation layer TFE1 can include silicon nitride (SiN x ​​), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ).

[0082] The second encapsulation layer TFE2 can be disposed on the first encapsulation layer TFE1. The second encapsulation layer TFE2 can entirely cover the first encapsulation layer TFE1. The second encapsulation layer TFE2 can be in contact with the first encapsulation layer TFE1.

[0083] The second encapsulation layer TFE2 can have a flat surface. For example, a lower surface of the second encapsulation layer TFE2 can be flat. Hereinafter, in the disclosure, a downward direction can be defined as a direction opposite to the third direction DR3. The lower surface of the second encapsulation layer TFE2 can face the upper surface of the first encapsulation layer TFE1. The lower surface of the second encapsulation layer TFE2 can be a surface in contact with the first encapsulation layer TFE1.

[0084] The second encapsulation layer TFE2 can have a substantially uneven surface. The upper surface of the second encapsulation layer TFE2 can not be substantially flat. The upper surface of the second encapsulation layer TFE2 can have uneven portions. For example, at least a portion of the upper surface of the second encapsulation layer TFE2 can protrude.

[0085] The second encapsulation layer TFE2 can include a base portion BSU and a protrusion PRU. A portion protruding from the upper surface of the second encapsulation layer TFE2 can be defined as the protrusion PRU. The second encapsulation layer TFE2 excluding the protrusion PRU can be defined as the base portion BSU. The protrusion PRU can protrude in one direction (for example, the third direction DR3). For example, the protrusion PRU can protrude from the base portion BSU in a normal direction of a plane in which the display device DD is disposed.

[0086] The protrusion PRU can define an opening H. The opening H can be disposed adjacent to (for example, on a side of) the protrusion PRU. The opening H can be disposed between the protrusions PRU. A plurality of openings H can be provided. The plurality of openings H can be spaced apart from each other at substantially uniform intervals. However, the disclosure is not limited thereto.

[0087] According to some embodiments, the protrusion PRU can have a quadrangular cross-section when viewed in a cross-section. According to some embodiments, the protrusion PRU can have a mesh pattern shape when viewed on a plane. However, the disclosure is not limited thereto, and the protrusion PRU can have various shapes of cross-sections.

[0088] Each of the base portion BSU and the protrusion PRU can have a substantially uniform thickness. The second encapsulation layer TFE2 can have a thickness greater than a thickness of the third encapsulation layer TFE3. In the present specification, the thickness of the second encapsulation layer TFE2 can be defined as an average thickness of the second encapsulation layer TFE2. The thickness of the second encapsulation layer TFE2 can include a thickness of the base portion BSU and a thickness of the protrusion PRU.

[0089] The second encapsulation layer TFE2 can include an organic material. For example, the second encapsulation layer TFE2 can include at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0090] The third encapsulation layer TFE3 can be disposed (e.g., directly disposed) on the second encapsulation layer TFE2. At least a portion of the third encapsulation layer TFE3 can be disposed in the opening H. The third encapsulation layer TFE3 can completely cover the second encapsulation layer TFE2. The third encapsulation layer TFE3 can be in contact with the second encapsulation layer TFE2. For example, the third encapsulation layer TFE3 can be directly adjacent to the protrusion PRU. At least a portion of the third encapsulation layer TFE3 can overlap a portion (e.g., the protrusion PRU) of the second encapsulation layer TFE2 in a planar direction along which the base layer BSL is disposed (e.g., a planar direction defined by the first direction DR1 and the second direction DR2).

[0091] The third encapsulation layer TFE3 can have a flat surface. For example, an upper surface of the third encapsulation layer TFE3 can be flat. The upper surface of the third encapsulation layer TFE3 can be a surface in contact with the fourth encapsulation layer TFE4. The third encapsulation layer TFE3 can have a non-flat surface. For example, a lower surface of the third encapsulation layer TFE3 can not be flat. The lower surface of the third encapsulation layer TFE3 can have a non-flat portion. The lower surface of the third encapsulation layer TFE3 can be a surface in contact with the second encapsulation layer TFE2.

[0092] The third encapsulation layer TFE3 can include a void VD. The void VD can be a hole formed during a process of depositing the third encapsulation layer TFE3. The void VD can be disposed within the opening H defined by the second encapsulation layer TFE2. This will be described later with reference to FIGS. 6A and 6B. Figure 12 This will be described later.

[0093] The third encapsulation layer TFE3 disposed on the side surface PSS of the protruding PRU can have a substantially non-uniform thickness. At least a portion of the third encapsulation layer TFE3 can have a non-uniform thickness. For example, the third encapsulation layer TFE3 disposed on the side surface PSS of the protruding PRU can have a thickness that increases from the center toward the outside. For example, when a thickness defined in a direction (e.g., the first direction DR1 or the second direction DR2) perpendicular to the side surface PSS of the protruding PRU is considered, the third encapsulation layer TFE3 can have a greater thickness at an edge of the side surface PSS of the protruding PRU than at the center. For example, when viewed from a direction along which a plane in which the base layer BSL is disposed extends (the first direction DR1 or the second direction DR2), the third encapsulation layer TFE3 overlapping the side surface PSS of the protruding PRU can have a non-uniform thickness.

[0094] Since the third encapsulation layer TFE3 includes the void VD and the third encapsulation layer TFE3 is disposed under the fourth encapsulation layer TFE4, the encapsulation layer TFE can mitigate stress applied to the fourth encapsulation layer TFE4 when the display device DD is bent. The encapsulation layer TFE can mitigate stress applied to the display device DD, thereby relatively reducing the risk of cracks being formed in the encapsulation layer TFE. Accordingly, the encapsulation layer TFE can relatively improve the reliability of the display device DD by relatively reducing the defect rate of the display device DD.

[0095] The third encapsulation layer TFE3 can have a thickness that is thinner than a thickness of the fourth encapsulation layer TFE4. The thickness of the third encapsulation layer TFE3 can be defined as an average thickness of the third encapsulation layer TFE3. The thickness of the third encapsulation layer TFE3 can include a thickness of the third encapsulation layer TFE3 that does not overlap the opening H and a thickness of the third encapsulation layer TFE3 formed within the opening H. The third encapsulation layer TFE3 can have a thickness of about to about Since the third encapsulation layer TFE3 has a thickness that is thinner than a thickness of the fourth encapsulation layer TFE4, the thickness of the display device DD can not be excessively increased, and the light output efficiency of the light emitting element can not be reduced.

[0096] The third encapsulation layer TFE3 can include an inorganic material. For example, the third encapsulation layer TFE3 can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ).

[0097] The fourth encapsulation layer TFE4 can be disposed on the third encapsulation layer TFE3. The fourth encapsulation layer TFE4 can completely cover the third encapsulation layer TFE3.

[0098] The fourth encapsulation layer TFE4 can have a flat surface. For example, the upper and lower surfaces of the fourth encapsulation layer TFE4 can be flat. The lower surface of the fourth encapsulation layer TFE4 can face the upper surface of the third encapsulation layer TFE3. The lower surface of the fourth encapsulation layer TFE4 can be the surface that contacts the third encapsulation layer TFE3.

[0099] The fourth encapsulation layer TFE4 can have a substantially uniform thickness. The fourth encapsulation layer TFE4 can have a greater thickness than the third encapsulation layer TFE3. The fourth encapsulation layer TFE4 can have a thinner thickness than the second encapsulation layer TFE2.

[0100] The fourth encapsulation layer TFE4 may include inorganic materials. For example, the fourth encapsulation layer TFE4 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following.

[0101] The fourth encapsulation layer TFE4 may have a density lower than or equal to that of the third encapsulation layer TFE3. For example, when observed by transmission electron microscopy (TEM), the film (or layer) density of the third encapsulation layer TFE3 may be higher than or equal to that of the fourth encapsulation layer TFE4. According to some embodiments of this disclosure, since the third encapsulation layer TFE3 has a film density higher than or equal to that of the fourth encapsulation layer TFE4, the adhesion between the third encapsulation layer TFE3 and the fourth encapsulation layer TFE4 can be enhanced.

[0102] In the following text, reference will be made to Figures 5 to 13 Describe the method for manufacturing the display device DD. Content that is already mentioned may be omitted.

[0103] Figure 5 This is a flowchart illustrating a method for manufacturing a display device according to some embodiments. Although Figure 5 The illustrations depict various operations in a method of manufacturing a display device, but the embodiments of this disclosure are not limited thereto, and according to some embodiments, the method may include additional or fewer operations, or the order of operations may be changed without departing from the spirit and scope of the embodiments of this disclosure unless otherwise stated or implied.

[0104] Figure 6 This is a cross-sectional view schematically illustrating a method for manufacturing a display device, based on further details of operations S100 and S200. Figure 7 It is a diagram. Figure 5a flowchart of further details of the operation S300. Although Figure 7 Various operations in the method of manufacturing the display device are illustrated, but embodiments according to the present disclosure are not limited thereto, and according to some embodiments, the method can include additional operations or fewer operations, or the order of the operations can be changed unless otherwise stated or implied, without departing from the spirit and scope of embodiments according to the present disclosure.

[0105] Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 are cross-sectional views schematically illustrating a method of manufacturing a display device according to some embodiments. For the sake of clarity, not all of the components of the display device are shown in the drawings. Figure 12 is an enlarged cross-sectional view of a region of Figure 11 and schematically shows an operation for depositing a third encapsulation layer TFE3.

[0106] Referring to Figure 5 , the method of manufacturing the display device DD can include forming a pixel circuit layer (operation S100), forming a light emitting element layer (operation S200), and forming an encapsulation layer (operation S300).

[0107] Referring to Figure 6 , in forming the pixel circuit layer (operation S100), a pixel circuit layer PCL including a pixel circuit for driving a light emitting element can be formed on the base layer BSL. The pixel circuit layer PCL can be formed to include a conductive layer and an insulating layer disposed between the conductive layer.

[0108] According to some embodiments, unless otherwise indicated, components disposed on the base layer BSL can be formed by a conventional patterning process (e.g., a photolithography process, etc.) using a mask.

[0109] In the present disclosure, unless otherwise indicated, as a process for depositing components of the display device DD, one or more of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process can be used. In the present disclosure, unless otherwise indicated, as an etching process, one or more of a wet etching process and a dry etching process can be used. However, the present disclosure is not limited to the specific examples.

[0110] Forming the light emitting element layer (operation S200) can refer to forming layers in the display element layer DPL described above, except for the encapsulation layer TFE.

[0111] ​​​​​Forming the light emitting element layer (operation S200) can include forming a first electrode ELT1. The first electrode ELT1 can be formed on the pixel circuit layer PCL. According to some embodiments, the first electrode ELT1 can be deposited on the pixel circuit layer PCL and then etched to expose at least a portion of the pixel circuit layer PCL.

[0112] Forming the light emitting element layer (operation S200) can further include forming a pixel defining layer PDL. The pixel defining layer PDL can be formed on the pixel circuit layer PCL. The pixel defining layer PDL can be deposited on the pixel circuit layer PCL and the first electrode ELT1, and the pixel defining layer PDL can be etched to expose at least a portion of the first electrode ELT1. The pixel defining layer PDL can be etched to overlap with a remaining portion of the first electrode ELT1 when viewed on a plane.

[0113] Forming the light emitting element layer (operation S200) can further include forming a light emitting portion LD. The light emitting portion LD can be disposed (or deposited) between the pixel defining layers PDL. The light emitting portion LD can be disposed (or deposited) within an area defined by the pixel defining layers PDL.

[0114] Forming the light emitting element layer (operation S200) can further include forming a second electrode ELT2. The second electrode ELT2 can be deposited on the light emitting portion LD and the pixel defining layers PDL.

[0115] Referring to Figure 7 Forming the encapsulation layer (operation S300) can include depositing a first encapsulation layer (operation S310), depositing a second encapsulation layer (operation S330), etching the second encapsulation layer (operation S350), depositing a third encapsulation layer (operation S370), and depositing a fourth encapsulation layer (operation S390).

[0116] Referring to Figure 8 Depositing the first encapsulation layer (operation S310) can correspond to forming a first encapsulation layer TFE1. In depositing the first encapsulation layer (operation S310), the first encapsulation layer TFE1 can be formed on the light emitting element layer LDL. The first encapsulation layer TFE1 can be deposited on the light emitting element layer LDL. The first encapsulation layer TFE1 can cover the light emitting element layer LDL. The first encapsulation layer TFE1 can be deposited on the second electrode ELT2.

[0117] Forming the second encapsulation layer TFE2 can include depositing a second encapsulation layer (operation S330) and etching the second encapsulation layer (operation S350).

[0118] Referring to Figure 9In depositing the second encapsulation layer (operation S330), a base encapsulation layer B_TFE2 can be deposited on the first encapsulation layer TFE1. The base encapsulation layer B_TFE2 can cover the first encapsulation layer TFE1. The base encapsulation layer B_TFE2 can be the second encapsulation layer TFE2 before forming the protrusion PRU, and can be the second encapsulation layer TFE2 before the plasma treatment.

[0119] The base encapsulation layer B_TFE2 can have a thickness greater than that of the first encapsulation layer TFE1.

[0120] The base encapsulation layer B_TFE2 can include at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0121] Referring to Figure 10 Etching the second encapsulation layer (operation S350) can include disposing a mask on the base encapsulation layer B_TFE2. The mask can be disposed on the base encapsulation layer B_TFE2. The mask can have a mask pattern corresponding to the protrusion PRU. For example, the mask pattern can overlap the opening H when viewed on a plane, and the mask can expose at least a portion of the base encapsulation layer B_TFE2.

[0122] Etching the second encapsulation layer (operation S350) can include exposing the base encapsulation layer B_TFE2 to a plasma. The base encapsulation layer B_TFE2 can be exposed to a plasma. At least a portion of the base encapsulation layer B_TFE2 exposed to the outside can be exposed to a plasma. At least a portion of a surface (e.g., an upper surface) of the base encapsulation layer B_TFE2 can be exposed to a plasma, and at least a portion of the surface of the base encapsulation layer B_TFE2 can be etched. For example, at least a portion of the base encapsulation layer B_TFE2 exposed to the outside through the mask pattern can be etched.

[0123] The base encapsulation layer B_TFE2 can be etched to form the second encapsulation layer TFE2. The base encapsulation layer B_TFE2 can be etched to form the protrusion PRU and the opening H.

[0124] Referring to Figure 11 and Figure 12 Forming the third encapsulation layer TFE3 can correspond to depositing the third encapsulation layer (operation S370). In depositing the third encapsulation layer (operation S370), the third encapsulation layer TFE3 can be formed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 can be deposited on the second encapsulation layer TFE2.

[0125] The third encapsulation layer TFE3 can completely cover the second encapsulation layer TFE2. At least a portion of the third encapsulation layer TFE3 can be formed within the opening H. At least a portion of the third encapsulation layer TFE3 can be deposited within the opening H.

[0126] Since the second encapsulation layer TFE2 includes the protrusion PRU, an upper surface of the second encapsulation layer TFE2 can have a step difference. Accordingly, when the third encapsulation layer TFE3 is deposited on the second encapsulation layer TFE2, the third encapsulation layer TFE3 can be deposited at a different deposition rate in some areas compared to in other areas. For example, the third encapsulation layer TFE3 can be deposited in a relatively small amount in some areas compared to in other areas. For example, an outer region of the side surface PSS of the protrusion PRU can be deposited at a first deposition rate L1, and a central region of the side surface PSS of the protrusion PRU can be deposited at a second deposition rate L2 different from the first deposition rate L1.

[0127] The first deposition rate L1 can be faster than the second deposition rate L2. Accordingly, the third encapsulation layer TFE3 disposed on the side surface PSS of the protrusion PRU can have a thickness that increases from the center toward the outside, and a hole (i.e., a void VD) can be formed during a process of depositing the third encapsulation layer TFE3.

[0128] The third encapsulation layer TFE3 according to some embodiments of the disclosure can not be etched alone in a process of forming the void VD. Accordingly, a void VD having a uniform shape can be formed in the third encapsulation layer TFE3, and stress applied to the encapsulation layer TFE can be reduced.

[0129] The void VD can be formed entirely in the entire display area DA and the non-display area NDA. Accordingly, the display device DD according to the disclosure, stress can be reduced in all areas of the display device DD, and the reliability of the display device DD can be relatively improved.

[0130] Referring to Figure 13 In depositing a fourth encapsulation layer (operation S390), a fourth encapsulation layer TFE4 can be formed on the third encapsulation layer TFE3. The fourth encapsulation layer TFE4 can be deposited on the third encapsulation layer TFE3. The fourth encapsulation layer TFE4 can entirely cover the third encapsulation layer TFE3.

[0131] The fourth encapsulation layer TFE4 can be deposited after the void VD is formed. Accordingly, the fourth encapsulation layer TFE4 can not be filled into the void VD.

[0132] According to some embodiments of the disclosure, a display device capable of relatively reducing a defect rate and a method of manufacturing the same can be provided.

[0133] As described above, aspects of some embodiments of the present disclosure have been disclosed by way of a detailed description and drawings. However, it will be appreciated that various modifications and changes can be made without departing from the spirit and technical scope of the present disclosure as set forth in the claims.

[0134] Therefore, the technical scope of the present disclosure is not limited to the detailed description described in the specification, but should be determined by the claims and their equivalents.

Claims

1. A display device comprising: a light-emitting element; and an encapsulating layer over the light-emitting element, wherein the encapsulating layer comprises a first encapsulating layer, a second encapsulating layer over the first encapsulating layer, a third encapsulating layer over the second encapsulating layer, and a fourth encapsulating layer over the third encapsulating layer, and wherein the third encapsulating layer comprises a void.

2. The display device according to claim 1, wherein the second encapsulating layer is formed of an organic material, and wherein the first encapsulating layer, the third encapsulating layer, and the fourth encapsulating layer are formed of an inorganic material.

3. The display device according to claim 1, wherein the second encapsulating layer comprises: a base portion; and a protrusion protruding from the base portion in a direction normal to a plane in which the display device is provided.

4. The display device according to claim 3, further comprising: an opening adjacent to the protrusion.

5. The display device according to claim 1, wherein the second encapsulating layer includes an upper surface having a portion that is uneven.

6. The display device according to claim 4, wherein at least a portion of the third encapsulating layer is within the opening, and wherein the void is within the opening.

7. The display device according to claim 1, wherein the third encapsulating layer has a density higher than or equal to that of the fourth encapsulating layer, wherein the fourth encapsulating layer has a thickness greater than that of the third encapsulating layer, and wherein the third encapsulation layer has a thickness in the range of to .

8. The display device according to claim 3, wherein the third encapsulating layer overlapping a side surface of the protrusion has a thickness that is not uniform.

9. The display device according to claim 1, wherein the first encapsulating layer contacts the second encapsulating layer, wherein the second encapsulating layer contacts the third encapsulating layer, and wherein the third encapsulating layer contacts the fourth encapsulating layer.

10. The display device according to any one of claims 1 to 9, wherein, the fourth encapsulating layer does not fill into the void.

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