Display panel and electronic device including the same

Abstract

The utility model relates to a display panel and an electronic device. A display panel according to one or more embodiments of the present disclosure includes: a display element layer including a pixel defining layer and a light emitting element, the pixel defining layer defining a pixel opening; and an encapsulation layer on the display element layer, and including: a first inorganic encapsulation layer on the display element layer, having a refractive index of about 1.90 or more and about 2.10 or less; a second inorganic encapsulation layer on the first inorganic encapsulation layer, the second inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; a third inorganic encapsulation layer on the second inorganic encapsulation layer, the third inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; and an organic encapsulation layer on the third inorganic encapsulation layer, the organic encapsulation layer having a dielectric constant of about 1.0 or more and about 2.5 or less.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0002037, filed on January 5, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display panels, electronic devices, and methods for manufacturing display panels, wherein the electronic devices have reduced thickness and, in the electronic devices, an input sensor located on the upper portion of the display panel has improved sensing performance. Background Technology

[0004] Various types of display devices are used to provide image information. Self-emissive display devices made of organic light-emitting materials or quantum dot light-emitting materials are under development. Because self-emissive display devices include light-emitting elements, and because these elements are susceptible to external environmental factors such as oxygen and moisture, various techniques for sealing the light-emitting elements are suitable. Among these techniques, a technique for arranging an encapsulation layer on the light-emitting element to block the penetration paths of air and moisture is being developed. The encapsulation layer may include an inorganic layer containing inorganic materials and an organic layer containing organic materials. Utility Model Content

[0005] This disclosure provides a display panel and an electronic device including the display panel, the display panel having reduced thickness and improved flexibility, and including an input sensor located on the upper portion of the display panel and having improved sensing performance.

[0006] This disclosure also provides a method for manufacturing a display panel, which manufactures a display panel with reduced thickness through a simplified process.

[0007] One or more embodiments of this disclosure provide a display panel including: a display element layer including a pixel defining layer and a light-emitting element, the pixel defining layer defining a pixel opening; and an encapsulation layer on the display element layer, including: a first inorganic encapsulation layer on the display element layer having a refractive index of about 1.90 or more and about 2.10 or less; a second inorganic encapsulation layer on the first inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; a third inorganic encapsulation layer on the second inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; and an organic encapsulation layer on the third inorganic encapsulation layer having a dielectric constant of about 1.0 or more and about 2.5 or less.

[0008] The organic encapsulation layer can be directly applied to the third inorganic encapsulation layer.

[0009] The second inorganic encapsulation layer can be directly on the first inorganic encapsulation layer, wherein the third inorganic encapsulation layer is directly on the second inorganic encapsulation layer.

[0010] The first, second, and third inorganic encapsulation layers can comprise the same material.

[0011] Each of the first, second, and third inorganic encapsulation layers can comprise one of silicon nitride, silicon oxide, and silicon oxynitride.

[0012] The second inorganic encapsulation layer can have a thickness that is greater than a thickness of the first inorganic encapsulation layer and greater than a thickness of the third inorganic encapsulation layer.

[0013] Each of the first and third inorganic encapsulation layers can have a thickness of about about 1 μm and about 3 μm, wherein the second inorganic encapsulation layer has a thickness of about about 1 μm and about 3 μm. The first, second, and third inorganic encapsulation layers can each have a thickness of about

[0014] The organic encapsulation layer can have a thickness of about 3 μm or more and about 8 μm or less.

[0015] A top surface of the second inorganic encapsulation layer can comprise a planarized surface.

[0016] The second inorganic encapsulation layer can have a water vapor transmission rate of about 1 x 10 -4 grams per square meter per day or more and about 9 x 10 -4 grams per square meter per day or less.

[0017] The encapsulation layer can cover the light emitting element.

[0018] The light emitting element can comprise a first electrode exposed through the pixel opening, a second electrode over the first electrode, and a light emitting layer between the first electrode and the second electrode.

[0019] The light emitting element can further comprise a hole control layer between the first electrode and the light emitting layer and an electron control layer between the light emitting layer and the second electrode.

[0020] A top surface of the organic encapsulation layer can define an uppermost surface of the encapsulation layer.

[0021] ​In one or more embodiments of the disclosure, an electronic device includes: an input sensor; a display panel below the input sensor and including: a display element layer including a pixel defining layer and a light emitting element, the pixel defining layer defining a pixel opening, the pixel opening defining a light emitting area; and an encapsulation layer on the display element layer and including: a first inorganic encapsulation layer on the display element layer having a refractive index of about 1.90 or more and about 2.10 or less; a second inorganic encapsulation layer on the first inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; a third inorganic encapsulation layer on the second inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; and an organic encapsulation layer on the third inorganic encapsulation layer having a dielectric constant of about 1.0 or more and about 2.5 or less.

[0022] The input sensor can be directly on the organic encapsulation layer.

[0023] The input sensor can include: a first sensor insulating layer directly on the organic encapsulation layer; a first sensor conductive layer on the first sensor insulating layer and including a first conductive pattern; a second sensor insulating layer on the first sensor insulating layer to cover the first sensor conductive layer; and a second sensor conductive layer on the second sensor insulating layer and including a second conductive pattern.

[0024] The electronic device further includes a housing accommodating the display panel and the input sensor.

[0025] In one or more embodiments of the disclosure, a method for manufacturing a display panel includes: forming a display element layer including a pixel defining layer and a light emitting element; and forming an encapsulation layer on the display element layer to cover the light emitting element by: forming a first inorganic encapsulation layer on the display element layer having a refractive index of about 1.90 or more and about 2.10 or less; forming a second inorganic encapsulation layer on the first inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; forming a third inorganic encapsulation layer on the second inorganic encapsulation layer having a refractive index of about 1.90 or more and about 2.10 or less; and forming an organic encapsulation layer on the third inorganic encapsulation layer having a dielectric constant of about 1.0 or more and about 2.5 or less.

[0026] The forming of the first inorganic encapsulation layer can be performed by a plasma enhanced atomic layer deposition (PEALD) or a physical vapor deposition (PVD) process, wherein the forming of the second inorganic encapsulation layer is performed by a plasma enhanced chemical vapor deposition (PECVD) process, and wherein the forming of the third inorganic encapsulation layer is performed by a PEALD or a PVD process.

[0027] The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be formed by the same silicon precursor. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain principles of the present disclosure. In the drawings:

[0029] FIG. 1A 、 FIG. 1B and FIG. 1C is a perspective view illustrating a display device according to one or more embodiments of the present disclosure;

[0030] FIG. 2 is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure;

[0031] FIG. 3 is a perspective view illustrating a display device according to one or more other embodiments of the present disclosure;

[0032] FIG. 4 is a cross-sectional view illustrating a display device according to one or more embodiments of the present disclosure;

[0033] FIG. 5 is a cross-sectional view illustrating a display module according to one or more embodiments of the present disclosure;

[0034] FIG. 6 is a plan view illustrating a display panel according to one or more embodiments of the present disclosure;

[0035] FIG. 7 is an enlarged cross-sectional view illustrating a display module according to one or more embodiments of the present disclosure;

[0036] FIG. 8 is an enlarged cross-sectional view illustrating a display module according to one or more embodiments of the present disclosure;

[0037] FIG. 9 is a cross-sectional view illustrating a partial configuration of a display module according to one or more embodiments of the present disclosure;

[0038] FIG. 10A is a flowchart illustrating a method for manufacturing a display panel according to one or more embodiments of the present disclosure;

[0039] FIG. 10B is a flowchart illustrating some processes of a method for manufacturing a display panel according to one or more embodiments of the present disclosure; and

[0040] FIG. 11A、 FIG. 11B 、 FIG. 11C 、 FIG. 11D and FIG. 11E are cross-sectional views respectively illustrating some processes of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] Aspects of some embodiments of the present disclosure and methods of realizing the same can be more readily understood by reference to the following detailed description of embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, that are unrelated to the embodiments described, or that are not necessary for understanding the aspects of the present disclosure can be omitted for the sake of brevity, clarity, and understanding. Unless otherwise noted, like reference numerals, characters or combinations thereof across the drawings and the written description indicate like elements, and thus repeated description can be omitted.

[0042] The described embodiments can have various modifications and can be implemented in different forms, and should not be interpreted as being limited to only the embodiments illustrated herein. The use of "can," "may," or "might" in describing the embodiments corresponds to one or more embodiments of the present disclosure.

[0043] In view of the overall disclosure, those of ordinary skill in the art will recognize that the present disclosure encompasses all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present disclosure, each feature of the embodiments of the present disclosure can be combined partially or wholly with each other, and various interlocks and operations are possible in the technical field, and each embodiment can be implemented independently of each other, or can be implemented in association together, unless otherwise stated or implied.

[0044] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, since the sizes and thicknesses of the elements in the drawings are arbitrarily illustrated for the convenience of description, the present disclosure is not limited thereto. In addition, the use of cross-hatching and / or shading in the drawings is for clarifying boundaries of adjacent elements. As such, the presence or absence of cross-hatching or shading is not a indication or a conveyance of any preference or requirement for particular materials, material properties, dimensions, ratios, commonality of illustrated elements between drawings, or any other characteristic, attribute, property, etc. of the elements, unless otherwise indicated.

[0045] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Further, embodiments disclosed herein are not limited to the specific structures described herein but include any structures that might be described by the words "structure" and / or "function" occurring in the written description and claims. For example, an implant region illustrated as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implant in the region between the buried region and the surface through which the implant was made.

[0046] For example, an implant region illustrated as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implant in the region between the buried region and the surface through which the implant was made.

[0047] For ease of explanation, spatially relative terms such as "beneath", "below", "lower", "bottom", "under", "above", "upper", "on", "over", "higher", "top", "side" (e.g., as in "sidewall") and the like can be used herein for describing the relationship between one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both orientations "above" and "below". The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first element is described as being "on" a second element, it indicates that the first element is disposed on the upper side or lower side of the second element, as terms are used in this context. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0048] Further, the phrase "in plan view" means when viewing the object portion from above, and the phrase "in schematic cross-sectional view" means when viewing a schematic cross-section taken through the object portion by a vertical cut from the side. The term "overlapping" means that a first object can be above or below or to the side of a second object, or vice versa. Additionally, the term "overlapping" can include stacking, facing, extending over, covering or partially covering, or any other suitable term that would be recognized and understood by one of ordinary skill in the art. The expression "not overlapping" can include such meanings as "spaced apart from" or "resting alongside" or "offset from" as well as any other suitable equivalents that would be recognized and understood by one of ordinary skill in the art. The term "facing" can mean that a first object can be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the third object can be understood to be indirectly opposite each other, but still facing each other.

[0049] It will be understood that when an element, layer, region or component is referred to as being "on" or "connected to" or "coupled to" or "operatively or communicatively coupled to" another element, layer, region or component, it can be directly on, connected to or coupled to the other element, layer, region or component, or intervening elements, layers, regions or components can be present. In addition, it can collectively mean directly or indirectly coupled or connected as well as integrally or non-integrally coupled or connected. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or coupled to the other layer, region and / or component, or one or more intervening layers, regions or components can be present. The one or more intervening components can include switches, resistors, capacitors, and / or the like. In describing embodiments, unless explicitly described as directly connected, expressions of connection denote electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected or coupled to another component or directly on another component without intervening components.

[0050] Also, in this specification, when a portion of a layer, film, region, plate, or the like is formed on another portion, the direction of formation is not limited to the upward direction, but includes the case where the portion is formed on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, or the like is formed "under" another portion, this includes not only the case where the portion is "directly under" the other portion, but also the case where there is a further portion between the portion and the other portion. Meanwhile, other expressions describing the relationship between components, such as "between", "directly between", or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0051] For purposes of the present disclosure, expressions such as "at least one of...", or "any of...", or "one or more of...", when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z", "at least one of X, Y, or Z", "at least one of a group of items consisting of X, Y, and Z", and "at least one of a group of items consisting of X, Y, or Z" can be interpreted as X alone, Y alone, Z alone, two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ, or any combination of any two or more of X, Y, and Z, and any variation of the foregoing. Similarly, the expressions "at least one of A and B" and "at least one of A or B" can include A, B, or both A and B. As used herein, "or" is generally employed in its sense including "and / or" and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or both A and B. Similarly, expressions such as "at least one of...", "one or more of...", "a or more of...", and other similar phrases when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Unless otherwise indicated, when the statement "C to D" is made, it means C or more and D or less.

[0052] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“first” element, component, region, layer or section described below could be termed a“second” element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. An element described as“first” need not necessarily be present before or before another element, or that it must be present before or before another element. The terms“first,”“second,” and the like can also be used herein to distinguish different classes or different groups of elements. For the sake of brevity, the terms“first,”“second,” and the like can be used herein to represent“first class (or first group),”“second class (or second group),” and so on.

[0053] In examples, the x-axis, y-axis and / or z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0054] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and / or“including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0055] When one or more embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in the opposite order to the described sequence.

[0056] As used herein, the terms "substantially," "about," "approximately," and the like, are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be apparent to one of ordinary skill in the art, which are understood to be within the scope of these terms. For example, "substantially" can include a range of + / - 5% of a recited value. As used herein, "about" or "approximately" includes the recited value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art considering the measurement in question and the error inherent in the measurement system (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within + / - 30%, 20%, 10%, 5% of the recited value. Further, the use of "may" when describing embodiments of the present disclosure relates to "one or more embodiments of the present disclosure."

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0058] FIG. 1A 、 FIG. 1B and FIG. 1C is a perspective view of a display device DD according to one or more embodiments of the present disclosure. FIG. 1A illustrates an unfolded state, and FIG. 1B and FIG. 1C illustrates a folded state.

[0059] Referring to FIG. 1A and FIG. 1B , a display device DD according to one or more embodiments of the present disclosure can include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR2. The display device DD can provide an image IM to a user through the display surface DS.

[0060] The display surface DS can include a display area DA and a non-display area NDA around the display area DA. The display area DA can display the image IM, and the non-display area NDA can not display the image IM. The non-display area NDA can surround the display area DA (e.g., in a plan view). However, the present disclosure is not limited thereto. For example, each of the display area DA and the non-display area NDA can be deformed in shape.

[0061] Hereinafter, a direction intersecting with a plane defined by the first direction DR1 and the second direction DR2 in a substantially perpendicular manner is defined as a third direction DR3. The third direction DR3 is a reference to distinguish a front surface and a rear surface of each member. In the present specification, the expression "viewed in a plane" can be defined as a state when viewed in the third direction DR3. Hereinafter, the first direction DR1, the second direction DR2, and the third direction DR3 are respectively indicated by first to third direction axes and referred to with the same reference numerals.

[0062] The display device DD can include a folding area FA and a plurality of non-folding areas NFA1 and NFA2. The non-folding areas NFA1 and NFA2 can include a first non-folding area NFA1 and a second non-folding area NFA2. In the second direction DR2, the folding area FA can be located between the first non-folding area NFA1 and the second non-folding area NFA2. Although the foldable display device DD is illustrated as an example, the present disclosure is not limited thereto. The display device DD can be a bar-type display device, a rollable display device, or a slide-type display device.

[0063] The display device DD can detect an input caused by a user's body FG. A finger is illustrated as an example of the user's body FG.

[0064] As shown in FIG. 1B , the folding area FA can be folded around a folding axis FX parallel to the first direction DR1. The folding area FA has a curvature (e.g., a predetermined curvature) and a curvature radius R1. The display device DD can be inwardly folded so that the display surface DS is not exposed to the outside, and the first non-folding area NFA1 and the second non-folding area NFA2 face each other.

[0065] In one or more embodiments of the present disclosure, the display device DD can be outwardly folded so that the display surface DS is exposed to the outside. In one or more embodiments of the present disclosure, the display device DD can perform an inward folding operation or an outward folding operation from a deployment operation in a repetitive manner. However, the present disclosure is not limited thereto. In one or more embodiments of the present disclosure, the display device DD can select one of a deployment operation, an inward folding operation, and an outward folding operation.

[0066] Although a distance between the first non-folding area NFA1 and the second non-folding area NFA2 can be substantially equal to twice the curvature radius R1 as shown in FIG. 1C , the distance between the first non-folding area NFA1 and the second non-folding area NFA2 can be less than twice the curvature radius R1 as shown in FIG. 1B FIG. 1C and FIG. 2 ​Based on the display surface DS illustration, and a housing HM providing an outer shape of the display device DD (see FIG. 2 ) can contact end regions of the first non-folded area NFA1 and the second non-folded area NFA2.

[0067] A display device DD suitable for a mobile terminal is illustrated as an example. A mobile phone can be formed as the electronic module, the camera module, and / or the power module mounted on a main board are located on a bracket or a housing together with the display device DD. However, the present disclosure is not limited thereto. For example, the display device DD according to one or more embodiments of the present disclosure can be applied to large electronic devices such as televisions and monitors, as well as small and medium electronic devices such as tablet computers, navigation units for vehicles, game consoles, and smart watches.

[0068] FIG. 2 An exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0069] As shown in FIG. 2 , the display device DD can include an electronic module EM, a power module PSM, and a housing HM. In one or more embodiments, the display device DD can further include a mechanical structure for controlling a folding operation of the display device DD. In one or more embodiments, an adhesive layer can couple the components to each other.

[0070] The display device DD generates an image, and detects an external input. The display device DD further includes a window WM and a display module DM. The window WM provides a front surface of the display device DD. The display device DD can further include additional components located between the window WM and the display module DM, or additional components located below the display module DM.

[0071] The display module DM can include at least a display panel DP. Although only the display panel DP in a stacked structure of the display module DM is illustrated in FIG. 1A , the display module DM can further substantially include a plurality of components located on the display panel DP. Detailed descriptions of the stacked structure of the display module DM will be described later.

[0072] However, the present disclosure is not limited to the display panel DP. For example, the display panel DP can be a light-emitting display panel such as an organic light-emitting display panel or an inorganic light-emitting display panel.

[0073] The display panel DP includes a display area DA (see FIG. 1A ) and a non-display area NDA (see FIG. 2The display area DP-DA and the non-display area DP-NDA are defined. Pixel PX is located in the display area DP-DA. The signal line that provides voltage to pixel PX is located in the non-display area DP-NDA, not in the display area DP-DA. In this specification, the statement "one area or portion corresponds to another area or portion" means that the area or portion overlaps with the other area or portion, and is not limited to having the same surface area.

[0074] like FIG. 2 As shown, the driver chip DIC can be located in the non-display area DP-NDA of the display panel DP. The flexible circuit board FCB can be connected to the non-display area DP-NDA of the display panel DP. The flexible circuit board FCB can be connected to the main circuit board. The main circuit board can be an electronic component of the electronic module EM. Additionally, the electronic module EM can further include a control module (e.g., an application processor), a wireless communication module, or an image input module. FIG. 2 Unlike other methods, a portion of the flexible circuit board (FCB) can be located below the display panel (DP). In a display device (DD) according to one or more embodiments, when the display module (DM) or a portion of the flexible circuit board (FCB) is bent, a portion of the flexible circuit board (FCB) can be located below the display panel (DP).

[0075] The driver chip (DIC) may include driving elements for driving pixels (PX), such as data driving circuitry. Although FIG. 2 The diagram illustrates a structure in which the driver chip DIC is mounted on the display panel DP, but this disclosure is not limited thereto. For example, the driver chip DIC can be mounted on a flexible circuit board FCB.

[0076] refer to FIG. 3 An electronic module EM may be located on each of the first housing HM1 and the second housing HM2, and a power supply module PSM may be located on each of the first housing HM1 and the second housing HM2. In one or more embodiments, the electronic module EM located on the first housing HM1 and the electronic module EM located on the second housing HM2 may be electrically connected via a flexible circuit board. The housing HM is coupled to the window WM to accommodate the other modules described above. Although the housing HM includes the first housing HM1 and the second housing HM2 which are separate from each other, this disclosure is not limited thereto. In one or more embodiments, the display device DD may further include a hinge structure for connecting the first housing HM1 and the second housing HM2.

[0077] FIG. 3 This is a perspective view illustrating a display device DD-1 according to one or more other embodiments of the present disclosure. FIG. 3As illustrated in FIG. 1A, the display device DD-1 can display an image by a display surface DS. The display surface DS can have a rectangular shape having a long side extending in a second direction DR2 and a short side extending in a first direction DR1 on a plane. However, the present disclosure is not limited thereto. For example, the display device DD-1 can have various shapes such as a circular shape or other polygonal shapes other than the rectangular shape.

[0078] Although the display device DD-1 having a flat display surface is illustrated in one or more embodiments of the present disclosure, the present disclosure is not limited thereto. The display device DD-1 can include a curved display surface or a three-dimensional display surface. The three-dimensional display surface can include a plurality of display regions indicating different directions from each other, and can also include, for example, a folded display surface. The display device DD-1 can be a flexible display device. The display device DD-1 can be a foldable display device capable of being folded.

[0079] The display device DD-1 suitable for a tablet computer is illustrated as an example. As an electronic module, a camera module, and a power supply module mounted on a main board are located on a stand or a housing together with the display device DD-1, a tablet computer can be formed. The display device DD-1 according to one or more embodiments of the present disclosure can be used for large electronic devices such as televisions and monitors, as well as small and medium electronic devices such as mobile phones, navigation units for vehicles, game consoles, and smart watches.

[0080] As FIG. 3 As illustrated in FIG. 1A, the display surface DS includes a display region DA on which an image is displayed and a non-display region NDA adjacent to the display region DA. The non-display region NDA is a region in which an image is not displayed. FIG. 3 An icon image is illustrated as an example of an image.

[0081] As FIG. 4 As illustrated in FIG. 1A, the display region DA can have a substantially rectangular shape. The term "substantially rectangular shape" includes not only a rectangular shape in terms of mathematics, but also a rectangular shape in which a curved boundary is defined at a vertex region (or a corner region) rather than a vertex.

[0082] The non-display region NDA can surround the display region DA. However, the present disclosure is not limited thereto. For example, the non-display region NDA can be deformed in shape. For example, the non-display region NDA can be located at one side of the display region DA.

[0083] FIG. 4 A cross-sectional view of a display device according to one or more embodiments of the present disclosure is illustrated. FIG. 2 A cross-sectional view taken along a line I-I' of FIG. 1A. FIG. 4 A cross-sectional view taken along a line I-I' of FIG. 1A.

[0084] ReferenceFIG. 2 The display device DD can include a window WM, a display module DM, a panel protection layer PPL, a cushion layer CSL, a first lower layer CTL1, a second lower layer CTL2, and first to fifth adhesive layers AL1 to AL5. Each of the first to fifth adhesive layers AL1 to AL5 couples two adjacent components among the components. Each of the first to fifth adhesive layers AL1 to AL5 can include a pressure sensitive adhesive (PSA) or an optically clear adhesive (OCA). However, the present disclosure is not limited to the kind of the adhesive layers.

[0085] The window WM provides an outer surface of the display device DD. The window WM can include a base layer WIN, a window protection layer WP, a hard coat layer HC, and a printing layer PIT (or a black matrix layer). The base layer WIN can have an optically transparent property. The window WM can include glass or a synthetic resin film. The window protection layer WP is attached to the base layer WIN by an adhesive layer AL. The window protection layer WP can include a flexible plastic material such as polyimide or polyethylene terephthalate. The hard coat layer HC can be located on a top surface of the window protection layer WP (as used herein, "on" can mean "above" or "below").

[0086] The printing layer PIT can be located on / below a bottom surface of the window protection layer WP. The printing layer PIT can be a black matrix layer. Although the printing layer PIT can have a black color, the present disclosure is not limited to the color of the printing layer PIT. The printing layer PIT can be located at an edge of the window protection layer WP. The printing layer PIT can overlap the non-display area NDA. However, the present disclosure is not limited to the above-described layer stack structure of the window WM.

[0087] The panel protection layer PPL can be located below the display module DM. The panel protection layer PPL can protect a lower portion of the display module DM. The panel protection layer PPL can include a flexible plastic material. For example, the panel protection layer PPL can include polyethylene terephthalate (PET). In one or more embodiments of the present disclosure, the panel protection layer PPL can be omitted.

[0088] The cushion layer CSL is located below the panel protection layer PPL. The cushion layer CSL absorbs external impact. The cushion layer CSL can include foamed plastic. In one or more embodiments of the present disclosure, the cushion layer CSL can be omitted.

[0089] The first lower layer CTL1 can be located below the cushion layer CSL. The first lower layer CTL1 can be located below the cushion layer CSL to protect components located thereabove from external impact. The first lower layer CTL1 can include a material having rigidity (e.g., a predetermined rigidity). The first lower layer CTL1 can include, for example, a metal plate. Alternatively, the first lower layer CTL1 can include a material having high magnetic permeability. The first lower layer CTL1 can include a ferromagnetic material. For example, the first lower layer CTL1 can include a magnetic metal powder layer. The magnetic metal powder layer can include a base resin and a magnetic metal powder mixed in the base resin. In one or more embodiments of the disclosure, the first lower layer CTL1 can be omitted.

[0090] The second lower layer CTL2 can be located below the first lower layer CTL1. The second lower layer CTL2 can block or reduce electromagnetic waves generated by the electronic module EM so that the electromagnetic waves do not interfere with the display module DM. FIG. 2 The second lower layer CTL2 can include a diamagnetic material. In addition, the second lower layer CTL2 can dissipate heat generated from the display module DM, such as heat generated from the driving chip DIC (refer to FIG. 1). FIG. 5 The second lower layer CTL2 can include a diamagnetic material. In addition, the second lower layer CTL2 can dissipate heat generated from the display module DM, such as heat generated from the driving chip DIC (refer to FIG. 1).

[0091] The second lower layer CTL2 can include a metal layer, such as a layer including copper, aluminum, gold, or titanium. The second lower layer CTL2 can include a metal oxide layer, such as a layer including indium tin oxide (ITO) or indium zinc oxide (IZO). The second lower layer CTL2 can include carbon nanotubes (e.g., carbon nanotubes coated with a conductive polymer) or graphite.

[0092] FIG. 5 is a cross-sectional view of a display module DM according to one or more embodiments of the disclosure. Referring to FIG. 2 , the display module DM can include a display panel DP, an input sensor IS, and an anti-reflector RL.

[0093] The display panel DP can include a base layer BS, a circuit element layer DP-CL, a display element layer DP-ED, and a sealing layer TFE. The base layer BS can provide a base surface on which the circuit element layer DP-CL is located.

[0094] The base layer BS can be a rigid plate or a flexible plate that is bendable, foldable, or rollable.

[0095] The base layer BS can have a single-layer structure or a multi-layer structure. The base layer BS according to one or more embodiments can include a single resin layer or a plurality of resin layers. The base layer BS can include a plurality of resin layers and a single inorganic layer located between the plurality of resin layers or a plurality of inorganic layers respectively located between the plurality of resin layers.

[0096] The circuit element layer DP-CL can be located on the base layer BS. The circuit element layer DP-CL can include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The circuit element layer DP-CL includes a reference FIG. 2 The driving circuit of the pixel PX described above. The display element layer DP-ED can be located on the circuit element layer DP-CL. The display element layer DP-ED includes a reference FIG. 6 The light emitting element of the pixel PX described above.

[0097] The encapsulation layer TFE is located on the display element layer DP-ED. The encapsulation layer TFE can protect the display element layer DP-ED from moisture, oxygen, and foreign substances such as dust particles. The encapsulation layer TFE can include at least one inorganic layer and at least one organic layer. The encapsulation layer TFE includes a stacked structure of the inorganic layer and the organic layer. The configuration of the encapsulation layer TFE will be described in more detail later.

[0098] The input sensor IS can be located on the display panel DP. The input sensor IS can detect an input of a stylus pen and an input of a user's body FG. The input sensor IS can be continuously provided on the display panel DP. In this case, the input sensor IS can be directly located on the display panel DP. The input sensor IS can be directly located on the encapsulation layer TFE. In this specification, the expression "a component A is directly located on a component B" can mean that no adhesive layer is located between the component A and the component B.

[0099] The anti-reflection layer RL can be located on the input sensor IS. The anti-reflection layer RL can reduce reflection of external light. The anti-reflection layer RL can be directly located on the input sensor IS by a continuous process.

[0100] The anti-reflection layer RL can include a color filter. The color filter has a color corresponding to a color of a source light. For example, a red color filter is located on a light emitting element that emits red light. The anti-reflection layer RL can further include a light blocking pattern located between the color filters.

[0101] FIG. 6 To illustrate a plan view of the display panel DP according to one or more embodiments of the present disclosure.

[0102] Referring to FIG. 7 , the display panel DP can include a plurality of pixels PX, a scan driver SDV, an emission driver EDV, a plurality of signal lines, and a plurality of first pads PD1. A driver IC mounted to the non-display area DP-NDA can include a data driver. In one or more embodiments of the present disclosure, the data driver can also be integrated with the display panel DP as the scan driver SDV and the emission driver EDV.

[0103] The multiple signal lines may include multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple transmit lines EL1 to ELm, a first control line SL-C1 and a second control line SL-C2, and a first power line PL1 and a second power line PL2. Here, each of the reference symbols m and n is a natural number equal to or greater than 2.

[0104] Scan lines SL1 to SLm can each extend along the first direction DR1 and can be connected to the pixel PX and the scan driver SDV. Data lines DL1 to DLn can each extend along the second direction DR2 and can be connected to the pixel PX and the driver chip DIC. Transmit lines EL1 to ELm can each extend along the first direction DR1 and can be connected to the pixel PX and the transmit driver EDV.

[0105] A first power line PL1 receives a first power supply voltage, and a second power line PL2 receives a second power supply voltage, wherein the voltage level of the second power supply is less than / lower than the voltage level of the first power supply voltage. In one or more embodiments, the second electrode (e.g., a cathode) of the light-emitting element is connected to the second power line PL2.

[0106] The first control line SL-C1 can be connected to the scan driver SDV and can extend towards the bottom of the display panel DP. The second control line SL-C2 can be connected to the transmit driver EDV and can extend towards the bottom of the display panel DP. The first pad PD1 can be located adjacent to the bottom of the display panel DP on the non-display area DP-NDA and can be positioned closer to the bottom of the display panel DP than the driver chip DIC. The first pad PD1 can be connected to the driver chip DIC and some signal lines.

[0107] The scan driver SDV generates multiple scan signals, which are applied to pixel PX via scan lines SL1 to SLm. The driver chip DIC generates multiple data voltages, which are applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV generates multiple transmit signals, which are applied to pixel PX via transmit lines EL1 to ELm.

[0108] A pixel PX can receive a data voltage in response to a scan signal. A pixel PX can display an image by emitting light with a brightness corresponding to the data voltage in response to a transmit signal.

[0109] FIG. 7 This is a cross-sectional view illustrating a display module DM according to one or more embodiments of the present disclosure.

[0110] FIG. 7 The diagram shows a cross-section corresponding to a light-emitting region LA and the surrounding non-light-emitting region NLA.FIG. 7 A cross-section of a light emitting element LD included in a pixel PX and a transistor TFT connected thereto is illustrated. The transistor TFT can be one of a plurality of transistors included in a driving circuit of the pixel PX. Although the transistor TFT is described as a silicon transistor, in one or more other embodiments, the transistor TFT can be an oxide transistor.

[0111] In FIG. 1A , the base layer BS is illustrated as a single layer. The base layer BS can include a synthetic resin such as polyimide. In one or more embodiments, the base layer BS can be provided by applying a synthetic resin layer on a working substrate (or a carrier substrate), and the working substrate can be removed when the display module DM is completed in a subsequent process.

[0112] The base layer BS can have a single layer structure or a multi-layer structure. For example, the base layer BS can include a first synthetic resin layer, an intermediate layer having a single layer structure or a multi-layer structure, and a second synthetic resin layer, which are sequentially stacked. The intermediate layer can be referred to as a base separation layer. The intermediate layer can include a silicon oxide (SiO x ) layer and an amorphous silicon (a-Si) layer on the silicon oxide layer. However, the present disclosure is not limited thereto. For example, the intermediate layer can include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an amorphous silicon layer.

[0113] Each of the first synthetic resin layer and the second synthetic resin layer can include a polyimide-based resin. In addition, each of the first synthetic resin layer and the second synthetic resin layer can include at least one of an acrylate-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In the present specification, the term “α”-based resin indicates a characteristic of including an “α” functional group.

[0114] A buffer layer 10br can be located on the base layer BS. The buffer layer 10br can reduce or prevent diffusion of metal atoms or impurities from the base layer 110 to a semiconductor pattern located thereabove. The semiconductor pattern includes an active area AC1 of the transistor TFT.

[0115] A shielding pattern BMLa can be located below the transistor TFT. The shielding pattern BMLa can block external light from reaching the transistor TFT. The shielding pattern BMLa can be located between the base layer BS and the buffer layer 10br. In one or more embodiments of the present disclosure, an inorganic separation layer can be further located between the shielding pattern BMLa and the buffer layer 10br. The shielding pattern BMLa can be connected to an electrode or a line, and can receive a constant voltage or a signal from the electrode or the line.

[0116] A semiconductor pattern can be located on the buffer layer 10br. The semiconductor pattern can include a silicon semiconductor. For example, the silicon semiconductor can include amorphous silicon and / or polycrystalline silicon. For example, the semiconductor pattern can include low-temperature polycrystalline silicon.

[0117] The semiconductor pattern can include a first region having high conductivity and a second region having low conductivity. The first region can be doped with an n-type dopant or a p-type dopant. A p-type transistor can include a doped region doped with a p-type dopant, and an n-type transistor can include a doped region doped with an n-type dopant. The second region can be a non-doped region, or can be a doped region having a concentration smaller than that of the first region.

[0118] The first region can have greater conductivity than that of the second region, and can substantially function as an electrode or a signal line. The second region can substantially correspond to an active region (or a channel) of a transistor. In other words, one portion of the semiconductor pattern can be an active region of a transistor, another portion can be a source or a drain of a transistor, and another portion can be a connection electrode or a connection signal line.

[0119] A source region SA1 (or a source electrode), an active region AC1 (or a channel), and a drain region DA1 (or a drain electrode) of a transistor TFT can be provided by the semiconductor pattern. The source region SA1 and the drain region DA1 can extend in opposite directions from the active region AC1 in a cross-section.

[0120] A first insulating layer 10 can be located on the buffer layer 10br. The first insulating layer 10 can overlap the plurality of pixels PX (refer to FIG. 1) in common, and can cover the semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 10 can be a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the circuit element layer DP-CL, which will be described later, can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. Although the inorganic layer can include at least one of the above-described materials, the present disclosure is not limited thereto.

[0121] A gate GT1 of a transistor TFT is located on the first insulating layer 10. The gate GT1 can be a portion of a metal pattern. The gate GT1 overlaps the active region AC1. The gate GT1 can be used as a mask in a process of doping the semiconductor pattern. Although the gate GT1 can include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), and / or indium zinc oxide (IZO), the present disclosure is not limited thereto.

[0122] A second insulating layer 20 can be positioned on the first insulating layer 10 to cover the gate electrode GT1. A third insulating layer 30 can be positioned on the second insulating layer 20. A second electrode CE20 of the storage capacitor Cst can be positioned between the second insulating layer 20 and the third insulating layer 30. Further, a first electrode CE10 of the storage capacitor Cst can be positioned between the first insulating layer 10 and the second insulating layer 20.

[0123] A first connection electrode CN1 can be positioned on the third insulating layer 30. The first connection electrode CN1 can be connected to the drain region DA1 of the transistor TFT through a contact hole passing through the first to third insulating layers 10, 20, and 30.

[0124] A fourth insulating layer 40 can be positioned on the third insulating layer 30. A second connection electrode CN2 can be positioned on the fourth insulating layer 40. The second connection electrode CN2 can be connected to the first connection electrode CN1 through a contact hole passing through the fourth insulating layer 40. A fifth insulating layer 50 can be positioned on the fourth insulating layer 40 to cover the second connection electrode CN2. The stack structure of the first to fifth insulating layers 10 to 50 is merely an example, and in addition to the first to fifth insulating layers 10 to 50, additional conductive layers and insulating layers can be further positioned.

[0125] Each of the fourth and fifth insulating layers 40 and 50 can be an organic layer. For example, the organic layer can include a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and / or a mixture thereof.

[0126] The light emitting element LD can include a first electrode AE (or a pixel electrode), a light emitting layer EL, and a second electrode CE (or a common electrode). The first electrode AE can be positioned on the fifth insulating layer 50. The first electrode AE can be a (semi-)transmissive electrode or a reflective electrode.

[0127] A pixel definition layer PDL can be positioned on the fifth insulating layer 50. According to one or more embodiments, the pixel definition layer PDL can have light absorption characteristics and can have, for example, black color. The pixel definition layer PDL can include a black colorant. The black colorant can include a black pigment and a black dye. The black colorant can include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition layer PDL can correspond to a light shielding pattern having light shielding characteristics.

[0128] The pixel definition layer PDL can cover a portion of the first electrode AE (e.g., anode). For example, an opening PDL-OP for exposing a portion of the first electrode AE can be defined in the pixel definition layer PDL. The opening PDL-OP of the pixel definition layer PDL can define a light emitting area LA.

[0129] The pixel definition layer PDL can increase a distance between an edge of the first electrode AE and the second electrode CE (e.g., cathode). Accordingly, the pixel definition layer PDL can be used to reduce or prevent a possibility of generating an electric arc at the edge of the first electrode AE.

[0130] In one or more embodiments, a hole control layer can be located between the first electrode AE and the light emitting layer EL. The hole control layer can include a hole transport layer, and can further include a hole injection layer. An electron control layer can be located between the light emitting layer EL and the second electrode CE. The electron control layer can include an electron transport layer, and can further include an electron injection layer.

[0131] A sealing layer TFE can be located on the display element layer DP-ED. The sealing layer TFE can protect the display element layer DP-ED from moisture, oxygen, and / or foreign substances such as dust particles. The sealing layer TFE can include at least one inorganic layer and at least one organic layer. The sealing layer TFE includes a stacked structure of the inorganic layer and the organic layer. The configuration of the sealing layer TFE will be described in more detail later.

[0132] An input sensor IS can be located on the display panel DP. The input sensor IS can include a first sensor insulating layer IS-IL1, a first sensor conductive layer IS-CL1, a second sensor insulating layer IS-IL2, a second sensor conductive layer IS-CL2, and a third sensor insulating layer IS-IL3. The first sensor insulating layer IS-IL1 can be directly located on the sealing layer TFE.

[0133] In one or more embodiments of the disclosure, the first sensor insulating layer IS-IL1 and / or the third sensor insulating layer IS-IL3 can be omitted. When the first sensor insulating layer IS-IL1 is omitted, the first sensor conductive layer IS-CL1 can be directly located on the uppermost insulating layer of the sealing layer TFE. The third sensor insulating layer IS-IL3 can be replaced by an adhesive layer or an insulating layer of an anti-reflective layer RL located on the input sensor IS.

[0134] The first sensor conductive layer IS-CL1 can include a first conductive pattern, and the second sensor conductive layer IS-CL2 can include a second conductive pattern. Hereinafter, the first sensor conductive layer IS-CL1 and the first conductive pattern are indicated by the same reference numerals, and the second sensor conductive layer IS-CL2 and the second conductive pattern are indicated by the same reference numerals. The first conductive pattern IS-CL1 is located on the first sensor insulating layer IS-IL1. The second conductive pattern IS-CL2 is located on the second sensor insulating layer IS-IL2.

[0135] Each of the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 can have a single layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3. The conductive layer having the multi-layer structure can include at least two of a transparent conductive layer and a metal layer. The conductive pattern having the multi-layer structure can include metal layers including different metals from each other. The transparent conductive layer can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, and / or graphene. The metal layer can include molybdenum, silver, titanium, copper, aluminum, and / or an alloy thereof.

[0136] Each of the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 can have a thickness of about 0.1 µm or more and about 1 µm or less. When each of the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 has a thickness less than about 0.1 µm, input detection performance of the input sensor IS can be reduced due to an increase in line resistance. When each of the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 has a thickness greater than about 1 µm, the total thickness of the display device DD (refer to FIG. 1) can increase and the folding characteristics can be deteriorated due to excessive increase in the thickness of the input sensor IS. FIG. 8 ) of the display device DD (refer to FIG. 1) can increase and the folding characteristics can be deteriorated due to excessive increase in the thickness of the input sensor IS.

[0137] Each of the first sensor insulating layer IS-IL1 to the third sensor insulating layer IS-IL3 can include an inorganic layer or an organic layer. Each of the first sensor insulating layer IS-IL1 to the third sensor insulating layer IS-IL3 can include an inorganic layer. The inorganic layer can include silicon oxide, silicon nitride, or silicon oxynitride.

[0138] In one or more embodiments of the disclosure, at least one of the first sensor insulating layer IS-IL1, the second sensor insulating layer IS-IL2, and the third sensor insulating layer IS-IL3 can be an organic layer. For example, the third sensor insulating layer IS-IL3 can include an organic layer. The organic layer can include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0139] The anti-reflection layer RL can be located on the input sensor IS. The anti-reflection layer RL can include the light-blocking pattern BM, the color filter CF, and the planarization layer OC. In one or more embodiments of the disclosure, the light-blocking pattern BM can be omitted.

[0140] The light-blocking pattern BM can be made of various light-absorbing materials. However, the disclosure is not limited thereto. The light-blocking pattern BM can be a layer having black color. In one or more embodiments, the light-blocking pattern BM can include a black colorant. The black colorant can include a black pigment and a black dye. The black colorant can include carbon black, a metal such as chromium, or an oxide thereof.

[0141] The light-blocking pattern BM can overlap the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 on / in a plan view. The light-blocking pattern BM can reduce or prevent external light reflection caused by the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2. An opening BM-OP can be defined in the light-blocking pattern BM. The opening BM-OP of the light-blocking pattern BM can overlap the first electrode AE and can have an area greater than that of the opening PDL-OP of the pixel-defining layer PDL. The opening BM-OP of the light-blocking pattern BM can define a pixel area PXA. The pixel area PXA can be defined as an area through which light generated by the light-emitting element LD is emitted to the outside. As the area of the pixel area PXA increases, the brightness of an image can increase.

[0142] The color filter CF can overlap at least the pixel area PXA. The color filter CF can further overlap the non-pixel area NPXA. The color filter CF can have a portion located on the light-blocking pattern BM. The color filter CF can transmit light generated by the light-emitting element LD and can reduce or block external light of a corresponding wavelength. Accordingly, the color filter CF can reduce external light reflection caused by the first electrode AE or the second electrode CE.

[0143] The planarization layer OC can cover the light-blocking pattern BM and the color filter CF. The planarization layer MC can include an organic material and provide a flat top surface.

[0144] FIG. 8To illustrate a magnified cross-sectional view of the display module DM according to one or more embodiments of the present disclosure. FIG. 8 FIG. 13 illustrates a cross-section corresponding to the light emitting regions LA-1, LA-2, and LA-3 adjacent to each other and the surrounding non-light emitting region NLA. Here, the anti-reflector RL described in FIG. 12 is omitted. FIG. 7 FIG. 8 FIG. 14 illustrates a cross-section corresponding to the light emitting regions LA-1, LA-2, and LA-3 adjacent to each other and the surrounding non-light emitting region NLA. Here, the anti-reflector RL described in FIG. 13 is omitted.

[0145] Referring to FIG. 1, FIG. 7 The base layer BS can have a single layer structure or a multi-layer structure. For example, the base layer BS can include a first synthetic resin layer, an intermediate layer having a single layer structure or a multi-layer structure, and a second synthetic resin layer, which are sequentially stacked. The intermediate layer can be referred to as a base separation layer. The intermediate layer can include a silicon oxide (SiO x ) layer and an amorphous silicon (a-Si) layer on the silicon oxide layer. However, the present disclosure is not limited thereto. For example, the intermediate layer can include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an amorphous silicon layer.

[0146] Each of the first synthetic resin layer and the second synthetic resin layer can include a polyimide-based resin. In addition, each of the first synthetic resin layer and the second synthetic resin layer can include at least one of an acrylate-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In the present specification, the term "α"-based resin indicates a characteristic of including an "α" functional group.

[0147] The circuit element layer DP-CL can be located on the base layer BS and can include a plurality of transistors, each of which can include a control electrode, an input electrode, and an output electrode in one or more embodiments. For example, the circuit element layer DP-CL can include a switching transistor and a driving transistor for driving the light emitting elements LD1, LD2, and LD3 of the display element layer DP-ED.

[0148] The display element layer DP-ED can include a pixel definition layer PDL and first to third light emitting elements LD1, LD2, and LD3. A pixel opening PDL-OP (refer to FIG. 2) can be defined in the pixel definition layer PDL. For example, the pixel definition layer PDL can contain an organic light shielding material or an inorganic light shielding material containing a black pigment or a black dye. FIG. 8

[0149] ​​The display panel DP can be divided into a non-light emitting area NLA and light emitting areas LA-1, LA-2, and LA-3. Each of the light emitting areas LA-1, LA-2, and LA-3 can be an area through which light generated by a corresponding one of the first to third light emitting elements LD1, LD2, and LD3 is emitted. The light emitting areas LA-1, LA-2, and LA-3 can be spaced apart from each other in a planar view.

[0150] Each of the light emitting areas LA-1, LA-2, and LA-3 can be defined by a pixel definition layer PDL. The non-light emitting area NLA can be located between adjacent light emitting areas LA-1, LA-2, and LA-3, and can correspond to the pixel definition layer PDL. In the present specification, each of the light emitting areas LA-1, LA-2, and LA-3 can correspond to a pixel. The pixel definition layer PDL can distinguish the first to third light emitting elements LD1, LD2, and LD3. The light emitting layers EL1, EL2, and EL3 of the first to third light emitting elements LD1, LD2, and LD3 can be located in a pixel opening PDL-OP defined in the pixel definition layer PDL.

[0151] The light emitting areas LA-1, LA-2, and LA-3 can be divided into a plurality of groups according to colors of light respectively generated from the first to third light emitting elements LD1, LD2, and LD3. In the display panel DP according to one or more embodiments in FIG. 8 In the display panel DP according to one or more embodiments, three light emitting areas LA-1, LA-2, and LA-3 respectively emitting red light, green light, and blue light are illustrated as an example. For example, the display module DM according to one or more embodiments can include a red light emitting area LA-1, a green light emitting area LA-2, and a blue light emitting area LA-3 distinguished from each other.

[0152] The first to third light emitting elements LD1, LD2, and LD3 can be spaced apart from each other in a direction (e.g., a first direction DR1) perpendicular to the thickness direction DR3. The first to third light emitting elements LD1, LD2, and LD3 can emit light of different wavelengths. For example, the first light emitting element LD1 can emit red light, the second light emitting element LD2 can emit green light, and the third light emitting element LD3 can emit blue light. That is, the red light emitting area LA-1, the green light emitting area LA-2, and the blue light emitting area LA-3 can correspond to the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, respectively.

[0153] However, the present disclosure is not limited thereto. For example, the first to third light emitting elements LD1, LD2, and LD3 can emit light in the same wavelength region or at least one light in different wavelength regions. For example, the first to third light emitting elements LD1, LD2, and LD3 can all emit blue light.

[0154] Each of the light emitting elements LD1, LD2, and LD3 can include a first electrode AE, a second electrode CE on the first electrode AE, and a light emitting layer EL1, EL2, or EL3 between the first electrode AE and the second electrode CE. The first electrode AE can be exposed from the pixel opening PDL-OP of the pixel definition layer PDL.

[0155] Further, each of the light emitting elements LD1, LD2, and LD3 can further include a hole control layer HTR and an electron control layer ETR. The hole control layer HTR can be located between the first electrode AE and the light emitting layer EL1, EL2, and EL3. The electron control layer ETR can be located between the light emitting layer EL1, EL2, and EL3 and the second electrode CE.

[0156] FIG. 9 The light emitting layers EL1, EL2, and EL3 of the light emitting elements LD1, LD2, and LD3 are illustrated as being located in the pixel openings PDL-OP defined in the pixel definition layer PDL and the hole control layer HTR, the electron control layer ETR, and the second electrode CE are provided as a common layer throughout all of the light emitting elements LD1, LD2, and LD3 in one or more embodiments. However, the present disclosure is not limited thereto. For example, unlike as shown in FIG. 1, the hole control layer HTR and the electron control layer ETR can be provided in the pixel openings PDL-OP defined in the pixel definition layer PDL by being patterned. For example, in one or more embodiments, the hole control layer HTR, the light emitting layer EL1, EL2, and EL3, and the electron control layer ETR of the light emitting elements LD1, LD2, and LD3 can be patterned by an inkjet printing method. FIG. 9

[0157] The first electrode AE can be an anode. However, the present disclosure is not limited thereto. Further, the first electrode AE can be a pixel electrode. The first electrode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The first electrode AE can include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, a compound of at least two thereof, a mixture selected from at least two thereof, and / or an oxide thereof.

[0158] ​When the first electrode AE is a transmissive electrode, the first electrode AE can include a metal oxide such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). When the first electrode AE is a semi-transmissive electrode or a reflective electrode, the first electrode AE can include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, or a compound or mixture thereof (for example, a mixture of Ag and Mg). Alternatively, the first electrode AE can have a multi-layer structure including a reflective layer or a semi-transflective layer made of the above-described materials and a transparent conductive layer made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). For example, the first electrode AE can have a three-layer structure of ITO / Ag / ITO. However, the present disclosure is not limited thereto. In addition, the first electrode AE can include a combination of two or more metal materials selected from the above-described metal materials or oxides of the above-described metal materials. However, the present disclosure is not limited thereto.

[0159] The hole control layer HTR can have a single layer made of a single material, a single layer made of a plurality of materials different from each other, or a multi-layer structure including a plurality of layers made of a plurality of materials different from each other. In one or more embodiments, the hole control layer HTR can include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. In addition, in one or more embodiments, the hole control layer HTR can further include a light emission auxiliary layer for compensating a resonance distance according to a wavelength of light emitted from the light emitting layers EL1, EL2, and EL3.

[0160] The hole control layer HTR can include phthalocyanine compounds such as copper phthalocyanine, DNTPD (N1,N1'-([1,1'-biphenyl]-4,4'-diyl)bis(N1-phenyl-N4,N4-dimethylphenylbenzene-1,4-diamine)), m-MTDATA (4,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine), TDATA (4,4',4"-tris(N,N-diphenylamino)triphenylamine), 2-TNATA (4,4',4"-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), PEDOT / PSS (poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate)), PANI / DBSA (polyaniline / dodecylbenzenesulfonic acid), PANI / CSA (polyaniline / camphor sulfonic acid), PANI / PSS (polyaniline / poly(4-styrenesulfonate)), NPB (N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine), triphenylamine-containing polyether ketone (TPAPEK), 4-isopropyl-4'-methyl diphenyl iodonium [tetra(pentafluorophenyl)borate], and / or HATCN (dipyrazino[2,3-f:2',3'-h]quinoxaline-2,3,6,7,10,11-hexacarbonitrile).

[0161] Further, the hole control layer HTR can include carbazole derivatives such as N-phenylcarbazole and / or polyvinylcarbazole, fluorene derivatives, TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), triphenylamine derivatives such as TCTA (4,4,4"tris(N-carbazolyl)triphenylamine), TAPC (4,4'-cyclohexylidenebis[N,N-bis(4-methylphenyl)benzenamine]), HMTPD (4,4'-bis[N,N'-(3-methylphenyl)amino]-3,3'-dimethylbiphenyl), CzSi (9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole), CCP (9-phenyl-9H-3,9'-bicarbazole), mCP (1,3-bis(N-carbazolyl)benzene), or mDCP (1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene).

[0162] The light emitting layers EL1, EL2, and EL3 can have a single layer structure made of a single material, a multi-layer structure made of a plurality of materials different from each other, or a multi-layer structure including a plurality of layers made of a plurality of materials different from each other. The light emitting layers EL1, EL2, and EL3 can contain anthracene derivatives, pyrene derivatives, fluoranthene derivatives, 1,2-benzo[ghi]phenanthrene derivatives, dihydrobenzanthracene derivatives, or triphenylene derivatives.

[0163] For example, the light-emitting layers EL1, EL2, and EL3 can include one host and one dopant. Alternatively, the light-emitting layers EL1, EL2, and EL3 can include two or more hosts and dopants.

[0164] The light-emitting layer EL3 of the third light-emitting element LD3 that emits blue light can emit thermally activated delayed fluorescence (TADF) or phosphorescence. The light-emitting layer EL3 of the third light-emitting element LD3 can include a TADF material and / or a phosphorescent material. The third light-emitting element LD3 containing the TADF material and / or the phosphorescent material can exhibit suitable light-emitting efficiency.

[0165] The light-emitting layers EL1, EL2, and EL3 can include a styryl derivative (e.g., 1,4-bis[2-(3-N-ethylcarbazolyl)vinyl]benzene (BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene (DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylaniline (N-BDAVBi)), 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl (DPAVBi), perylene, and / or a perylene derivative (e.g., 2,5,8,11-tetra-tert-butylperylene (TBP)), pyrene, and / or a pyrene derivative (e.g., 1,1-dipyrene, 1,4-dipyrenylbenzene, 1,4-bis(N,N-diphenylamino)pyrene) as a well-known dopant material.

[0166] The light-emitting layers EL1, EL2, and EL3 can include a well-known phosphorescent dopant material. For example, as a phosphorescent dopant, a metal complex including iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm) can be used. For example, FIrPic (bis(4,6-difluorophenylpyridinato-N,C2') picolinate iridium(III)), FIr6 (bis(2,4-difluorophenylpyridinato)-tetrakis(1-pyrazolyl)borate iridium(III)), or PtOEP (octaethylporphyrin platinum) can be used as a phosphorescent dopant. However, the present disclosure is not limited thereto.

[0167] In one or more embodiments, the electron control layer ETR can include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer. The electron control layer ETR can have a single layer made of a single material, a single layer made of a plurality of materials different from each other, or a multi-layer structure including a plurality of layers made of a plurality of materials different from each other.

[0168] The electron control layer ETR can include an anthracene compound. However, the present disclosure is not limited thereto. For example, the electron control layer ETR can include Alq3 (tris(8-hydroxyquinoline)aluminum), 1,3,5-tris[(3-pyridyl)-3-phenyl]benzene, 2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine, 2-(4-(N-phenylbenzoimidazol-1-yl)phenyl)-9,10-dinaphthylanthracene, TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene), BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-diphenyl-1,10-phenanthroline), TAZ (3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ (4-(naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD (2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq (bis(2-methyl-8-octahydroxyquinolinatoaluminum-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum), Bebq2 (bis(benzoquinoline-10-hydroxy)beryllium), ADN (9,10-di(naphthalen-2-yl)anthracene), BmPyPhB (1,3-bis[3,5-di(pyridin-3-yl)phenyl]benzene), and / or a mixture thereof.

[0169] Further, the electron control layer ETR can include a metal halide such as LiF, NaCl, CsF, RbCl, RbI, CuI, and / or KI, a lanthanide metal such as Yb, or a co-deposited material of the above metal halide and / or lanthanide metal. For example, the electron control layer ETR can include a co-deposited material such as KI:Yb, RbI:Yb, and / or LiF:Yb. The electron control layer ETR can be made of a metal oxide such as Li2O and / or BaO or Liq (lithium 8-hydroxyquinolate). However, the present disclosure is not limited thereto. The electron control layer ETR can be made of a material in which an electron transport material and an insulating organic metal salt are mixed. The organic metal salt can be a material having an energy band gap of about 4 eV or more. For example, the organic metal salt can include a metal acetate, a metal benzoate, a metal acetoacetate, a metal acetylacetone, or a metal stearate.

[0170] The second electrode CE can be a common electrode. Although the second electrode CE can be a cathode, the present disclosure is not limited thereto. The second electrode CE can include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, a compound selected from at least two of them, a mixture selected from at least two of them, and / or an oxide thereof.

[0171] In one or more embodiments, the light emitting elements LD1, LD2, and LD3 can further include a capping layer on the second electrode CE. The capping layer can be an organic layer or an inorganic layer. For example, when the capping layer includes an inorganic material, the inorganic material can include an alkali metal compound (such as LiF) and / or an alkaline earth metal compound (such as MgF2, SiON, SiN X , and / or SiO y ). For example, when the capping layer includes an organic material, the organic material can include α-NPD (N'-bis(naphthalen-1-yl)-N,N'-di(phenyl)-2,2'-dimethylbenzidine), NPB, TPD, m-MTDATA, Alq3, CuPc (copper phthalocyanine), TPD15 (N4,N4,N4',N4'-tetrakis(4-biphenyl-4-yl) biphenyl-4,4'-diamine), and / or TCTA (4,4',4"-tris(carbazol-9-yl)triphenylamine), or can include an epoxy resin or an acrylate such as a methacrylate.

[0172] In one or more embodiments, the encapsulation layer TFE can cover the display element layer DP-ED. The encapsulation layer TFE can be a thin film encapsulation layer. The encapsulation layer TFE includes at least one inorganic encapsulation layer or an organic encapsulation layer on the inorganic encapsulation layer. The encapsulation layer TFE will be described later in detail with reference to FIG. 9 .

[0173] FIG. 9 A cross-sectional view illustrating a partial configuration of a display module according to one or more embodiments of the disclosure. FIG. 7 A cross-sectional layer stack structure of the encapsulation layer TFE and layers adjacent to the upper and lower portions of the encapsulation layer TFE is illustrated. The description of the encapsulation layer TFE in FIG. 8 may be applied to the encapsulation layer TFE of the display panel DP in FIG. 9 and FIG. 7 .

[0174] With reference to FIG. 8 , the encapsulation layer TFE includes an inorganic encapsulation layer T-IOL and an organic encapsulation layer T-OL. The encapsulation layer TFE can include the inorganic encapsulation layer T-IOL on the display element layer DP-ED and the organic encapsulation layer T-OL on the inorganic encapsulation layer T-IOL.

[0175] The inorganic encapsulation layer T-IOL can be located on the display element layer DP-ED to protect the display element layer DP-ED from moisture and / or oxygen. The inorganic encapsulation layer T-IOL can include a material having a high refractive index. The inorganic encapsulation layer T-IOL can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0176] The inorganic encapsulation layer T-IOL can include a first inorganic encapsulation layer T-IOL1, a second inorganic encapsulation layer T-IOL2, and a third inorganic encapsulation layer T-IOL3, which are sequentially stacked. The first inorganic encapsulation layer T-IOL1 can be located on the display element layer DP-ED, the second inorganic encapsulation layer T-IOL2 can be located on the first inorganic encapsulation layer T-IOL1, and the third inorganic encapsulation layer T-IOL3 can be located on the second inorganic encapsulation layer T-IOL2.

[0177] The first inorganic encapsulation layer T-IOL1 can be directly located on the display element layer DP-ED. The first inorganic encapsulation layer T-IOL1 can be directly located on FIG. 7 and FIG. 8 the above-described light emitting element LD (LD1, LD2, LD3) in order to cover the light emitting element LD (LD1, LD2, LD3). The first inorganic encapsulation layer T-IOL1 can be directly located on the second electrode CE of the light emitting element LD (LD1, LD2, LD3). If the light emitting element LD (LD1, LD2, LD3) further includes a capping layer, the first inorganic encapsulation layer T-IOL1 can be directly located on the capping layer.

[0178] The second inorganic encapsulation layer T-IOL2 can be directly located on the first inorganic encapsulation layer T-IOL1. The third inorganic encapsulation layer T-IOL3 can be directly located on the second inorganic encapsulation layer T-IOL2. The first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can have a layered structure of a continuous stack without another layer therebetween.

[0179] Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can be made of the same precursor material. Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can be made of a silicon precursor material. Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can include the same material. Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can include at least one of silicon nitride, silicon oxynitride, and silicon oxide. For example, the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can all be made of silicon nitride.

[0180] Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 has a high refractive index. In one or more embodiments, each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can have a refractive index of about 1.90 or more and about 2.10 or less. Further, each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can have a refractive index of about 1.90 or more and about 2.10 or less in a wavelength range of about 430 nm or more and about 490 nm or less. Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can have a refractive index of about 1.90 or more and about 2.10 or less in a wavelength range of a blue light region.

[0181] The second inorganic encapsulation layer T-IOL2 can have a thickness TH2 that is greater than each of a thickness TH1 of the first inorganic encapsulation layer T-IOL1 and a thickness TH3 of the third inorganic encapsulation layer T-IOL3. The thickness TH1 of the first inorganic encapsulation layer T-IOL1 can be substantially equal to the thickness TH3 of the third inorganic encapsulation layer T-IOL3. The second inorganic encapsulation layer T-IOL2 can have a thickness TH2 of about about 1.90 µm or more and about 2.10 µm or less. Each of the thickness TH1 of the first inorganic encapsulation layer T-IOL1 and the thickness TH3 of the third inorganic encapsulation layer T-IOL3 can be about 1.90 µm or more and about 2.10 µm or less. The inorganic encapsulation layers T-IOL can have a total thickness TH5 of about 1.90 µm or more and about 2.10 µm or less. Each of the thickness TH1 of the first inorganic encapsulation layer T-IOL1 and the thickness TH3 of the third inorganic encapsulation layer T-IOL3 can be about 1.90 µm or more and about 2.10 µm or less. The inorganic encapsulation layers T-IOL can have a total thickness TH5 of about 1.90 µm or more and about 2.10 µm or less. Each of the thickness TH1 of the first inorganic encapsulation layer T-IOL1 and the thickness TH3 of the third inorganic encapsulation layer T-IOL3 can be about 1.90 µm or more and about 2.10 µm or less. The inorganic encapsulation layers T-IOL can have a total thickness TH5 of about

[0182] The second inorganic encapsulation layer T-IOL2 can have a thickness TH2 that is equal to or greater than about 100 times each of a thickness TH1 of the first inorganic encapsulation layer T-IOL1 and a thickness TH3 of the third inorganic encapsulation layer T-IOL3. A process for manufacturing the second inorganic encapsulation layer T-IOL2 can be different from a process for manufacturing each of the first inorganic encapsulation layer T-IOL1 and the third inorganic encapsulation layer T-IOL3 such that the second inorganic encapsulation layer T-IOL2 has a thickness that is equal to or greater than about 100 times each of a thickness of the first inorganic encapsulation layer T-IOL1 and a thickness of the third inorganic encapsulation layer T-IOL3.

[0183] The second inorganic encapsulation layer T-IOL2 with a large thickness can have a planarization property. That is, the second inorganic encapsulation layer T-IOL2 can have a planarized top surface. In an embodiment, the top surface of the second inorganic encapsulation layer T-IOL2 can include a planarized surface. The second inorganic encapsulation layer T-IOL2 can planarize a step portion generated by a foreign matter located thereunder or a step portion generated by a pixel definition layer PDL in FIG. 7 and FIG. 7 to provide a planarized top surface.

[0184] The second inorganic encapsulation layer T-IOL2 can have a moderate moisture barrier property. The second inorganic encapsulation layer T-IOL2 can have a water vapor transmission rate of about 1 x 10 -4 grams per square meter per day or more and about 9 x 10 -4 grams per square meter per day or less.

[0185] The organic encapsulation layer T-OL is located on the inorganic encapsulation layer T-IOL. The organic encapsulation layer T-OL can be directly located on the third inorganic encapsulation layer T-IOL3. The organic encapsulation layer T-OL can protect the display element layer DP-ED from foreign matters such as dust particles. The organic encapsulation layer T-OL can have a refractive index smaller than that of the inorganic encapsulation layer T-IOL. The organic encapsulation layer T-OL can include acrylate-based compounds, epoxy-based compounds, and vinyl-based compounds. The organic encapsulation layer T-OL can include a photopolymerizable organic material. However, the present disclosure is not limited thereto.

[0186] The organic encapsulation layer T-OL can have a thickness TH4 greater than a thickness TH5 of the inorganic encapsulation layer T-IOL. For example, the organic encapsulation layer T-OL can have a thickness TH4 of about 3 μm or more and about 8 μm or less. The organic encapsulation layer T-OL having a thickness less than about 3 μm can not be sufficient to protect the display element layer DP-ED from foreign matters. Further, the organic encapsulation layer T-OL having a thickness greater than about 8 μm can undesirably reduce an output of light emitted from the display element layer DP-ED. The organic encapsulation layer T-OL having a thickness TH4 of about 3 μm to about 8 μm can exhibit appropriate sealing reliability and help to maintain a satisfactory display quality.

[0187] In the encapsulation layer TFE according to one or more embodiments, the organic encapsulation layer T-OL has a relatively low dielectric constant. The organic encapsulation layer T-OL can include a material having a low dielectric constant. In one or more embodiments, the organic encapsulation layer T-OL has a dielectric constant (Dk) of about 1.0 or more and about 2.5 or less.

[0188] The organic encapsulation layer T-OL can comprise a polymeric material with high molecular anisotropy, and therefore can have a smaller dielectric constant than that of a typical organic layer comprising a polymer with low molecular anisotropy. In the encapsulation layer TFE according to one or more embodiments, the organic encapsulation layer T-OL can comprise (meth)acrylate polymers, epoxy polymers, and / or vinyl polymers. (Meth)acrylate polymers represent acrylate polymers or methacrylate polymers.

[0189] The organic encapsulation layer T-OL can comprise a polymer material with high molecular anisotropy and can possess low dielectric constant properties by including appropriate free volumes within the polymer molecules. Simultaneously, the organic encapsulation layer T-OL can possess the strength properties required for the encapsulation layer TFE. According to one or more embodiments, the encapsulation layer TFE can reduce the input sensor IS (referencing) located on the encapsulation layer TFE due to the low dielectric constant properties of the organic encapsulation layer T-OL. FIG. 7 This reduces noise and improves the touch sensitivity of the input sensor IS. Specifically, according to one or more embodiments, the encapsulation layer TFE can reduce the noise between the second electrode CE located below the encapsulation layer TFE and the sensor conductive layers IS-CL1 and IS-CL2 located on the encapsulation layer TF by including an organic encapsulation layer T-OL with low dielectric constant properties (see reference). FIG. 9 The capacitance between the two is used to improve the touch sensitivity of the input sensor IS.

[0190] The top surface of the organic encapsulation layer T-OL can define the uppermost surface of the encapsulation layer TFE. Other components within the encapsulation layer TFE may not be located on the organic encapsulation layer T-OL. Input sensor IS (reference) FIG. 7 It can be located directly on the organic encapsulation layer T-OL. For example... FIG. 1A As shown, the first sensor insulating layer IS-IL1 of the input sensor IS can be directly located on the organic encapsulation layer T-OL. In the display panel DP (reference) according to one or more embodiments... FIG. 1B In this process, other components may not be located on the organic encapsulation layer T-OL, which is included in the encapsulation layer TFE.

[0191] The encapsulation layer TFE, comprising an inorganic encapsulation layer T-IOL and an organic encapsulation layer T-OL, can have a total thickness TH6 of about 3.2 μm or more and about 8.2 μm or less. According to one or more embodiments, the encapsulation layer TFE can have a structure with reduced total thickness because, unlike typical encapsulation layer structures, the encapsulation layer TFE does not include an additional inorganic encapsulation layer located on the organic encapsulation layer T-OL. Therefore, when the encapsulation layer TFE is applied to, for example... FIG. 1C , FIG. 6 and FIG. 7When the foldable display device DD shown is used, the possibility of cracks caused by the folding operation can be reduced or prevented, and although the display panel DP (reference) FIG. 10A A portion of it is bent, but it can be done without cracking.

[0192] The encapsulation layer TFE included in the display panel according to one or more embodiments may include an inorganic encapsulation layer T-IOL having a three-layer structure, and an organic encapsulation layer T-OL located on the inorganic encapsulation layer T-IOL having low dielectric constant characteristics. Therefore, when the encapsulation layer TFE is applied to the display panel, the encapsulation layer TFE can reduce the overall thickness and improve the touch sensitivity of the input sensor IS located above it. For example, because the encapsulation layer TFE includes a first inorganic encapsulation layer T-IOL1, a second inorganic encapsulation layer T-IOL2, and a third inorganic encapsulation layer T-IL3 stacked in sequence, and because the second inorganic encapsulation layer T-IOL2 has a structure with a relatively large thickness, the encapsulation layer TFE can have suitable isolation characteristics and can reduce the overall thickness, even though no additional inorganic encapsulation layer is provided on the organic encapsulation layer T-OL. Although the thickness of the encapsulation layer TFE is reduced, because the organic encapsulation layer T-OL contains a material with a low dielectric constant (Dk), the thickness of the input sensor IS (see reference) located on the encapsulation layer TFE can be reduced. FIG. 10B It reduces noise and can improve the touch sensitivity of the input sensor IS.

[0193] FIG. 11A This is a flowchart illustrating a method for manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 11B This is a flowchart illustrating some processes of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 11C , FIG. 11D , FIG. 11E , FIG. 10B and FIG. 11A Cross-sectional views are provided to illustrate some processes of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 11B Each process included in the process of forming an encapsulation layer in a method for manufacturing a display panel according to one or more embodiments of the present disclosure is illustrated. FIG. 11C , FIG. 11D , FIG. 11E , FIG. 10A and FIG. 10B The figures illustrate cross-sections of the process for forming an encapsulation layer in a method for manufacturing a display panel according to one or more embodiments of the present disclosure.

[0194] refer to FIG. 5 to FIG. 9A method for manufacturing a display panel according to one or more embodiments includes a process S100 of forming a display element layer including a pixel definition layer and a light emitting element; and a process S200 of forming an encapsulation layer on the display element layer. With reference to FIG. 11A A process S200 of forming an encapsulation layer according to one or more embodiments includes a process S201 of forming a first inorganic encapsulation layer on the display element layer; a process S202 of forming a second inorganic encapsulation layer on the first inorganic encapsulation layer; a process S203 of forming a third inorganic encapsulation layer on the second inorganic encapsulation layer; and a process S204 of forming an organic encapsulation layer on the third inorganic encapsulation layer. The description of the configuration of each of the display element layer and the encapsulation layer can be the same as the description of the configuration of each of the display element layer and the encapsulation layer described in FIG. 11B .

[0195] FIG. 11C , FIG. 11D , FIG. 11E , FIG. 9 and FIG. 10B are sequentially illustrated on a cross-section corresponding to FIG. 11A .

[0196] With reference to FIG. 11B , FIG. 7 and FIG. 8 , a process S200 of forming an encapsulation layer in a method for manufacturing a display panel according to one or more embodiments includes a process S201 of forming a first inorganic encapsulation layer T-IOL1 on a display element layer DP-ED.

[0197] The first inorganic encapsulation layer T-IOL1 can be formed by providing a first inorganic deposition material DPM1 on a top surface of the display element layer DP-ED. The first inorganic encapsulation layer T-IOL1 can be formed directly on the display element layer DP-ED. The first inorganic encapsulation layer T-IOL1 can be formed directly on the above-described light emitting elements LD (LD1, LD2, LD3) in FIG. 10B and FIG. 11B to cover the light emitting elements LD (LD1, LD2, LD3). The first inorganic encapsulation layer T-IOL1 can be formed directly on the second electrode CE of the light emitting elements LD (LD1, LD2, LD3). When the light emitting elements LD (LD1, LD2, LD3) further include a capping layer, the first inorganic encapsulation layer T-IOL1 can be formed directly on the capping layer.

[0198] With reference to FIG. 11C , FIG. 10B and FIG. 11CThe process S200 of forming the encapsulation layer in the method for manufacturing the display panel according to one or more embodiments includes a process S202 of forming a second inorganic encapsulation layer T-IOL2 on the first inorganic encapsulation layer T-IOL1.

[0199] The second inorganic encapsulation layer T-IOL2 can be formed by providing a second inorganic deposition material DPM2 on a top surface of the first inorganic encapsulation layer T-IOL1. The second inorganic encapsulation layer T-IOL2 can be formed directly on the first inorganic encapsulation layer T-IOL1.

[0200] Referring to FIG. 11D , FIG. 10B and FIG. 11D The process S200 of forming the encapsulation layer in the method for manufacturing the display panel according to one or more embodiments includes a process S203 of forming a third inorganic encapsulation layer T-IOL3 on the second inorganic encapsulation layer T-IOL2.

[0201] The third inorganic encapsulation layer T-IOL3 can be formed by providing a third inorganic deposition material DPM3 on a top surface of the second inorganic encapsulation layer T-IOL2. The third inorganic encapsulation layer T-IOL3 can be formed directly on the second inorganic encapsulation layer T-IOL2.

[0202] Each of the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can be made of the same precursor material. That is, the first inorganic deposition material DPM1, the second inorganic deposition material DPM2, and the third inorganic deposition material DPM3 that respectively form the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 can be identical to each other. Each of the first inorganic deposition material DPM1, the second inorganic deposition material DPM2, and the third inorganic deposition material DPM3 can include the same silicon precursor. In one or more embodiments, each of the first inorganic deposition material DPM1, the second inorganic deposition material DPM2, and the third inorganic deposition material DPM3 can include silicon nitride. Since the first inorganic encapsulation layer T-IOL1, the second inorganic encapsulation layer T-IOL2, and the third inorganic encapsulation layer T-IOL3 are made of the same precursor material, the process for forming the first inorganic encapsulation layer T-IOL1, the process for forming the second inorganic encapsulation layer T-IOL2, and the process for forming the third inorganic encapsulation layer T-IOL3 can be performed as a continuous process in the same chamber. However, the present disclosure is not limited thereto. The process for forming the first inorganic encapsulation layer T-IOL1, the process for forming the second inorganic encapsulation layer T-IOL2, and the process for forming the third inorganic encapsulation layer T-IOL3 can be performed in different chambers.

[0203] As described above, the second inorganic encapsulation layer T-IOL2 can have a thickness greater than each of a thickness of the first inorganic encapsulation layer T-IOL1 and a thickness of the third inorganic encapsulation layer T-IOL3. The second inorganic encapsulation layer T-IOL2 can have a thickness equal to or greater than about 100 times each of a thickness of the first inorganic encapsulation layer T-IOL1 and a thickness of the third inorganic encapsulation layer T-IOL3. A process for forming the second inorganic encapsulation layer T-IOL2 can be different from a process for forming each of the first inorganic encapsulation layer T-IOL1 and the third inorganic encapsulation layer T-IOL3, such that the second inorganic encapsulation layer T-IOL2 has a thickness equal to or greater than about 100 times each of a thickness of the first inorganic encapsulation layer T-IOL1 and a thickness of the third inorganic encapsulation layer T-IOL3.

[0204] In one or more embodiments, each of the process S201 of forming the first inorganic encapsulation layer T-IOL1 and the process S203 of forming the third inorganic encapsulation layer T-IOL3 can be performed by a plasma enhanced atomic layer deposition (PEALD) or a physical vapor deposition process. For example, each of the process S201 of forming the first inorganic encapsulation layer T-IOL1 and the process S203 of forming the third inorganic encapsulation layer T-IOL3 can be performed by a plasma enhanced atomic layer deposition (PEALD), sputtering, thermal evaporation, or e-beam evaporation. The process S202 of forming the second inorganic encapsulation layer T-IOL2 can be performed by a plasma enhanced chemical vapor deposition (PECVD) process. Each of the first inorganic encapsulation layer T-IOL1 and the third inorganic encapsulation layer T-IOL3 can be formed by a PEALD or a physical vapor deposition process to have a relatively thin thickness and to have a relatively high isolation characteristic, and the second inorganic encapsulation layer T-IOL2 can be formed by a PECVD process to have a relatively large thickness.

[0205] Referring to FIG. 11E , FIG. 7 and ​ , the process S200 of forming an encapsulation layer in the method for manufacturing a display panel according to one or more embodiments includes a process S204 of forming an organic encapsulation layer T-OL on the third inorganic encapsulation layer T-IOL3.

[0206] The organic encapsulation layer T-OL can be formed by providing an organic material OM on a top surface of the third inorganic encapsulation layer T-IOL3. The organic encapsulation layer T-OL can be formed directly on the third inorganic encapsulation layer T-IOL3.

[0207] Organic material OM can be provided onto the third inorganic encapsulation layer T-IOL3 using processes such as inkjet printing, screen printing, spin coating, and slot coating. Organic material OM can have a low dielectric constant. In one or more embodiments, organic material OM can have a dielectric constant (Dk) of more than about 1.0 and less than about 2.5. Organic material OM can comprise polymeric materials with high molecular anisotropy, and therefore can have a smaller dielectric constant than that of typical organic layers comprising polymers with low molecular anisotropy. In a method for manufacturing a display panel according to one or more embodiments, organic material OM can comprise (meth)acrylate polymers, epoxy polymers, and / or vinyl polymers.

[0208] In a method for manufacturing a display panel according to one or more embodiments, the process of forming the encapsulation layer TFE can be completed after the process of forming the organic encapsulation layer T-OL, and the top surface of the organic encapsulation layer T-OL can define the top surface of the encapsulation layer TFE. Other components may not be attached to the organic encapsulation layer T-OL in the encapsulation layer TFE. After the process of forming the organic encapsulation layer T-OL, an input sensor IS (referencing) can be formed on the organic encapsulation layer T-OL. ​ The first sensor insulating layer IS-IL1 can be formed directly on the organic encapsulation layer T-OL. The method for manufacturing a display panel according to one or more embodiments may exclude the process of forming an additional inorganic encapsulation layer on the organic encapsulation layer T-OL.

[0209] In the method for manufacturing a display panel according to one or more embodiments, since the process of forming the encapsulation layer TFE includes a process of forming an inorganic encapsulation layer T-IOL having a three-layer structure and a process of forming an organic encapsulation layer T-OL located on the inorganic encapsulation layer T-IOL, the display panel formed by the method for manufacturing the display panel can have a reduced overall thickness, and the touch sensitivity of the input sensor can be improved when the input sensor is subsequently formed on the display panel.

[0210] According to embodiments of this disclosure, the flexibility can be improved by reducing the thickness of the display panel, and the sensing performance of the input sensor can be improved.

[0211] According to embodiments of this disclosure, display panels with reduced thickness can be manufactured by simplifying the process.

[0212] Although embodiments of this disclosure have been described, it is to be understood that this disclosure should not be limited to these embodiments, but rather various changes and modifications can be made by those skilled in the art within the spirit and scope of the claimed disclosure. Therefore, the true scope of this disclosure should be determined by the appended claims and the technical scope of its functional equivalents to be included therein.

Claims

1. A display panel, characterized by, The display panel includes: a display element layer including a pixel definition layer and a light emitting element, the pixel definition layer defining a pixel opening; and an encapsulation layer on the display element layer, and including: a first inorganic encapsulation layer on the display element layer, having a refractive index of 1.90 or more and 2.10 or less; a second inorganic encapsulation layer on the first inorganic encapsulation layer, having a refractive index of 1.90 or more and 2.10 or less; a third inorganic encapsulation layer on the second inorganic encapsulation layer, having a refractive index of 1.90 or more and 2.10 or less; and an organic encapsulation layer on the third inorganic encapsulation layer, having a dielectric constant of 1.0 or more and 2.5 or less.

2. The display panel of claim 1, wherein, The organic encapsulation layer is directly on the third inorganic encapsulation layer, and wherein the second inorganic encapsulation layer is directly on the first inorganic encapsulation layer, and wherein the third inorganic encapsulation layer is directly on the second inorganic encapsulation layer.

3. The display panel of claim 1, wherein, The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer include the same material, and wherein each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer includes one of silicon nitride, silicon oxide, and silicon oxynitride.

4. The display panel of claim 1, wherein, The second inorganic encapsulation layer has a thickness that is greater than a thickness of the first inorganic encapsulation layer and greater than a thickness of the third inorganic encapsulation layer.

5. The display panel of claim 1, wherein, Each of the first inorganic encapsulation layer and the third inorganic encapsulation layer has The above and The following thicknesses, wherein the second inorganic encapsulation layer has The above and a thickness of wherein the organic encapsulation layer has a thickness of 3 µm or more and 8 µm or less, wherein a top surface of the second inorganic encapsulation layer includes a planarized surface, and wherein the second inorganic encapsulating layer has a water vapor transmission rate of 1 x 10 -4 g / m2day or more and 9 x 10 -4 g / m2day or less.

6. The display panel of claim 1, wherein, The encapsulation layer covers the light emitting element, wherein the light emitting element includes a first electrode exposed through the pixel opening, a second electrode over the first electrode, and a light emitting layer between the first electrode and the second electrode, and wherein the light emitting element further includes a hole control layer between the first electrode and the light emitting layer, and an electron control layer between the light emitting layer and the second electrode.

7. The display panel of any one of claims 1-6, wherein, A top surface of the organic encapsulation layer defines an uppermost surface of the encapsulation layer.

8. An electronic device, comprising: The electronic device includes: an input sensor; and a display panel below the input sensor, the display panel being the display panel according to any one of claims 1 to 7, wherein the pixel opening defines a light emitting area. 9.The electronic device of claim 8, wherein, The input sensor is directly on the organic encapsulation layer, and The input sensor includes: a first sensor insulating layer directly on the organic encapsulation layer; a first sensor conductive layer on the first sensor insulating layer, and including a first conductive pattern; a second sensor insulating layer on the first sensor insulating layer to cover the first sensor conductive layer; and a second sensor conductive layer on the second sensor insulating layer, and including a second conductive pattern. 10.The electronic device of claim 8, wherein, The electronic device further includes: a housing accommodating the display panel and the input sensor.

Images