Display device

Abstract

A display device is provided. The display device includes a display area and a non-display area. The display device includes a base layer including a first substrate, a first barrier layer on the first substrate, a second substrate on the first barrier layer, and a second barrier layer on the second substrate, a light emitting element disposed on the base layer in a display area, and an upper organic layer disposed across the display area and a non-display area. Each of the first substrate and the second substrate includes an organic material. Each of the first barrier layer and the second barrier layer includes an inorganic material. The non-display area includes an organic contact area, and the second barrier layer exposes the second substrate in the organic contact area. The upper organic layer and the second substrate are in contact with each other in the organic contact region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0062922, filed with the Korean Intellectual Property Office on May 14, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device and a method for manufacturing a display device. Background Technology

[0004] In recent years, with the increasing interest in information display, research and development of display devices have been ongoing.

[0005] Display devices need to have robust characteristics against external environments. For example, display devices need structures that prevent risks associated with impurity penetration (such as moisture ingress) or stress generation.

[0006] It should be understood that the background section of this technical section is partly intended to provide useful background for understanding the technology. However, the background section of this technical section may also include ideas, concepts, or knowledge that were not known or understood by a person skilled in the art prior to the corresponding valid application date of the subject matter disclosed herein. Utility Model Content

[0007] This disclosure provides a display device with robust characteristics against external environments and a method for manufacturing the display device.

[0008] This disclosure provides a display device in which the risks of moisture penetration and stress are reduced, as well as a method for manufacturing the display device.

[0009] This disclosure provides a display device in which the risk of delamination of inorganic layers included in the display device can be reduced, as well as a method for manufacturing the display device.

[0010] According to embodiments of this disclosure, a display device including a display area and a non-display area may include a base layer comprising a first substrate, a first barrier layer on the first substrate, a second substrate on the first barrier layer, and a second barrier layer on the second substrate, a light-emitting element disposed on the base layer in the display area, and an upper organic layer disposed throughout the display area and the non-display area. Each of the first substrate and the second substrate may be made of an organic material. Each of the first barrier layer and the second barrier layer may be made of an inorganic material. The non-display area may include an organic contact area, and the second barrier layer may expose the second substrate in the organic contact area. The upper organic layer and the second substrate may be in contact with each other in the organic contact area.

[0011] According to an embodiment, the display device can further include a buffer layer disposed on the second barrier layer, extending across the display area and the non-display area, an active layer disposed on the buffer layer in the display area, a gate insulating layer disposed on the buffer layer, extending across the display area and the non-display area, and covering the active layer, a gate conductive layer including at least a portion of the gate insulating layer disposed on the gate insulating layer in the display area, an interlayer insulating layer disposed on the gate insulating layer, extending across the display area and the non-display area, and covering the gate conductive layer, and a first inorganic insulating layer extending across the display area and the non-display area, and covering the light emitting element. The second barrier layer can include a barrier end portion in the non-display area. The buffer layer can include a buffer end portion in the non-display area. The gate insulating layer can include a gate insulating end portion in the non-display area. The interlayer insulating layer can include an interlayer insulating end portion in the non-display area. The first inorganic insulating layer can include a first inorganic insulating end portion in the non-display area.

[0012] According to an embodiment, the buffer layer and the active layer can contact each other. The buffer layer can expose the second base in the non-display area, and can not expose the second base in the display area.

[0013] According to an embodiment, the first inorganic insulating end portion can be disposed between the buffer end portion and the interlayer insulating end portion. The first inorganic insulating layer can cover a portion of an upper surface of the buffer layer, and expose another portion of the upper surface of the buffer layer in a portion of the non-display area. The upper organic layer and the buffer layer can contact each other at the other portion of the upper surface of the buffer layer exposed by the first inorganic insulating layer.

[0014] According to an embodiment, the barrier end portion and the buffer end portion can be directly adjacent to the organic contact area.

[0015] According to an embodiment, the barrier end portion and the buffer end portion can overlap each other in a plan view.

[0016] According to an embodiment, the gate insulating end portion and the interlayer insulating end portion can be covered by the first inorganic insulating layer.

[0017] According to an embodiment, the gate insulating end portion and the interlayer insulating end portion can overlap each other in a plan view.

[0018] According to an embodiment, the display device can further include a dam disposed in the dam region formed in the non-display area, an organic encapsulation layer including at least a portion disposed on the first inorganic insulation layer in a region surrounded by the dam, a second inorganic insulation layer covering the organic encapsulation layer and disposed on the first inorganic insulation layer, a first upper insulation layer disposed on the second inorganic insulation layer, a first conductive pattern layer disposed on the first upper insulation layer, a second upper insulation layer covering the first conductive pattern layer and disposed on the first upper insulation layer, and a second conductive pattern layer disposed on the second upper insulation layer. The second inorganic insulation layer can include a second inorganic insulation end portion in the non-display area. The first upper insulation layer can include a first upper insulation end portion in the non-display area. The second upper insulation layer can include a second upper insulation end portion in the non-display area.

[0019] According to an embodiment, the organic contact region can be formed outside the dam region. The first conductive pattern layer and the second conductive pattern layer can form a sensing electrode that obtains information related to a touch input of a user.

[0020] According to an embodiment, the second inorganic insulation end portion, the first upper insulation end portion, and the second upper insulation end portion can overlap each other in a plan view.

[0021] According to an embodiment, the upper organic layer can cover the second conductive pattern layer, the barrier end portion, the buffer end portion, the first inorganic insulation end portion, the second inorganic insulation end portion, the first upper insulation end portion, and the second upper insulation end portion, and can be spaced apart from the gate insulation end portion and the interlayer insulation end portion.

[0022] According to an embodiment, the display device can further include a polarization layer disposed on the upper organic layer. The polarization layer, the upper organic layer, the first base, the first barrier layer, and the second base can have end portions overlapping each other.

[0023] According to an embodiment, the display device can further include an organic protection layer disposed on the second conductive pattern layer and spaced apart from the organic contact region, and a polarization layer disposed on the upper organic layer. The upper organic layer can cover the organic protection layer.

[0024] According to embodiments of the present disclosure, a method of manufacturing a display device including a non-display area and a display area can include: providing a base layer including a first substrate, a first barrier layer on the first substrate, a second substrate on the first barrier layer, and a second barrier layer on the second substrate; arranging a buffer layer on the second barrier layer; arranging a gate insulating layer on the buffer layer; arranging an interlayer insulating layer on the gate insulating layer; exposing the buffer layer in a first exposed area that is a portion of the non-display area by removing at least portions of the gate insulating layer and the interlayer insulating layer; exposing the second substrate in a second exposed area that is a portion of the non-display area by removing at least portions of the second barrier layer and the buffer layer; forming a light emitting element on the base layer in the display area; forming a first inorganic insulating layer in which at least a portion covers the light emitting element; forming an organic encapsulation layer on the first inorganic insulating layer; forming a second inorganic insulating layer on the organic encapsulation layer; forming a first upper insulating layer on the second inorganic insulating layer; forming a second upper insulating layer on the first upper insulating layer; exposing the first inorganic insulating layer by removing at least portions of the second inorganic insulating layer, the first upper insulating layer, and the second upper insulating layer; exposing the second substrate by removing at least a portion of the first inorganic insulating layer; and forming an upper organic layer across the display area and the non-display area. Forming the upper organic layer can include contacting the upper organic layer and the second substrate in an organic contact area.

[0025] According to embodiments, the method of manufacturing a display device can further include performing a cutting process based on a cutting line defined in the organic contact area.

[0026] According to embodiments, the method of manufacturing a display device can further include patterning an active layer on the buffer layer. Exposing the buffer layer can include forming a contact portion of the active layer exposed.

[0027] According to embodiments, exposing the buffer layer can include forming a first step area defined by end portions of the gate insulating layer and the interlayer insulating layer. Exposing the second substrate in the second exposed area that is a portion of the non-display area by removing at least portions of the second barrier layer and the buffer layer can include forming a second step area defined by end portions of the second barrier layer and the buffer layer. Exposing the second substrate by removing at least a portion of the first inorganic insulating layer can include forming an end portion of the first inorganic insulating layer between the first step area and the second step area.

[0028] According to embodiments, exposing the second substrate in the second exposed area that is a portion of the non-display area by removing at least portions of the second barrier layer and the buffer layer can include etching the second barrier layer and the buffer layer using a first etching mask. Exposing the first inorganic insulating layer can include etching the second inorganic insulating layer, the first upper insulating layer, and the second upper insulating layer using a second etching mask.

[0029] According to embodiments, the method of manufacturing a display device can further include arranging a polarizing layer on the upper organic layer. Attached Figure Description

[0030] The above and other aspects, features, and advantages of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a schematic perspective view showing a display device according to an embodiment.

[0032] Figure 2 This is a schematic plan view showing a display device according to an embodiment.

[0033] Figure 3 This is a schematic cross-sectional view showing a display device according to an embodiment.

[0034] Figures 4 to 6 It is along Figure 2 A schematic cross-sectional view taken by line A-A'.

[0035] Figure 7 This is a schematic plan view showing a mother substrate comprising multiple unit cells, to explain a method for manufacturing a display device according to an embodiment.

[0036] Figures 8 to 19 This is a schematic cross-sectional view illustrating each process step of the method for manufacturing a display device according to an embodiment.

[0037] Figures 20 to 22 This is a schematic cross-sectional view illustrating each process step of the method for manufacturing a display device according to an embodiment.

[0038] Figures 23 to 26 This is a schematic cross-sectional view illustrating each process step of the method for manufacturing a display device according to an embodiment. Detailed Implementation

[0039] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The various embodiments are not necessarily exclusive, nor are they intended to limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0040] In the accompanying drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for ease of description and clarity. Throughout the specification, similar reference numerals refer to similar elements.

[0041] As used herein, the term "and / or," refers to a combination comprising at least one of the associated listed items. For example, "A and / or B" means "A, B, or A and B." The terms "and" and "or" can be used in either their conjunctive or disjunctive sense, and can be used synonymously with "and / or." The term "comprising" means "including, but not limited to."

[0042] For the purpose of their meaning and explanation, the term "at least one of... " is intended to include the meaning of "at least one selected from...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". The term "at least one of... ", when following a list of elements, modifies the entire list of elements and does not modify the individual elements of the list.

[0043] It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could later be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element could be termed a first element without departing from the teachings of the present disclosure.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] In view of related measurements and errors associated with measurements of recited quantities (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated value and mean within an acceptable range of deviation for the stated value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±20%, ±10%, ±5% of the stated value.

[0046] It should be understood that the terms "comprise", "comprising", "include", "including", "have", "has", and similar terms are intended to indicate that the stated features, integers, steps, operations, elements, components, and / or combinations thereof are present, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0047] In the present disclosure, it will be understood that when an element (or a region, layer, portion, etc.) is referred to as being "on", "connected to" or "coupled to" another element (or a region, layer, portion, etc.), it can be directly on, directly connected to, or directly coupled to, the other element or intervening elements can be present. In similar manner, when an element (or a region, layer, portion, etc.) is referred to as being "covered", it can be directly covered, or intervening elements can be present.

[0048] The terms "overlap", "overlapping" or "overlapped" mean that a first object can be above or below or to the side of a second object, and vice versa. The term "overlap" can include layering, stacking, facing, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0049] When an element is described as "not overlapping" or "not to overlap" another element, this can include that the elements are spaced apart, offset from each other, or separated from each other, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0050] In the present disclosure, when an element is "directly on", "directly connected to", or "directly coupled to" another element, then there are no intervening elements present. For example, "directly on" can mean that two layers or elements are disposed without additional elements such as adhesive elements therebetween.

[0051] Spatially relative terms "below", "beneath", "lower", "above", "upper" or similar terms can be used herein for ease of description to describe one element or component's or portion's relationship to another element or component's or portion's relationship as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, in the figures shown, the device is inverted, and as such, a device positioned "below" or "beneath" another device can be placed "above" the other device. Thus, the illustrative term "below" can include both lower and upper positions. The device can also be oriented in other directions, and as such, the spatially relative terms can be interpreted differently depending upon the orientation of the device.

[0052] The phrase "in plan view" means to view an object from the top, and the phrase "in a schematic cross-sectional view" means to view a cross-section of an object that is cut vertically from the side. Thus, the expression "in plan view" used herein can mean to view an object from the top in the third direction. The phrase "in a schematic cross-sectional view" means to view a cross-section of an object that is cut vertically from the side in the first direction or the second direction. The third direction can also be referred to as a "thickness direction."

[0053] Unless otherwise defined or implied in the text, all terms used (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless clearly defined in the specification. Further, the expression "A component is disposed throughout a B area" in the text can mean that the A component overlaps at least a portion of the B area in a plan view.

[0054] The present disclosure relates to a display apparatus and a method of manufacturing a display apparatus. Hereinafter, a display apparatus and a method of manufacturing a display apparatus according to an embodiment will be described with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view schematically illustrating a display apparatus according to an embodiment. Figure 2 is a plan view schematically illustrating a display apparatus according to an embodiment. Figure 3 is a cross-sectional view schematically illustrating a display apparatus according to an embodiment.

[0056] Referring to Figures 1 to 3 The display apparatus DD can provide (or emit) light. The display apparatus DD can include a panel PNL and a driving circuit unit DV for driving the panel PNL. The display apparatus DD can further include a polarization layer POL disposed on the panel PNL.

[0057] The panel PNL can include a display layer DP for displaying an image and a sensor layer TSP for sensing an input (e.g., a touch input) of a user. The display layer DP can be referred to as a display panel. The sensor layer TSP can be referred to as a sensing panel.

[0058] The panel PNL can include a sub-pixel SPX and a sensing electrode SP. In an embodiment, the sub-pixel SPX can display an image in units of a frame period. The sensing electrode SP can sense an input (e.g., a touch input) of a user in units of a frame period.

[0059] The display layer DP can output visual information (e.g., an image). In an embodiment, the display layer DP can include an organic light emitting diode or a light emitting diode including an inorganic material. However, the present disclosure is not limited to a specific example. Hereinafter, for the convenience of description, an embodiment in which the display layer DP includes an organic light emitting diode will be described as an example.

[0060] The display layer DP can include a base layer BSL and a sub-pixel SPX including a light emitting element LD (see Figure 4 ) provided on the base layer BSL. The sub-pixel SPX can be arranged in a display area DA. The sub-pixel SPX can form a pixel PXL.

[0061] The base layer BSL (or the display device DD) can include a display area DA displaying an image and a non-display area NDA which is an area other than the display area DA. The non-display area NDA can surround at least a portion of the display area DA.

[0062] The base layer BSL can form a base for layers forming the display layer DP. In an embodiment, the base layer BSL can include a multi-layer structure. In an embodiment, the base layer BSL can include a structure in which an organic layer and an inorganic layer are alternately stacked. For example, the base layer BSL can include a first substrate BS1 (see Figure 4 ), a first barrier layer BR1 (see Figure 4 ) on the first substrate BS1, a second substrate BS2 (see Figure 4 ) on the first barrier layer BR1, and a second barrier layer BR2 (see Figure 4 ) on the second substrate BS2.

[0063] The first substrate BS1 and the second substrate BS2 can include an organic material. The first barrier layer BR1 and the second barrier layer BR2 can include an inorganic material.

[0064] The base layer BSL can form a base of a mother substrate MS (see Figure 7 ). At least a portion of the mother substrate MS can be cut to form each base layer BSL of the display device DD.

[0065] The pixel PXL (or the sub-pixel SPX) can be arranged in an array structure such as a stripe, or the like. However, the present disclosure is not limited thereto, and various embodiments can be applicable to the present disclosure.

[0066] In an embodiment, the pixel PXL (or the sub-pixel SPX) can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be sub-pixels. At least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can form a pixel PXL that emits light of various colors.

[0067] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can emit light of one color. For example, the first sub-pixel SPX1 can be a red pixel that emits red (e.g., a first color) light, the second sub-pixel SPX2 can be a green pixel that emits green (e.g., a second color) light, and the third sub-pixel SPX3 can be a blue pixel that emits blue (e.g., a third color) light. The red pixel can provide light in a wavelength range of about 600 nm to about 750 nm. The green pixel can provide light in a wavelength range of about 480 nm to about 560 nm. The blue pixel can provide light in a wavelength range of about 370 nm to about 460 nm.

[0068] In an embodiment, the number of the second sub-pixels SPX2 can be greater than each of the number of the first sub-pixels SPX1 and the number of the third sub-pixels SPX3. However, the color, type, and / or number of the first sub-pixels SPX1, the second sub-pixels SPX2, and the third sub-pixels SPX3 forming each pixel PXL are not limited to specific examples.

[0069] In the display area DA, scan lines SL, data lines DL, and sub-pixels SPX electrically connected to the scan lines SL and the data lines DL can be arranged. The sub-pixels SPX can be selected by a scan signal of an on level supplied from the scan lines SL to receive a data signal from the data lines DL, and can emit light having a luminance corresponding to the data signal. Accordingly, an image corresponding to the data signal can be displayed in the display area DA.

[0070] In the non-display area NDA, various wiring and / or built-in circuit portions connected to the sub-pixels SPX in the display area DA can be arranged. For example, the wiring can be arranged in the non-display area NDA to supply various power sources and control signals to the display area DA.

[0071] The sensor layer TSP can obtain information related to a touch input of a user. The sensing electrode SP can include a first sensing electrode SP1 providing a first sensing signal and a second sensing electrode SP2 providing a second sensing signal. In an embodiment, such as mutual capacitance method, the first sensing electrode SP1 can be a Tx (transmitter) pattern electrode and the second sensing electrode SP2 can be a Rx (receiver) pattern electrode. The information related to the touch input (or touch event) can mean information including a position of a touch intended to be provided by the user. However, the disclosure is not limited thereto. In an embodiment, such as self-capacitance method, the sensing electrode SP can include a sensing electrode that does not distinguish the first sensing electrode SP1 and the second sensing electrode SP2.

[0072] The sensor layer TSP can be disposed (e.g., directly disposed) on the display layer DP. The sensor layer TSP can include a sensor base layer SBSL and a sensing electrode SP formed on the sensor base layer SBSL. The sensing electrode SP can be disposed in a sensing area SA on the sensor base layer SBSL.

[0073] The driving circuit unit DV can include a display driver (D-IC) DDV for driving the display layer DP and a sensor driver (T-IC) SDV for driving the sensor layer TSP.

[0074] The sensor base layer SBSL (or the display device DD) can include a sensing area SA configured to detect a touch input or the like and a non-sensing area NSA surrounding the sensing area SA. In an embodiment, the sensing area SA can be disposed to overlap at least one area of the display area DA. For example, the sensing area SA can correspond to the display area DA (e.g., the sensing area SA overlaps the display area DA), and the non-sensing area NSA can correspond to the non-display area NDA (e.g., the non-sensing area NSA overlaps the non-display area NDA). In a case where the touch input or the like is provided on the display area DA, the touch input can be detected by the sensor layer TSP.

[0075] The sensor base layer SBSL can include one or more insulating layers (e.g., a first upper insulating layer YIL1 (see Figure 4 )) for forming the sensor base layer SBSL can be disposed on the display layer DP to form a substrate on which the sensing electrode SP is formed.

[0076] The sensing area SA can be an area that can be responsive to a touch input, such as an active area of a sensor. The sensor layer TSP can obtain information related to a user input. In the non-sensing area NSA of the sensor layer TSP, a sensing line electrically connecting the sensing electrode SP to the sensor driver SDV and the like can be disposed.

[0077] In an embodiment, the first sensing electrode SP1 can extend in the first direction DR1. The first sensing electrode SP1 can be arranged in the second direction DR2. In an embodiment, the second sensing electrode SP2 can extend in the second direction DR2. The second sensing electrode SP2 can be arranged in the first direction DR1. The second direction DR2 can be different from the first direction DR1; for example, the second direction DR2 can be perpendicular to the first direction DR1.

[0078] The driving circuit unit DV can include a display driver DDV for driving the display layer DP and a sensor driver SDV for driving the sensor layer TSP.

[0079] The display driver DDV can be electrically connected to the display layer DP to drive the sub-pixel SPX. The sensor driver SDV can be electrically connected to the sensor layer TSP to drive the sensor layer TSP.

[0080] In an embodiment, the display device DD can further include a dam area DAA. For example, the dam area DAA can be defined (e.g., arranged) in the non-display area NDA (or non-sensing area NSA). The dam area DAA can be an area in which the first dam DAM1 (see Figure 4 ) and / or the second dam DAM2 are arranged.

[0081] The dam area DAA can be arranged at a periphery of the display area DA (or sensing area SA). In a plan view, the dam area DAA can completely surround the display area DA (or sensing area SA). For example, the dam area DAA can have a closed loop structure surrounding the display area DA (or sensing area SA).

[0082] As shown in a plan view, the plane defined in the present specification can extend in both the first direction DR1 and the second direction DR2, and can be defined based on a plane on which the base layer BSL is arranged. In an embodiment, the third direction DR3 can represent a thickness direction of the base layer BSL perpendicular to the plane in a plan view. The third direction DR3 can also correspond to a direction in which light is emitted from the display device DD.

[0083] The polarization layer POL can be arranged on the panel PNL (e.g., the sensor layer TSP). Light provided from the display layer DP can pass through the polarization layer POL and be output to the outside. The polarization layer POL can include a material having various polarization properties. For example, the polarization layer POL can include a phase retardation layer, and can also include a wire grid polarization layer.

[0084] Reference will be made to FIG. 1 showing a schematic cross-sectional structure of a display device DD according to an embodiment. Figures 4 to 6 A display device DD according to an embodiment is described. Figures 4 to 6 is along Figure 2Fig. 2 is a schematic cross-sectional view of the display device DD taken along the line A-A' of Fig. 1. These figures show regions from the non-display region NDA including the dam region DAA to the display region DA.

[0085] Reference will be made to Figure 4 a display device DD according to a first embodiment.

[0086] As described above, the display region DA and the sensing region SA can overlap each other in a plan view, and the non-display region NDA and the non-sensing region NSA can overlap each other in a plan view. Hereinafter, for the convenience of description, cross-sectional views of the display device DD will be described based on the display region DA and the non-display region NDA. Technical descriptions related to the display region DA can be equally applicable to structures related to the sensing region SA, and technical descriptions related to the non-display region NDA can be similarly applicable to structures related to the non-sensing region NSA.

[0087] In embodiments, the display device DD can include a base layer BSL.

[0088] The base layer BSL can include a first substrate BS1 and a second substrate BS2 each including an organic material, and a first barrier layer BR1 and a second barrier layer BR2 each including an inorganic material. For example, the organic material can include, but is not limited to, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB). In embodiments, the first substrate BS1 and the second substrate BS2 can include a polyimide resin. The inorganic material can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0089] The second barrier layer BR2 can be disposed on the second substrate BS2 throughout the display region DA and the non-display region NDA while exposing at least a portion of the second substrate BS2. The portion of the upper surface of the second substrate BS2 exposed by the second barrier layer BR2 can be disposed in the non-display region NDA and defined outside the dam region DAA. In embodiments, the second substrate BS2 can not be exposed by the second barrier layer BR2 in the display region DA.

[0090] At least a portion of the second base BS2 exposed by the second barrier layer BR2 can include an organic contact area COA. The organic contact area COA can be part of the base layer BSL and can be an area of the second base BS2 that contacts the upper organic layer UOL. The organic contact area COA can be included in the non-display area NDA.

[0091] An end portion (e.g., a barrier end portion EP1) of the second barrier layer BR2 can be directly adjacent to the organic contact area COA. The barrier end portion EP1 of the second barrier layer BR2 can be directly adjacent to the upper organic layer UOL.

[0092] In an embodiment, the display device DD can include a buffer layer BFL.

[0093] The buffer layer BFL can be disposed throughout the display area DA and the non-display area NDA and can be disposed on the second barrier layer BR2. The buffer layer BFL can be disposed between the active layer ACT and the base layer BSL. The buffer layer BFL can expose at least a portion of the second base BS2. In an embodiment, the buffer layer BFL can contact the active layer ACT in the display area DA. The buffer layer BFL can include an inorganic material. For example, the buffer layer BFL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0094] An end portion (e.g., a buffer end portion EP2) of the buffer layer BFL can be directly adjacent to the organic contact area COA. The buffer end portion EP2 of the buffer layer BFL can be directly adjacent to the upper organic layer UOL.

[0095] In an embodiment, the second barrier layer BR2 and the buffer layer BFL can extend farther toward an edge of the display device DD than the gate insulating layer GI and the interlayer insulating layer ILD. The barrier end portion EP1 and the buffer end portion EP2 can correspond to (e.g., overlap) each other in a plan view. For example, the second barrier layer BR2 and the buffer layer BFL can have edges that correspond to each other. For example, the second barrier layer BR2 and the buffer layer BFL can be etched using a common mask.

[0096] The second barrier layer BR2 and the buffer layer BFL can form a second stepped area STA2. For example, the second barrier layer BR2 and the buffer layer BFL can extend to a lesser extent than the second base BS2, thereby forming the second stepped area STA2.

[0097] A portion of the buffer layer BFL can be exposed by the first inorganic insulating layer IL1, and a portion of the upper surface of the buffer layer BFL exposed by the first inorganic insulating layer IL1 can contact the upper organic layer UOL.

[0098] In an embodiment, the display device DD can include an active layer ACT.

[0099] The active layer ACT can be disposed on the buffer layer BFL in the display area DA. The active layer ACT can include various semiconductor materials. For example, the active layer ACT can include, but is not limited to, at least one of polysilicon (e.g., low temperature polysilicon (LTPS)), amorphous silicon, and oxide semiconductor.

[0100] In an embodiment, the display device DD can include a gate insulating layer GI.

[0101] The gate insulating layer GI can be disposed on the buffer layer BFL throughout both the display area DA and the non-display area NDA, and it can cover the active layer ACT. The gate insulating layer GI can expose at least a portion of the buffer layer BFL. The gate insulating layer GI can include an inorganic material. For example, the buffer layer BFL can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0102] An end portion (e.g., a gate insulating end portion EP3) of the gate insulating layer GI can be spaced apart from the organic contact area COA and the second step area STA2. The gate insulating end portion EP3 of the gate insulating layer GI can be covered by the first inorganic insulating layer IL1.

[0103] In an embodiment, the display device DD can include a gate conductive layer GAT.

[0104] The gate conductive layer GAT can be disposed on the gate insulating layer GI in the display area DA, and can overlap the active layer ACT in a plan view. The gate conductive layer GAT can include various conductive materials. For example, the gate conductive layer GAT can include, but is not limited to, at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt).

[0105] In an embodiment, the display device DD can include an interlayer insulating layer ILD.

[0106] The interlayer insulating layer ILD can be disposed on the gate insulating layer GI throughout both the display area DA and the non-display area NDA, and it can cover the gate conductive layer GAT. The interlayer insulating layer ILD can expose at least a portion of the buffer layer BFL. The interlayer insulating layer ILD can include an inorganic material. For example, the interlayer insulating layer ILD can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0107] An end portion of the interlayer insulating layer ILD (e.g., the interlayer insulating end portion EP4) can be spaced apart from the organic contact area COA and the second step area STA2. The interlayer insulating end portion EP4 of the interlayer insulating layer ILD can be covered by the first inorganic insulating layer IL1. The gate insulating layer GI and the interlayer insulating layer ILD can be physically spaced apart from the organic contact area COA and the upper organic layer UOL. For example, the gate insulating end portion EP3 and the interlayer insulating end portion EP4 can be spaced apart from the upper organic layer UOL.

[0108] In an embodiment, the gate insulating end portion EP3 and the interlayer insulating end portion EP4 can correspond to (e.g., overlap) each other in a plan view. For example, the gate insulating layer GI and the interlayer insulating layer ILD can have edges corresponding to each other. For example, the gate insulating layer GI and the interlayer insulating layer ILD can be etched using a common mask.

[0109] The gate insulating layer GI and the interlayer insulating layer ILD can form the first step area STA1. For example, the gate insulating layer GI and the interlayer insulating layer ILD can extend to a smaller degree than the second barrier layer BR2 and the buffer layer BFL, thereby forming the first step area STA1.

[0110] In an embodiment, the display device DD can include the first transistor electrode TE1 and the second transistor electrode TE2 and the first cathode power supply line VSS1.

[0111] The first transistor electrode TE1 and the second transistor electrode TE2 can be disposed on the interlayer insulating layer ILD in the display area DA and electrically connected to the active layer ACT through a contact member that penetrates the interlayer insulating layer ILD and the gate insulating layer GI. The first transistor electrode TE1 and the second transistor electrode TE2 can function as a source electrode and a drain electrode or a drain electrode and a source electrode.

[0112] The first cathode power supply line VSS1 can be disposed on the interlayer insulating layer ILD in the non-display area NDA. In an embodiment, a portion of the first cathode power supply line VSS1 can be disposed in the dam area DAA and can overlap the first dam DAM1 in a plan view.

[0113] The first and second transistor electrodes TE1 and TE2 and the first cathode power supply line VSS1 can be patterned using the same process and can include the same conductive material. The first and second transistor electrodes TE1 and TE2 and the first cathode power supply line VSS1 can include various conductive materials. For example, the first and second transistor electrodes TE1 and TE2 and the first cathode power supply line VSS1 can include, but are not limited to, at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt).

[0114] The first and second transistor electrodes TE1 and TE2, the gate conductive layer GAT, and the active layer ACT can form a pixel circuit for driving the light emitting element LD. For example, the pixel circuit can include a driving transistor, a switching transistor, and the like, and can further include a capacitor.

[0115] In an embodiment, the display device DD can include a first via layer VIA1 and a (2-1)th dam DAM2-1.

[0116] The first via layer VIA1 can be disposed on the interlayer insulating layer ILD in the display area DA. The first via layer VIA1 can cover portions of the first and second transistor electrodes TE1 and TE2. The first via layer VIA1 can include an organic material.

[0117] The (2-1)th dam DAM2-1 can be disposed on the interlayer insulating layer ILD in the non-display area NDA (e.g., the dam area DAA). The (2-1)th dam DAM2-1 can cover a portion of the first cathode power supply line VSS1. The (2-1)th dam DAM2-1 can include an organic material. The (2-1)th dam DAM2-1 can form a lower portion of a second dam DAM2.

[0118] The first via layer VIA1 and the (2-1)th dam DAM2-1 can be patterned using the same process and can include the same material.

[0119] In an embodiment, the display device DD can include a bridge layer BRP and a second cathode power supply line VSS2.

[0120] The bridge layer BRP can be disposed on the first via layer VIA1 in the display area DA, and can be electrically connected to the second transistor electrode TE2 by a contact member penetrating the first via layer VIA1.

[0121] The second cathode power supply line VSS2 can be disposed on the first via layer VIA1 in the display area DA and the (2-1)th dam D AM2-1 in the non-display area NDA. The second cathode power supply line VSS2 can be electrically connected to the first cathode power supply line VSS1 by a contact member penetrating the first via layer VIA1 and the (2-1)th dam D AM2-1. In an embodiment, a portion of the second cathode power supply line VSS2 can be disposed in the dam area DAA, and can overlap the first dam DAM1 in a plan view.

[0122] The bridge layer BRP and the second cathode power supply line VSS2 can be patterned using the same process, and can include the same conductive material. The bridge layer BRP and the second cathode power supply line VSS2 can include various conductive materials. For example, the bridge layer BRP and the second cathode power supply line VSS2 can include, but are not limited to, at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt).

[0123] In an embodiment, the display device DD includes a second via layer VIA2, a (1-1)th dam DAM1-1, and a (2-2)th dam DAM2-2.

[0124] The second via layer VIA2 can be disposed on the first via layer VIA1 in the display area DA. The second via layer VIA2 can cover a portion of the bridge layer BRP, and can also cover a portion of the second cathode power supply line VSS2. The second via layer VIA2 can include an organic material.

[0125] The (1-1)th dam DAM1-1 can be disposed on the second cathode power supply line VSS2 disposed on the first cathode power supply line VSS1 in the non-display area NDA (e.g., the dam area DAA). The (1-1)th dam DAM1-1 can include an organic material. The (1-1)th dam DAM1-1 can form a lower portion of the first dam DAM1.

[0126] The (2-2)th dam DAM2-2 can be disposed on the (2-1)th dam DAM2-1 in the non-display area NDA (e.g., the dam area DAA). The (2-2)th dam DAM2-2 can cover a portion of the second cathode power supply line VSS2. The (2-2)th dam DAM2-2 can include an organic material. The (2-2)th dam DAM2-2 can form a middle lower portion of the second dam DAM2.

[0127] The second via layer VIA2, the first (1-1) dam DAM1-1, and the second (2-2) dam DAM2-2 can be patterned using the same process, and can include the same material.

[0128] In an embodiment, the display device DD can include an anode AE, a cathode connection electrode CCE, and a third cathode power supply line VSS3.

[0129] The anode AE can be disposed on the second via layer VIA2 in the display area DA. The anode AE can be electrically connected to the bridge layer BRP through a contact member that penetrates the second via layer VIA2. The anode AE can include a multi-layer structure, and can include various conductive materials. For example, the anode AE can include at least one of a transparent conductive material and a reflective conductive material. The anode AE can include, but is not limited to, a structure in which ITO / Ag / ITO are sequentially stacked.

[0130] The cathode connection electrode CCE can be disposed on the second via layer VIA2 in the display area DA. The cathode connection electrode CCE can be electrically connected to the cathode CE.

[0131] The third cathode power supply line VSS3 can be disposed on the second via layer VIA2 and the first (1-1) dam DAM1-1 in the non-display area NDA. The third cathode power supply line VSS3 can be electrically connected to the second cathode power supply line VSS2 through a contact member that penetrates the second via layer VIA2 and the first (1-1) dam DAM1-1. In an embodiment, a portion of the third cathode power supply line VSS3 can be disposed in the dam area DAA, and can overlap the first dam DAM1 in a plan view.

[0132] The first to third cathode power supply lines VSS1 to VSS3 can form a cathode power supply line VSS. Accordingly, a cathode signal (e.g., a cathode voltage) can be supplied to the cathode CE to enable the light emitting element LD to emit light.

[0133] The anode AE, the cathode connection electrode CCE, and the third cathode power supply line VSS3 can be patterned using the same process, and can include the same conductive material.

[0134] In an embodiment, the display device DD can include a pixel definition layer PDL, a first (1-2) dam DAM1-2, and a second (2-3) dam DAM2-3.

[0135] The pixel definition layer PDL can be disposed in the display area DA, and can cover the anode AE and the cathode connection electrode CCE. The pixel definition layer PDL can define an area in which the light emitting layer EL and the anode AE are electrically connected to each other.

[0136] The pixel definition layer PDL can include an inorganic material. For example, the pixel definition layer PDL can include, but is not limited to, at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). The pixel definition layer PDL can include a multi-layer structure. For example, the pixel definition layer PDL can include a multi-layer structure in which silicon oxide (SiO x ) and silicon nitride (SiN x ) are alternately stacked. In another embodiment, the pixel definition layer PDL can include an organic material.

[0137] The (1-2) dam DAM1-2 can be disposed on the (1-1) dam DAM1-1 in the non-display area NDA (e.g., dam area DAA). The (1-2) dam DAM1-2 can cover a portion of the second cathode power supply line VSS2. The (1-2) dam DAM1-2 can form a middle portion of the first dam DAM1.

[0138] The (2-3) dam DAM2-3 can be disposed on the (2-2) dam DAM2-2 in the non-display area NDA (e.g., dam area DAA). The (2-3) dam DAM2-3 can cover a portion of the second cathode power supply line VSS2. The (2-3) dam DAM2-3 can form an upper middle portion of the second dam DAM2.

[0139] The pixel definition layer PDL, the (1-2) dam DAM1-2, and the (2-3) dam DAM2-3 can be patterned using the same process and can include the same material.

[0140] In an embodiment, the display device DD can include an emission layer EL.

[0141] The emission layer EL can be disposed on the anode AE in the display area DA and can be electrically connected between the anode AE and the cathode CE. In an embodiment, the emission layer EL can emit different colors of light according to the corresponding sub-pixel SPX (e.g., refer to Figure 2 ). For example, the emission layer EL included in the first sub-pixel SPX1 (e.g., refer to Figure 2 ) can emit a first color of light, the emission layer EL included in the second sub-pixel SPX2 (e.g., refer to Figure 2 ) can emit a second color of light, and the emission layer EL included in the third sub-pixel SPX3 (e.g., refer to Figure 2 ) can emit a third color of light.

[0142] The light-emitting layer EL can be manufactured based on various process methods such as a deposition process, a coating process, or the like. The light-emitting layer EL can include multiple layers. For example, the light-emitting layer EL can include a hole transport portion, a light-emitting portion (or a light-generating portion), and an electron transport portion. Each portion forming the light-emitting layer EL can include an organic material, and in embodiments, can further include a metal-containing compound, an inorganic material such as a quantum dot, or the like.

[0143] The hole transport portion can include a multi-layer structure of multiple layers having different materials. As an example, the hole transport portion can include a hole injection layer and a hole transport layer, and in embodiments, can further include a light-emitting auxiliary layer, an electron blocking layer, and the like.

[0144] The light-emitting portion can include a material configured to emit light of one color. The light-emitting portion can include a host and a dopant. The host of the light-emitting portion can be a light-emitting material configured to trap carriers (electrons and holes) generating light, and can induce efficient generation of excitons. The dopant can include a phosphorescent dopant or a fluorescent dopant. In embodiments, examples of the dopant are not particularly limited. In embodiments, the dopant can include an organic material, a metal complex, or the like.

[0145] The electron transport portion can include a multi-layer structure of multiple layers having different materials. The electron transport portion can include an electron injection layer and an electron transport layer, and in embodiments, can further include an electron buffer layer, a hole blocking layer, and the like.

[0146] In embodiments, the display device DD can include a cathode CE.

[0147] The cathode CE can be disposed on the pixel definition layer PDL and the light-emitting layer EL in the display area DA. The cathode CE can include various conductive materials. For example, the cathode CE can include silver (Ag), and can further include an additional metal. The additional metal can include, but is not limited to, at least one of magnesium (Mg), aluminum (Al), copper (Cu), calcium (Ca), and barium (Ba). For example, the cathode CE can include a silver-magnesium (AgMg) alloy. However, the present disclosure is not limited thereto. In embodiments, the cathode CE can include various transparent conductive materials.

[0148] In embodiments, the anode AE, the light-emitting layer EL, and the cathode CE can form a light-emitting element LD.

[0149] In embodiments, the display device DD can include the first (1-3) dam DAM1-3 and the second (2-4) dam DAM2-4.

[0150] The (1-3) dam DAM1-3 can be disposed on the (1-2) dam DAM1-2 in a non-display area NDA (e.g., a dam area DAA). The (1-3) dam DAM1-3 can cover the second cathode power supply line VSS2 and the third cathode power supply line VSS3. The (1-3) dam DAM1-3 can form an upper portion of the first dam DAM1.

[0151] The (2-4) dam DAM2-4 can be disposed on the (2-3) dam DAM2-3 in a non-display area NDA (e.g., a dam area DAA). The (2-4) dam DAM2-4 can cover the interlayer insulating layer ILD and the second cathode power supply line VSS2. The (2-4) dam DAM2-4 can form an upper portion of the second dam DAM2.

[0152] The (1-3) dam DAM1-3 and the (2-4) dam DAM2-4 can be patterned using the same process and can include the same material. For example, the (1-3) dam DAM1-3 and the (2-4) dam DAM2-4 can include, but are not limited to, an organic material.

[0153] The (1-1) dam DAM1-1, the (1-2) dam DAM1-2, and the (1-3) dam DAM1-3 can form the first dam DAM1. The first dam DAM1 can be an inner dam closer to the display area DA than the second dam DAM2. The (2-1) dam DAM2-1, the (2-2) dam DAM2-2, the (2-3) dam DAM2-3, and the (2-4) dam DAM2-4 can form the second dam DAM2. The second dam DAM2 can be positioned farther from the display area DA than the first dam DAM1, serving as an outer dam.

[0154] In an embodiment, the display device DD can include a passivation layer TFE. The passivation layer TFE can include a first inorganic insulating layer IL1, an organic passivation layer OL, and a second inorganic insulating layer IL2.

[0155] The first inorganic insulating layer IL1 can be disposed throughout the display area DA and the non-display area NDA, and can cover (e.g., passivate) the cathode CE, the third cathode power supply line VSS3, the first dam DAM1, the second dam DAM2, the interlayer insulating layer ILD, the interlayer insulating end portion EP4, the gate insulating end portion EP3, and the buffer layer BFL. The first inorganic insulating layer IL1 can include an inorganic material. For example, the first inorganic insulating layer IL1 can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0156] The first inorganic insulating layer IL1 can expose at least a portion of the upper surface of the buffer layer BFL. The first inorganic insulating layer IL1 can expose the blocking end portion EP1 and the buffer end portion EP2. The first inorganic insulating layer IL1 can not expose the interlayer insulating end portion EP4 and the gate insulating end portion EP3.

[0157] The first inorganic insulating layer IL1 can extend farther than the gate insulating layer GI and the interlayer insulating layer ILD, but not as far as the buffer layer BFL and the second blocking layer BR2. Accordingly, an end portion (e.g., a first inorganic insulating end portion EP5) of the first inorganic insulating layer IL1 can be disposed between the first step area STA1 and the second step area STA2.

[0158] The organic encapsulation layer OL can be disposed on the first inorganic insulating layer IL1 in the dam area DAA. The organic encapsulation layer OL can be disposed in an area surrounded by the first dam DAM1 and the second dam DAM2. Accordingly, in the case where the organic encapsulation layer OL is provided in the display area DA, the first dam DAM1 and the second dam DAM2 can reduce the risk of diffusion of the organic encapsulation layer OL.

[0159] The second inorganic insulating layer IL2 can be disposed throughout the display area DA and the non-display area NDA, and can cover (e.g., passivate) the organic encapsulation layer OL and the first inorganic insulating layer IL1. The second inorganic insulating layer IL2 can include an inorganic material. For example, the second inorganic insulating layer IL2 can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0160] The second inorganic insulating layer IL2 can expose at least a portion of the upper surface of the first inorganic insulating layer IL1. The second inorganic insulating layer IL2 can expose the first inorganic insulating end portion EP5 of the first inorganic insulating layer IL1.

[0161] The second inorganic insulating layer IL2 can include a second inorganic insulating end portion EP6. The second inorganic insulating layer IL2 can extend farther than the gate insulating layer GI and the interlayer insulating layer ILD, but not as far as the first inorganic insulating layer IL1, the buffer layer BFL, and the second blocking layer BR2.

[0162] In an embodiment, the display device DD can include a first upper insulating layer YIL1, a first conductive pattern layer CP1, a second upper insulating layer YIL2, a second conductive pattern layer CP2, and an organic protection layer PVX.

[0163] The first upper insulating layer YIL1, the first conductive pattern layer CP1, the second upper insulating layer YIL2, the second conductive pattern layer CP2, and the organic protective layer PVX can form a sensor layer TSP (e.g., refer to Figure 1 ). For example, the first conductive pattern layer CP1 and the second conductive pattern layer CP2 can form a sensing electrode SP (e.g., refer to Figure 1 ). In an embodiment, at least part of the first conductive pattern layer CP1 and the second conductive pattern layer CP2 can form a first sensing electrode SP1 (e.g., refer to Figure 1 ), and at least part of the first conductive pattern layer CP1 and the second conductive pattern layer CP2 can form a second sensing electrode SP2 (e.g., refer to Figure 1 ).

[0164] The first upper insulating layer YIL1 can be disposed on the second inorganic insulating layer IL2 over the display area DA and the non-display area NDA. The first upper insulating layer YIL1 can include an inorganic material. For example, the first upper insulating layer YIL1 can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O y ).

[0165] The first upper insulating layer YIL1 can form a sensor base layer SBSL. The first upper insulating layer YIL1 can form a base on which other layers forming the sensor layer TSP are disposed.

[0166] The first upper insulating layer YIL1 can expose at least part of an upper surface of the first inorganic insulating layer IL1. The first upper insulating layer YIL1 can expose the first inorganic insulating end portion EP5 of the first inorganic insulating layer IL1.

[0167] The first upper insulating layer YIL1 can include a first upper insulating end portion EP7.

[0168] The second upper insulating layer YIL2 can be disposed on the first upper insulating layer YIL1 over the display area DA and the non-display area NDA, and can cover the first conductive pattern layer CP1. The second upper insulating layer YIL2 can include an inorganic material. For example, the second upper insulating layer YIL2 can include, but is not limited to, at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (Al x O yIn another embodiment, the second upper insulating layer YIL2 can include an organic material.

[0169] The second upper insulating layer YIL2 can separate the first conductive pattern layer CP1 and the second conductive pattern layer CP2.

[0170] The second upper insulating layer YIL2 can expose at least a portion of an upper surface of the first inorganic insulating layer IL1. The second upper insulating layer YIL2 can expose the first inorganic insulating end portion EP5 of the first inorganic insulating layer IL1.

[0171] The second upper insulating layer YIL2 can include a second upper insulating end portion EP8.

[0172] In an embodiment, the second inorganic insulating end portion EP6, the first upper insulating end portion EP7, and the second upper insulating end portion EP8 can have edges corresponding to (e.g., overlapping) each other. For example, the second inorganic insulating layer IL2, the first upper insulating layer YIL1, and the second upper insulating layer YIL2 can be etched using a common mask.

[0173] The first conductive pattern layer CP1 can be disposed on the first upper insulating layer YIL1. The second conductive pattern layer CP2 can be disposed on the second upper insulating layer YIL2. The first conductive pattern layer CP1 and the second conductive pattern layer CP2 can be disposed on different layers. The first conductive pattern layer CP1 and the second conductive pattern layer CP2 can partially overlap each other in a plan view. In an embodiment, the first conductive pattern layer CP1 and the second conductive pattern layer CP2 can overlap the pixel defining layer PDL in a plan view.

[0174] The first conductive pattern layer CP1 and the second conductive pattern layer CP2 can include a single or multiple metal layers. The first conductive pattern layer CP1 and the second conductive pattern layer CP2 can include at least one of various metal materials such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt), or an alloy thereof, but are not limited thereto. In an embodiment, the first conductive pattern layer CP1 and the second conductive pattern layer CP2 can include at least one of various transparent conductive materials such as silver nanowires (AgNW), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), tin oxide (SnO2), carbon nanotubes, or graphene, but are not limited thereto.

[0175] The organic protective layer PVX can be disposed throughout the display area DA and the non-display area NDA. The organic protective layer PVX can cover the second conductive pattern layer CP2, the second upper insulating layer YIL2, the first inorganic insulating layer IL1, the buffer layer BFL, and the second base BS2. The organic protective layer PVX can include an organic material. For example, the organic protective layer PVX can include, but is not limited to, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0176] The organic protective layer PVX can cover the barrier end portion EP1, the buffer end portion EP2, the first inorganic insulating end portion EP5, the second inorganic insulating end portion EP6, the first upper insulating end portion EP7, and the second upper insulating end portion EP8. The organic protective layer PVX can be spaced apart from the gate insulating end portion EP3 and the interlayer insulating end portion EP4.

[0177] The organic protective layer PVX can be directly adjacent to the second stepped area STA2. The organic protective layer PVX can be spaced apart from the first stepped area STA1.

[0178] In an embodiment, the display device DD can include a polarizing layer POL.

[0179] The polarizing layer POL can be disposed throughout the display area DA and the non-display area NDA, and can cover the organic protective layer PVX. As described above, the polarizing layer POL can include various materials having a polarizing property.

[0180] The polarizing layer POL, the organic protective layer PVX, the first base BS1, the first barrier layer BR1, and the second base BS2 can include end portions overlapping each other. For example, as the mother substrate MS (see Figure 7 ) is cut, the plurality of display devices DD can be separated from each other, and can define the end portions of the polarizing layer POL, the organic protective layer PVX, the first base BS1, the first barrier layer BR1, and the second base BS2.

[0181] In an embodiment, the organic protective layer PVX can be an upper organic layer UOL in which the organic contact area COA is formed.

[0182] For example, the organic protective layer PVX can contact the second base BS2 in the organic contact area COA. For example, the organic protective layer PVX can be formed after the second base BS2 is exposed, and a portion of the organic protective layer PVX can be directly adjacent to the second base BS2 through a portion of the exposed second base BS2.

[0183] As described above, since the organic protective layer PVX and the second base BS2 can include an organic material, the organic layer can be continuously disposed through the organic contact area COA.

[0184] The organic contact area COA can be formed adjacent to an edge of the display device DD. The organic contact area COA can be more spaced apart from the display area DA than other layers disposed between the organic protective layer PVX and the second substrate BS2. The organic contact area COA can be directly adjacent to an edge of the display device DD.

[0185] In an embodiment, when the organic contact area COA is formed, the risk of impurities such as moisture or oxygen penetrating into the display device DD can be reduced. For example, a structure that blocks impurities such as moisture can be formed by continuously disposing an organic layer on the outside of the display device DD. Accordingly, a problem affecting the reliability of the display device DD due to impurities or similar factors can be reconsidered.

[0186] In an embodiment, when the organic contact area COA is formed, the risk of delamination of the inorganic layer formed on the base layer BSL can be reduced. For example, when the organic contact area COA is formed outside the various inorganic layers on the base layer BSL, the upper organic layer UOL can cover the end of the inorganic layer and the upper surface of the inorganic layer. Even if stress is generated in the display device DD during a manufacturing process of the display device DD, the upper organic layer UOL can reduce the risk of delamination of the inorganic layer.

[0187] For example, layers for manufacturing the display device DD can be formed on the mother substrate MS, and a polarizing layer POL can be formed. Thereafter, the display device DD can be manufactured by performing a cutting process on the mother substrate MS. Experimentally, in the case of cutting the polarizing layer POL, a portion of the polarizing layer POL shrinks, causing stress from the non-display area NDA to the display area DA. The resulting stress can act on various components of the display device DD, and can induce delamination of the inorganic layer on the base layer BSL. However, according to the embodiment, since the organic contact area COA is formed, the upper organic layer UOL can sufficiently cover the inorganic layer, and the risk of the above-described delamination can be reduced.

[0188] In an embodiment, the formation of the organic contact area COA can reduce the risk of delamination of the inorganic layer, such that a cutting area on the mother substrate MS is expanded. This expansion improves process convenience, and reduces the risk of process deviation by securing a greater process margin for the cutting process.

[0189] In an embodiment, an etching process can be performed on the insulating layer to define the organic contact area COA. This etching process can be combined with an etching process for other layers on the base layer BSL, thereby reducing mask consumption.

[0190] A display device DD according to a second embodiment will be described with reference to Figure 5 A display device DD according to a second embodiment will be described with reference to

[0191] Figure 5 The display device DD according to the second embodiment shown in FIG. 7 can be different from the display device DD according to the embodiment described with reference to Figure 4 The display device DD of the embodiment described with reference to

[0192] In an embodiment, the display device DD can further include an additional organic protective layer AOL disposed on the organic protective layer PVX serving as the upper organic layer UOL.

[0193] The additional organic protective layer AOL can be disposed on the organic protective layer PVX throughout the display area DA and the non-display area NDA. The additional organic protective layer AOL can include an organic material. For example, the additional organic protective layer AOL can include, but is not limited to, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0194] End portions of the additional organic protective layer AOL can overlap the polarizing layer POL, the organic protective layer PVX, the first substrate BS1, the first barrier layer BR1, and the second substrate BS2. For example, as the mother substrate MS is cut, a plurality of display devices DD can be separated from each other. This process defines the end portions of the additional organic protective layer AOL, the polarizing layer POL, the organic protective layer PVX, the first substrate BS1, the first barrier layer BR1, and the second substrate BS2.

[0195] A display device DD according to a third embodiment will be described with reference to Figure 6 A display device DD according to a third embodiment will be described with reference to

[0196] Figure 6 The display device DD according to the third embodiment shown in FIG. 9 can be different from the display device DD according to the embodiment described with reference to Figure 5 The display device DD of the embodiment described with reference to

[0197] In an embodiment, the additional organic protective layer AOL can contact at least a portion of an upper surface of the second substrate BS2 exposed by the second barrier layer BR2 and the buffer layer BFL in the organic contact area COA. The additional organic protective layer AOL and the second substrate BS2 can form a structure in which an organic layer is continuously formed through the organic contact area COA. In an embodiment, since the organic contact area COA is formed, a risk of permeation of impurities such as moisture and a risk of delamination of an inorganic layer can be reduced.

[0198] In an embodiment, reference is made to Figure 6The organic protective layer PVX can have an end portion in the dam region DAA. For example, the organic protective layer PVX can not extend to the organic contact region COA. The organic protective layer PVX can extend shorter than the gate insulating layer GI and the interlayer insulating layer ILD to the outside of the display device DD.

[0199] A method of manufacturing a display device DD according to an embodiment will be described with reference to Figures 7 to 26 A method of manufacturing a display device DD according to an embodiment will be described with reference to

[0200] First, a method of manufacturing a display device DD according to a first embodiment will be described with reference to Figures 7 to 19 A method of manufacturing a display device DD according to an embodiment will be described with reference to Figure 4 A method of manufacturing a display device DD according to an embodiment will be described with reference to

[0201] Figure 7 is a plan view showing a structure in which a mother substrate includes a plurality of unit bodies, to explain a method of manufacturing a display device according to an embodiment. Figures 8 to 19 is a cross-sectional view schematically showing each process step of a method of manufacturing a display device according to an embodiment.

[0202] Referring to Figure 7 , a display device DD can be manufactured by using a mother substrate MS including a plurality of unit bodies UCE. A cutting process can be performed outside the dam region DAA of the mother substrate MS to separate the plurality of unit bodies UCE, so that a display device DD according to an embodiment is provided. Each of the plurality of unit bodies UCE separated by the cutting process can correspond to a display device DD according to an embodiment. For example, after a plurality of layers for manufacturing a display device DD are sequentially arranged on the mother substrate MS, the cutting process can be performed to provide the display device DD separately separated.

[0203] Hereinafter, referring to Figures 8 to 19 , a method of manufacturing a display device DD will be described based on a unit body UCE and a region adjacent thereto. Figures 8 to 19 schematically depicts a cross-sectional structure taken along a line B-B' in Figure 7 . The process steps shown in Figures 8 to 19 may be understood to be applied to the entire mother substrate MS. For the convenience of description, Figures 8 to 19 regions for forming a display device DD are schematically depicted in

[0204] Referring to Figure 8 , a base layer BSL can be provided. A buffer layer BFL, an active layer ACT, a gate insulating layer GI, a gate conductive layer GAT, and an interlayer insulating layer ILD can be sequentially arranged on the base layer BSL.

[0205] In an embodiment, the conductive layer or the insulating layer on the base layer BSL can be formed based on a general process for manufacturing a semiconductor device. For example, the conductive layer or the insulating layer on the base layer BSL can be formed by, but not limited to, using a photolithography process, etching by various methods such as a wet etching, a dry etching, or the like, and depositing by various methods such as sputtering, chemical vapor deposition, or the like.

[0206] In this step, to provide the base layer BSL, a structure in which the first substrate BS1, the first barrier layer BR1, the second substrate BS2, and the second barrier layer BR2 are sequentially disposed can be formed.

[0207] In this step, the second substrate BS2 can be covered by the second barrier layer BR2, and an upper surface of the second substrate BS2 can not be exposed.

[0208] Referring to Figure 9 At least a portion of the gate insulating layer GI and the interlayer insulating layer ILD can be removed.

[0209] In this step, an etching process can be performed on the gate insulating layer GI and the interlayer insulating layer ILD using the first etching mask. For example, using the first etching mask, a first exposure area EA1 exposing a portion of the buffer layer BFL can be formed, and a contact portion PCNT exposing the active layer ACT can be formed. For example, the etching process exposing the buffer layer BFL and the etching process exposing the active layer ACT can be performed using the same process.

[0210] In this step, a gate insulating end portion EP3 and an interlayer insulating end portion EP4 adjacent to the first exposure area EA1 can be formed, and a first step area STA1 can be defined.

[0211] Referring to Figure 10 At least a portion of the second barrier layer BR2 and the buffer layer BFL can be removed.

[0212] In this step, an etching process can be performed on the second barrier layer BR2 and the buffer layer BFL using the second etching mask. For example, using the second etching mask, a second exposure area EA2 exposing a portion of the second substrate BS2 can be formed. The process of exposing the second substrate BS2 can be performed after the etching process on the gate insulating layer GI and the interlayer insulating layer ILD.

[0213] In this step, a barrier end portion EP1 and a buffer end portion EP2 adjacent to the second exposure area EA2 can be formed, and a second step area STA2 can be defined.

[0214] Referring to Figure 11The first transistor electrode TE1 and the second transistor electrode TE2, the first cathode power supply line VSS1, the first via layer VIA1, the (2-1)th dam D AM2-1, the bridging layer BRP, the second cathode power supply line VSS2, the second via layer VIA2, the (1-1)th dam D AM1-1, and the (2-2)th dam D AM2-2 can be patterned (e.g., sequentially patterned).

[0215] In this step, the second substrate BS2 can be kept in the exposed state in the second exposed area EA2.

[0216] Referring to Figure 12 The anode AE, the cathode connection electrode CCE, the third cathode power supply line VSS3, the pixel definition layer PDL, the (1-2)th dam D AM1-2, the (2-3)th dam D AM2-3, the light emitting layer EL, the cathode CE, the (1-3)th dam D AM1-3, and the (2-4)th dam D AM2-4 can be patterned (e.g., sequentially patterned).

[0217] In this step, the second substrate BS2 can be kept in the exposed state in the second exposed area EA2, and the first dam D AM1 and the second dam D AM2 and the light emitting element LD can be provided.

[0218] Referring to Figure 13 The first inorganic insulating layer IL1, the organic encapsulation layer OL, and the second inorganic insulating layer IL2 can be arranged (e.g., sequentially arranged), and the encapsulation layer TFE can be formed.

[0219] In this step, the first inorganic insulating layer IL1 can be formed to cover the barrier end portion EP1, the buffer end portion EP2, the gate insulating end portion EP3, and the interlayer insulating end portion EP4. The first inorganic insulating layer IL1 can cover the second exposed area EA2, and can contact the second substrate BS2. Herein, the second exposed area EA2 can correspond to the organic contact area COA, and thus, in some drawings (e.g., Figure 13 and the like), the second exposed area EA2 is indicated with the organic contact area COA.

[0220] In this step, the organic encapsulation layer OL can cover the light emitting element LD, and can be formed inside the dam area DAA.

[0221] In this step, the second inorganic insulating layer IL2 can cover the organic encapsulation layer OL and the upper surface of the first inorganic insulating layer IL1 which is not covered by the organic encapsulation layer OL.

[0222] Referring to Figure 14 The first upper insulating layer YIL1, the first conductive pattern layer CP1, the second upper insulating layer YIL2, and the second conductive pattern layer CP2 can be patterned (e.g., sequentially patterned).

[0223] In this step, the first upper insulating layer YIL1 can cover the second inorganic insulating layer IL2. The second upper insulating layer YIL2 can cover the first conductive pattern layer CP1 and the first upper insulating layer YIL1. The first conductive pattern layer CP1 and the second conductive pattern layer CP2 are patterned to form a sensing electrode SP (for example, refer to FIG. 1B). Figure 1 ).

[0224] Referring to Figure 15 , at least a portion of the second inorganic insulating layer IL2, the first upper insulating layer YIL1, and the second upper insulating layer YIL2 can be removed.

[0225] In this step, an etching process can be performed on the second inorganic insulating layer IL2, the first upper insulating layer YIL1, and the second upper insulating layer YIL2 using a third etching mask.

[0226] In this step, a second inorganic insulating end portion EP6, a first upper insulating end portion EP7, and a second upper insulating end portion EP8 can be formed between the first step region STA1 and the second step region STA2.

[0227] In this step, the first inorganic insulating layer IL1 can not be removed. Thus, a portion of the second substrate BS2 can still contact the first inorganic insulating layer IL1.

[0228] Referring to Figure 16 , at least a portion of the first inorganic insulating layer IL1 can be removed.

[0229] In this step, an etching process can be performed on the first inorganic insulating layer IL1 using a fourth etching mask.

[0230] In this step, a first inorganic insulating end portion EP5 can be formed between the first step region STA1 and the second step region STA2.

[0231] In this step, a portion of the first inorganic insulating layer IL1 that contacts the second substrate BS2 can be removed, the blocking end portion EP1 and the buffer end portion EP2 can be exposed, and at least a portion of the second substrate BS2 can be exposed.

[0232] Referring to Figure 17 , an organic protective layer PVX that serves as an upper organic layer UOL can be formed.

[0233] In this step, the organic protective layer PVX can cover the blocking end portion EP1, the buffer end portion EP2, the first inorganic insulating end portion EP5, the second inorganic insulating end portion EP6, the first upper insulating end portion EP7, and the second upper insulating end portion EP8.

[0234] In this step, the organic protective layer PVX can contact the exposed upper surface of the second substrate BS2 and can define an organic contact area COA.

[0235] Referring to Figure 18 , the polarizing layer POL can be formed.

[0236] In this step, the polarizing layer POL can cover the organic protective layer PVX serving as the upper organic layer UOL. Referring to Figure 7 , in this step, the polarizing layer POL can be arranged throughout the plurality of unit bodies UCE and formed across the entire mother substrate MS.

[0237] Referring to Figure 19 , a cutting process can be performed to separate the plurality of unit bodies UCE. The cutting process can be applied outside the dam area DAA in each of the unit bodies UCE.

[0238] The cutting process performed in this step can include a laser application process. In an embodiment, the cutting process can be referred to as a laser process or a scribe process. For the convenience of description, in the present specification, a cutting line to which the cutting process is applied is indicated as a single-dot chain line.

[0239] In this step, a cutting line at which the cutting process is performed can be defined in the organic contact area COA. As described above, defining the cutting line in a structure having an organic layer formed continuously can reduce the risk of penetration of impurities such as moisture and the risk of delamination of an inorganic layer. For example, in this step, stress can be generated in the polarizing layer POL in a direction from the non-display area NDA toward the display area DA. However, the formation of the organic contact area COA can reduce the risk of delamination of the inorganic layer.

[0240] As this step is performed, the plurality of unit bodies UCE can be separated from each other and a display device DD according to an embodiment can be provided.

[0241] Referring to Figures 20 to 22 , a method of manufacturing a display device according to a second embodiment will be described in conjunction with Figure 7 . The method of manufacturing a display device according to the second embodiment will be described in conjunction with Figure 5 . The method of manufacturing a display device according to the second embodiment will be described in conjunction with

[0242] Figures 20 to 22 is a cross-sectional view schematically showing each process step of a method of manufacturing a display device according to an embodiment. Figures 20 to 22 shows a schematic cross-sectional structure taken along a line B-B' in Figures 8 to 19 . Figure 7

[0243] In the method of manufacturing a display device DD according to an embodiment, the above-described​Figures 8 to 17 The described process steps.

[0244] Reference Figure 20 After the organic protective layer PVX is formed, an additional organic protective layer AOL can be formed.

[0245] In this step, the additional organic protective layer AOL can be arranged to cover the upper surface of the organic protective layer PVX. In a plan view, the additional organic protective layer AOL can overlap with the organic contact area COA.

[0246] Reference Figure 21 A polarization layer POL can be formed on the additional organic protective layer AOL.

[0247] In this step, the polarizing layer POL completely covers the upper surface of the additional organic protective layer AOL. (See reference...) Figure 7 The polarizing layer POL and the additional organic protective layer AOL can be in contact with each other throughout the mother substrate MS.

[0248] Reference Figure 22 It can perform a cutting process to separate multiple unit cells (UCEs).

[0249] In this step, a cutting process can be performed corresponding to the organic contact area COA. In an embodiment, an additional organic protective layer AOL can be further cut. Therefore, multiple display devices DD separated from the mother substrate MS can be provided.

[0250] Reference Figures 23 to 26 Together Figure 7 Description of manufacturing reference Figure 6 The method of the display device DD according to the third embodiment is described. Content overlapping with the above will be briefly described or omitted.

[0251] Figures 23 to 26 This is a cross-sectional view schematically illustrating each process step of the method for manufacturing a display device according to an embodiment. Figures 23 to 26 The above description shows Figures 8 to 19 Similar, along Figure 7 The schematic cross-sectional structure taken by line B-B' in the diagram.

[0252] In the method for manufacturing the display device DD according to the embodiment, the above-mentioned references can be performed in the same manner. Figures 8 to 16 The described process steps.

[0253] Reference Figure 23 After exposing a portion of the second substrate BS2, the organic protective layer PVX can be patterned in some areas to avoid contact with the second substrate BS2.

[0254] In this step, the organic protective layer PVX can not be used as the upper organic layer UOL, and can be partially disposed in some regions including the display area DA to be spaced apart from the organic contact area COA.

[0255] In this step, the second substrate BS2 can still be exposed, and the barrier end portion EP1, the buffer end portion EP2, the first inorganic insulation end portion EP5, the second inorganic insulation end portion EP6, the first upper insulation end portion EP7, and the second upper insulation end portion EP8 can also still be exposed.

[0256] Referring to Figure 24 After the organic protective layer PVX is formed, an additional organic protective layer AOL can be formed.

[0257] In an embodiment, the additional organic protective layer AOL can be used as the upper organic layer UOL. For example, in this step, the additional organic protective layer AOL can contact the second substrate BS2 in the organic contact area COA.

[0258] In this step, the additional organic protective layer AOL can cover the barrier end portion EP1, the buffer end portion EP2, the first inorganic insulation end portion EP5, the second inorganic insulation end portion EP6, the first upper insulation end portion EP7, and the second upper insulation end portion EP8.

[0259] Referring to Figure 25 A polarizing layer POL can be formed on the additional organic protective layer AOL.

[0260] In this step, the polarizing layer POL can completely cover the upper surface of the additional organic protective layer AOL. Referring to Figure 7 The polarizing layer POL and the additional organic protective layer AOL can contact each other in the entire mother substrate MS.

[0261] Referring to Figure 26 A cutting process can be performed to separate a plurality of unit bodies UCE.

[0262] In this step, the cutting process can be performed in correspondence with the organic contact area COA. Unlike the process according to the above-described embodiment, the cutting process can not be applied to the organic protective layer PVX, and the cutting process can be applied to layers including the additional organic protective layer AOL. Accordingly, a plurality of display devices DD separated from the mother substrate MS can be provided.

[0263] According to embodiments of the disclosure, a display device having robust characteristics against an external environment and a method of manufacturing a display device can be provided.

[0264] According to embodiments of the disclosure, a display device in which the risk of moisture penetration and stress can be reduced and a method of manufacturing a display device can be provided.

[0265] According to embodiments of the present disclosure, a display device in which the risk of delamination of an inorganic layer can be reduced and a method of manufacturing a display device can be provided.

[0266] Embodiments have been disclosed herein and, although the terms are employed in the description, they are used in a generic and descriptive sense only and not for purposes of limitation, notwithstanding any common meaning taken from patent terminology. In some instances, features, attributes and / or benefits of embodiments described in connection with a particular embodiment can be used in connection with other embodiments, unless expressly contradicted by or inconsistent with such use, as will be readily recognized by those of ordinary skill in the art. Thus, it should be understood that various changes in form and detail can be made to the embodiments without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A display device comprising a display region and a non-display region, characterized by, The display device includes: a base layer including: a first substrate, a first barrier layer on the first substrate, a second substrate on the first barrier layer, and a second barrier layer on the second substrate; a light-emitting element arranged on the base layer in the display region; and an upper organic layer arranged throughout the display region and the non-display region, wherein each of the first substrate and the second substrate is composed of an organic material, each of the first barrier layer and the second barrier layer is composed of an inorganic material, the non-display region includes an organic contact region, and the second barrier layer exposes the second substrate in the organic contact region, and the upper organic layer and the second substrate are in contact with each other in the organic contact region.

2. The display device according to claim 1, wherein The display device further includes: a buffer layer arranged on the second barrier layer and extending throughout the display region and the non-display region; an active layer arranged on the buffer layer in the display region; a gate insulating layer arranged on the buffer layer, extending throughout the display region and the non-display region, and covering the active layer; a gate conductive layer including at least a portion arranged on the gate insulating layer in the display region; an interlayer insulating layer arranged on the gate insulating layer, extending throughout the display region and the non-display region, and covering the gate conductive layer; and a first inorganic insulating layer extending throughout the display region and the non-display region and covering the light-emitting element, wherein the second barrier layer includes a barrier end portion in the non-display region, the buffer layer includes a buffer end portion in the non-display region, the gate insulating layer includes a gate insulating end portion in the non-display region, the interlayer insulating layer includes an interlayer insulating end portion in the non-display region, and the first inorganic insulating layer includes a first inorganic insulating end portion in the non-display region.

3. The display device according to claim 2, wherein the buffer layer and the active layer are in contact with each other, and the buffer layer exposes the second substrate in the non-display region and does not expose the second substrate in the display region.

4. The display device according to claim 2, wherein the first inorganic insulating end portion is arranged between the buffer end portion and the interlayer insulating end portion, the first inorganic insulating layer covers a portion of an upper surface of the buffer layer and exposes another portion of the upper surface of the buffer layer in a portion of the non-display region, and the upper organic layer and the buffer layer are in contact with each other at the other portion of the upper surface of the buffer layer exposed by the first inorganic insulating layer.

5. The display device according to claim 2, wherein The barrier end portion and the buffer end portion are directly adjacent to the organic contact region.

6. The display device according to claim 5, wherein The barrier end portion and the buffer end portion overlap each other in a plan view.

7. The display device according to claim 2, wherein The gate insulating end portion and the interlayer insulating end portion are covered by the first inorganic insulating layer.

8. The display device according to claim 7, wherein The gate insulating end portion and the interlayer insulating end portion overlap each other in a plan view.

9. The display device according to claim 2, wherein The display device further includes: a dam disposed in a dam region formed in the non-display region; an organic encapsulation layer including at least a portion disposed on the first inorganic insulating layer in a region surrounded by the dam; a second inorganic insulating layer covering the organic encapsulation layer and disposed on the first inorganic insulating layer; a first upper insulating layer disposed on the second inorganic insulating layer; a first conductive pattern layer disposed on the first upper insulating layer; a second upper insulating layer covering the first conductive pattern layer and disposed on the first upper insulating layer; and a second conductive pattern layer disposed on the second upper insulating layer, wherein the second inorganic insulating layer includes a second inorganic insulating end portion in the non-display region, the first upper insulating layer includes a first upper insulating end portion in the non-display region, and the second upper insulating layer includes a second upper insulating end portion in the non-display region.

10. The display device according to claim 9, wherein the organic contact region is formed outside the dam region, and the first conductive pattern layer and the second conductive pattern layer form a sensing electrode that obtains information related to a touch input of a user.

11. The display device according to claim 9, wherein The second inorganic insulating end portion, the first upper insulating end portion, and the second upper insulating end portion overlap each other in a plan view.

12. The display device according to claim 9, wherein The upper organic layer covers the second conductive pattern layer, the barrier end portion, the buffer end portion, the first inorganic insulating end portion, the second inorganic insulating end portion, the first upper insulating end portion, and the second upper insulating end portion, and is spaced apart from the gate insulating end portion and the interlayer insulating end portion.

13. The display device of claim 1, wherein, The display device further includes: a polarizing layer disposed on the upper organic layer, wherein the polarizing layer, the upper organic layer, the first base, the first barrier layer, and the second base have end portions that overlap each other.

14. The display device of claim 9, wherein, The display device further includes: an organic protection layer disposed on the second conductive pattern layer and spaced apart from the organic contact region; and a polarizing layer disposed on the upper organic layer, wherein the upper organic layer covers the organic protection layer.

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