Storage device and test system thereof

Abstract

The utility model discloses a storage device and a test system thereof, the storage device comprises a storage unit and a plurality of calibration compensation circuits, the storage unit comprises a plurality of storage chips, each storage chip is internally provided with a calibration network, and the calibration compensation circuits are connected with the corresponding storage chips one by one to activate the calibration networks for calibration matching. Through the structure, the stability of the output signal of the storage chip can be improved, the situation that the product function is incomplete or problems occur due to calibration mismatch of the storage chip is reduced, and the stability and reliability of the storage device are improved.

Description

TECHNICAL FIELD

[0001] The application applies to the technical field of signal calibration of storage products, in particular to a storage device and a test system thereof. BACKGROUND

[0002] Storage chip products are widely used in intelligent electronic products due to low power consumption and small size. For storage products, the main function is to store data.

[0003] Generally, the storage products are wafer cut into grains, that is, storage chips, and then packaged and tested to be qualified products.

[0004] However, due to uneven grain resources or resource defect problems caused by the factory itself, when the packaged products using problem grains are applied to mainstream platforms, calibration mismatch occurs, resulting in incomplete product functions or problems. CONTENT OF THE INVENTION

[0005] The application provides a storage device and a test system thereof to solve the problem of calibration mismatch of storage chips.

[0006] To solve the above technical problems, the application provides a storage device, comprising: a storage unit and a plurality of calibration compensation circuits, the storage unit comprising a plurality of storage chips, each storage chip being provided with a calibration network, and the calibration compensation circuits being connected one by one with the corresponding storage chips to activate the calibration network for calibration matching.

[0007] Among them, the calibration compensation circuit comprises a calibration resistor; one end of the calibration resistor is connected to the corresponding storage chip, and the other end of the calibration resistor is connected to the power supply or the ground.

[0008] Among them, the storage chip is provided with a plurality of pads, the plurality of pads comprising internal signal pads, function pads and external signal pads; one end of the calibration resistor is connected to the internal signal pad of the corresponding storage chip.

[0009] Among them, the storage unit comprises a circuit board, a plurality of storage chips and a plastic sealing layer; the plurality of storage chips and the calibration compensation circuits are fixed on the first side of the circuit board, the plastic sealing layer plastic seals the first side of the circuit board, and wraps each storage chip and the calibration compensation circuit for plastic sealing; wherein the internal signal pads, the function pads and the external signal pads of the storage chip are further connected one by one with the corresponding pads on the first side of the circuit board.

[0010] Among them, the storage unit further comprises a plurality of connecting pieces, the connecting pieces are arranged in the plastic sealing layer, one end of each connecting piece is connected to the pad of the storage chip, and the other end of the connecting piece is connected to the corresponding pad on the first side of the circuit board; wherein the connecting piece comprises one or more of a connecting line, a plated connecting piece or a punched connecting piece.

[0011] The circuit board is provided with a connecting mechanism, and a plurality of tin balls are fixedly arranged on the second side of the circuit board.

[0012] The calibration compensation circuit comprises a wire bonding pad, a first wire, a first resistance pad, a calibration resistance, a second resistance pad and a second wire connected in sequence. The wire bonding pad is further connected to an internal signal pad on the corresponding storage chip, and the second wire is grounded or connected to a power supply. The calibration resistance is welded on the first side of the circuit board through the first resistance pad and the second resistance pad.

[0013] The plurality of storage chips are arranged on the first side of the circuit board in a vertical stacking, side-by-side arrangement and / or stepped stacking manner. The plurality of storage chips are arranged on the first side of the circuit board in a vertical stacking, side-by-side arrangement and / or stepped stacking manner.

[0014] The calibration network comprises a control circuit and a calibration adjustment circuit. The calibration adjustment circuit is connected to the control circuit and the calibration compensation circuit. The control circuit is further connected to the calibration compensation circuit to match the impedance of the calibration adjustment circuit based on the impedance of the calibration compensation circuit.

[0015] To solve the above technical problems, the application also provides a test system for a storage device, comprising a storage device, a test board and a tester connected in sequence. The test board is provided with other calibration compensation circuits. The other calibration compensation circuits are connected to the other storage chips in the storage device that are not connected to the calibration compensation circuit to activate the calibration network of the other storage chips for calibration matching.

[0016] The storage device of the application comprises a storage unit and a plurality of calibration compensation circuits. The storage unit comprises a plurality of storage chips. Each storage chip is provided with a calibration network. The calibration compensation circuit is connected to the storage chip one by one to activate the calibration network for calibration matching. The storage chip adjusts its impedance through the calibration network to match the calibration compensation circuit. After matching, it is beneficial to improve the stability of the output signal of the storage chip, reduce the calibration mismatch of the storage chip, and improve the stability and reliability of the storage device. The above calibration can solve the calibration mismatch problem at the die packaging stage, ensure normal calibration of the storage device, and be suitable for various mainstream platforms. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a structural schematic diagram of the first embodiment of the storage device provided by the application.

[0018] Figure 2 is a structural schematic diagram of an embodiment of a calibration network;

[0019] Figure 3 is a structural block schematic diagram of a first embodiment of a storage device provided by the present application;

[0020] Figure 4 is a cross-sectional schematic diagram of the first embodiment of the storage device provided by the present application;

[0021] Figure 5 is an amplification structural schematic diagram of a calibration compensation circuit;

[0022] Figure 6 is a cross-sectional schematic diagram of a second embodiment of a storage device provided by the present application;

[0023] Figure 7 is a cross-sectional schematic diagram of a third embodiment of a storage device provided by the present application;

[0024] Figure 8 is a cross-sectional schematic diagram of a fourth embodiment of a storage device provided by the present application;

[0025] Figure 9 is a cross-sectional schematic diagram of a fifth embodiment of a storage device provided by the present application;

[0026] Figure 10 is a cross-sectional schematic diagram of a sixth embodiment of a storage device provided by the present application;

[0027] Figure 11 is a cross-sectional schematic diagram of a seventh embodiment of a storage device provided by the present application;

[0028] Figure 12 is a cross-sectional schematic diagram of an eighth embodiment of a storage device provided by the present application;

[0029] Figure 13 is a cross-sectional schematic diagram of a ninth embodiment of a storage device provided by the present application;

[0030] Figure 14 is a structural schematic diagram of an embodiment of a test system of a storage device provided by the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0032] It should be noted that if the application embodiments have directionality indication (such as up, down, left, right, front, back, …), the directionality indication is only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), if the certain posture changes, the directionality indication also changes accordingly.

[0033] In addition, if the application embodiments have descriptions of "first", "second", etc., the "first", "second", etc. descriptions are only for description purposes, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the application.

[0034] Please refer to Figures 1-2 , Figure 1 is a structural schematic diagram of a first embodiment of a storage device provided by the application. Figure 2 is a structural schematic diagram of an embodiment of a calibration network.

[0035] The storage device 100 includes a storage unit 110 and a plurality of calibration compensation circuits 120. The storage unit 110 is used to realize the storage function of the storage device 100. The storage unit 110 includes a plurality of storage chips 111 (DIE), which is a small piece of semiconductor material on which a given functional circuit is manufactured to realize the data storage function. Please further refer to Figure 2 , each storage chip 111 is provided with a calibration network 400. The impedance in the storage chip 111 may not be accurate, and by setting the calibration network 400 to anchor the standard resistance of the outside world, the impedance in the storage chip 111 is adjusted to realize impedance matching and improve the accuracy of the impedance in the storage chip 111.

[0036] In a specific application scenario, the calibration network 400 can include a control circuit 401 and a calibration adjustment circuit 402. The calibration adjustment circuit 402 is connected with the control circuit 401 and the calibration compensation circuit 120 respectively, and the control circuit 401 is also connected with the calibration compensation circuit 120. The control circuit 401 includes an RCV circuit (receiver) or other control circuit, and the calibration adjustment circuit 402 is composed of a plurality of MOS tubes. The impedance of the calibration adjustment circuit 402 can deviate, and therefore needs to be regulated by the control circuit 401 for impedance matching. The control circuit 401 is used to calibrate the resistance of the control circuit 401 based on the resistance of the calibration compensation circuit 120, so as to obtain the matched impedance after calibration, and to realize the normal function of the storage chip 111.

[0037] The calibration compensation circuit 120 is connected with the corresponding storage chip 111 one by one, so as to activate the calibration network 400 in the storage chip 111 to perform calibration matching. Specifically, after the calibration network 400 is activated, the storage chip 111 adjusts its own impedance through the calibration network 400, so as to match the calibration compensation circuit 120 connected therewith. After the matching, the stability of the output signal of the storage chip 111 is improved.

[0038] The specific number of the calibration compensation circuit 120 and the storage chip 111 is set based on actual needs, and is not limited.

[0039] The type of the storage device 100 of the embodiment includes but is not limited to various types of DDR (Double Data Rate DRAM, double data rate dynamic random access memory), various types of LPDDR (Low Power Double Data Rate DRAM, low power double data rate dynamic random access memory), such as LPDDR1, LPDDR2, LPDDR3, LPDDR4 / 4X, LPDDR5 / 5X, DDR3, DDR4 or DDR5, etc., which are not limited herein.

[0040] Through the above steps, the storage device of the embodiment includes a storage unit and a plurality of calibration compensation circuits. The storage unit includes a plurality of storage chips, each of which is provided with a calibration network. The calibration compensation circuit is connected with the storage chip one by one to activate the calibration network for calibration matching, so that the storage chip adjusts its own impedance through the calibration network, so as to match the calibration compensation circuit connected therewith. After the matching, the stability of the output signal of the storage chip is improved, the calibration mismatch of the storage chip is reduced, the situation that the product function is not complete or problems occur is avoided, and the stability and reliability of the storage device are improved. The above calibration can solve the calibration mismatch problem at the wafer packaging stage, ensure the normal calibration of the storage device, and thus be suitable for mainstream platforms.

[0041] Further reference is made to Figures 3-4 , Figure 3 is a structural block diagram of a first embodiment of a storage device provided by the present application. Figure 4 is a cross-sectional diagram of the first embodiment of the storage device provided by the present application. The above diagram shows two storage chips and one calibration compensation circuit, which is only for illustration and does not limit the number of storage chips and calibration compensation circuits in the storage device.

[0042] In some embodiments, the calibration compensation circuit 120 includes a calibration resistor 121; one end of the calibration resistor 121 is connected to the corresponding storage chip 111, and the other end of the calibration resistor 121 is connected to the power supply or ground.

[0043] When the calibration resistor 121 is connected to the power supply or ground, the calibration compensation circuit 120 is started to activate the check network in the storage chip 111; wherein the selection of whether the calibration resistor 121 is connected to the power supply to start the calibration compensation circuit 120 or connected to the ground to start the calibration compensation circuit 120 is based on the corresponding setting of different types of storage 100, so as to meet the wide applicability.

[0044] Among them, the calibration resistor 121 is a fixed value resistor, and its specific resistance value can be set correspondingly based on the type of different storage device 100, so as to activate the corresponding check network. In different types of storage device 100, the resistance value of the calibration resistor 121 can include but is not limited to 15 ohms, 50 ohms, 100 ohms, 180 ohms, 200 ohms, 220 ohms, 240 ohms or 300 ohms, etc.

[0045] The above calibration compensation circuit 120 has low cost and simple and ingenious design scheme, and does not affect the packaging operation.

[0046] In some embodiments, the plurality of pads on the memory chip 111 include internal signal pads 112, functional pads 113, and external signal pads 114. The pads 134 are used for data transmission or exchange. The signal types of the external signal pads 114 include DQ signals (data signals), CA signals (address signals), CS (Chip Select, chip selection signals), CKE (Clock Enable, clock enable signals), and other signals transmitted externally. The functional pads 113 are used for power supply or grounding, including power supply pads and grounding pads. The internal signal pads 112 refer to special enable signals, such as ZQRX, ZQTX (ZQ Receiver or Transfer, chip internal communication signals), ODT (On-Die Termination, on-die termination resistance), and other signals transmitted internally in the memory device 100. The specific number of internal signal pads 112, functional pads 113, and external signal pads 114 can be multiple, and is set based on the connection requirements of the memory chip 111, which is not limited here.

[0047] One end of the calibration resistance 121 is connected to the internal signal pad 112 of the corresponding memory chip 111, and the other end of the calibration resistance 121 is grounded or connected to a power supply. By connecting the calibration resistance 121 to the internal signal pad 112, the calibration network in the memory chip 111 is activated internally.

[0048] In some embodiments, the memory unit 110 includes a circuit board 150, a plurality of memory chips 111, and a plastic encapsulation layer 140.

[0049] The plurality of memory chips 111 and the calibration compensation circuit 120 are fixed on the first side 151 of the circuit board 150, and the plastic encapsulation layer 140 encapsulates the first side 151 of the circuit board 150 and wraps each memory chip 111 and the calibration compensation circuit 120 for encapsulation, to fix the relative positions between the circuit board 150, the memory chip 111, and the calibration compensation circuit 120, and improve the stability of the memory device 100.

[0050] The circuit board 150 is a PCB (Printed Circuit Board) with a prepared circuit structure, wherein the circuit of the circuit board 150 is patterned. The circuit board 150 can be a multi-layer board with only through-hole interconnections, or a HDI (High Density Interconnector) board containing blind-hole interconnections. The specific structure of the circuit board 150 is set based on actual requirements.

[0051] The plastic sealing layer 140 includes one or more of the following insulating materials: epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), Ajinomoto build film (ABF), FR4 resin, etc.

[0052] The internal signal pad 112, the function pad 113, and the external signal pad 114 of the storage chip 111 are respectively connected to the corresponding pads 134 on the first side 151 of the circuit board 150. In a specific application scenario, the pads 134 on the circuit board 150 can include a first pad 131, a second pad 132, and a third pad 133. The first pad 131 is connected to the internal signal pad 112, the second pad 132 is connected to the function pad 113, and the third pad 133 is connected to the external signal pad 114, so as to realize the connection between the circuit board 150 and the storage chip 111.

[0053] In some embodiments, the storage unit 110 further includes a plurality of connectors 160. The connectors 160 are arranged in the plastic sealing layer 140. One end of each connector 160 is connected to the pad of the storage chip 111, and the other end of the connector 160 is connected to the corresponding pad 134 on the first side 151 of the circuit board 150, so as to realize the connection between the circuit board 150 and the storage chip 111.

[0054] The connector 160 includes one or more of the following: a connecting line, a plated connector, or a stamped connector, without limitation.

[0055] Please further refer to Figure 5 , Figure 5 is a schematic diagram of an amplification structure of the calibration compensation circuit.

[0056] The calibration compensation circuit 120 includes a wire bonding pad 122, a first wire 123, a first resistance pad 124, a calibration resistance 121, a second resistance pad 125, and a second wire 126 connected in sequence.

[0057] The wire bonding pad 122 is also connected to the internal signal pad 112 on the corresponding storage chip 111. Specifically, the wire bonding pad 122 and the internal signal pad 112 can be connected through the connector 160.

[0058] The second wire 126 is connected to the ground or the power supply 170 at the end away from the second resistance pad 125.

[0059] The calibration resistor 121 is welded to the first side 151 of the circuit board 150 through the first resistance pad 124 and the second resistance pad 125, and the first trace 123 and the second trace 126 are embedded in the circuit board 150, so as to fix the calibration resistor 121 and its connecting mechanism on the first side 151 of the circuit board 150.

[0060] Please refer back Figure 4 The circuit board 150 is provided with the connecting mechanism 180, and the second side 152 of the circuit board 150 is fixedly provided with a plurality of tin balls 153; the connecting mechanism 180 is connected with the pads 134 of the respective memory chips 111 and the corresponding tin balls 153, so as to connect the signals of the memory chips 111 to the outside through the tin balls 153.

[0061] In a specific application scenario, the connecting mechanism 180 can include a metalized hole and a conductive circuit, and the specific position and shape of the metalized hole and the conductive circuit include a plurality of types, which can be set according to the electrical connection requirements of the circuit board 150, and are not limited herein.

[0062] In a specific application scenario, the plurality of memory chips 111 are arranged on the first side 151 of the circuit board 150 in a vertical stacking, side-by-side arrangement and / or stepped stacking manner.

[0063] The memory chips 111 are stacked and fixed by the adhesive 119. Figure 4 The side-by-side arrangement is shown.

[0064] Please refer back Figure 6 , Figure 6 is a cross-sectional schematic view of a second embodiment of the storage device provided by the present application.

[0065] The present embodiment takes four memory chips as an example for illustration, wherein the first memory chip 211 and the second memory chip 212 are offset stacked, that is, in the vertical direction, the positions of the two chips are offset; the third memory chip 213 and the fourth memory chip 214 are vertically stacked, that is, in the vertical direction, the positions of the two chips coincide.

[0066] In the storage device, the vertical stacking, side-by-side arrangement and stepped stacking can be set in one or a plurality of mixed manners according to actual requirements and the number of memory chips, and the specific selection is not limited herein.

[0067] In a specific application scenario, the first storage chip 211 is connected with the first calibration compensation circuit 222 to activate the calibration network in the first calibration compensation circuit 222. The third storage chip 213 is connected with the second calibration compensation circuit 221 to activate the calibration network in the second calibration compensation circuit 221. The second storage chip 212 and the fourth storage chip 214 can not be connected with the corresponding calibration compensation circuit in the storage device, but can be connected with the corresponding calibration compensation circuit on the test board one by one when testing the storage chip, that is, when testing, the test board can be used to realize the full corresponding connection between the plurality of storage chips and the corresponding calibration compensation circuit. The storage device is provided with part of the corresponding calibration compensation circuit, which can save the internal space of the storage device, facilitate the miniaturization and lightening of the storage device, and facilitate the improvement of the wiring degree of freedom in the storage device.

[0068] In a specific application scenario, if there are N storage chips in the storage device, N is a positive integer, then N calibration compensation circuits can be correspondingly arranged on the first side of the circuit board to be connected with the storage chips one by one, so that each storage chip is provided with a corresponding calibration compensation circuit to improve the test stability.

[0069] Please refer back Figure 1 , Figure 1 The above-mentioned schematic diagram is an embodiment in which each storage chip is provided with a corresponding calibration compensation circuit; please refer back Figure 3 、 4 , 5, the above-mentioned schematic diagram is an embodiment in which part of the storage chips are provided with a corresponding calibration compensation circuit; wherein, in the storage device, at least part of the storage chips are provided with a corresponding calibration compensation circuit, and the calibration compensation circuits of the other storage chips can be supplemented by the test board.

[0070] Please refer back Figure 7 , Figure 7 is a cross-sectional schematic diagram of the third embodiment of the storage device provided by the present application.

[0071] The embodiment shown in the present application is that the first storage chip 61 and the second storage chip 62 are offset stacked, and the first storage chip 61 is connected with the calibration compensation circuit 63. The stacked chips are not connected, but are directly connected with the pads on the circuit board.

[0072] Please refer back Figure 8 , Figure 8 is a cross-sectional schematic diagram of the fourth embodiment of the storage device provided by the present application.

[0073] The embodiment shown in the present application is that the first storage chip 71 and the second storage chip 72 are vertically stacked, and the third storage chip 73 and the fourth storage chip 74 are vertically stacked, and the first storage chip 71 is connected with the calibration compensation circuit 75. The stacked chips are not connected, but are directly connected with the pads on the circuit board.

[0074] Please refer to Figure 9 , Figure 9 is a cross-sectional schematic view of the fifth embodiment of the storage device provided in the present application.

[0075] The first storage chip 81 and the second storage chip 82 are offset stacked, the third storage chip 83 and the fourth storage chip 84 are offset stacked, and the first storage chip 81 is connected with the calibration compensation circuit 85. The stacked chips are not connected with each other, but are directly connected with the pads on the circuit board.

[0076] Please refer to Figure 10 , Figure 10 is a cross-sectional schematic view of the sixth embodiment of the storage device provided in the present application.

[0077] The first storage chip 91 and the second storage chip 92 are offset stacked, the third storage chip 93 and the fourth storage chip 94 are offset stacked, and the first storage chip 91 is connected with the calibration compensation circuit 95. The stacked chips are connected with each other, that is, the first storage chip 91 is connected with the pads of the second storage chip 92 and the pads of the circuit board, the third storage chip 93 is connected with the pads of the fourth storage chip 94 and the pads of the circuit board, and the second storage chip 92 and the fourth storage chip 94 are directly connected with the pads of the circuit board.

[0078] The connection relationship between the stacked chips can be set according to actual needs, which is not limited herein. Among them, Figures 7-10 are various embodiments under one calibration compensation circuit, that is, when there are 4m or 2m storage chips in the storage device, and m calibration compensation circuits, the setting structure can refer to Figures 7-10 , m is a positive integer.

[0079] Please refer to Figure 11 , Figure 11 is a cross-sectional schematic view of the seventh embodiment of the storage device provided in the present application.

[0080] The first storage chip 1001 and the second storage chip 1002 are vertically stacked, the first storage chip 1001 is connected with the first calibration compensation circuit 1003, and the second storage chip 1002 is connected with the second calibration compensation circuit 1004. The stacked chips are not connected with each other, but are directly connected with the pads on the circuit board.

[0081] Please refer to Figure 12 , Figure 12 is a cross-sectional schematic view of the eighth embodiment of the storage device provided in the present application.

[0082] The first storage chip 1101 and the second storage chip 1102 are offset stacked, the third storage chip 1103 and the fourth storage chip 1104 are offset stacked, the second storage chip 1102 is connected with the first calibration compensation circuit 1005, and the third storage chip 1103 is connected with the second calibration compensation circuit 1006. The stacked chips are connected, that is, the first storage chip 1101 is connected with the pad of the circuit board through the pad of the second storage chip 1102, and the third storage chip 1103 is connected with the pad of the circuit board through the pad of the fourth storage chip 1104; the second storage chip 1102 and the fourth storage chip 1104 are directly connected with the pad of the circuit board. Wherein, Figures 11-12 The above-mentioned connection and setting described embodiments are only part of the embodiments of the present application, but not all the embodiments, and the equivalent structures based on the above-mentioned embodiments all belong to the protection scope of the present application. Figures 11-12

[0083] Please refer to Figure 13 Figure 13 is a cross-sectional schematic view of the ninth embodiment of the storage device provided by the present application.

[0084] The first storage chip 1201 and the second storage chip 1202 are vertically stacked, the third storage chip 1203 and the fourth storage chip 1204 are vertically stacked, the first storage chip 1201 is connected with the first calibration compensation circuit 1205, the second storage chip 1102 is connected with the second calibration compensation circuit 1206, the third storage chip 1103 is connected with the third calibration compensation circuit 1208, and the fourth storage chip 1204 is connected with the fourth calibration compensation circuit 1207. Each storage chip is directly connected with the pad on the circuit board.

[0085] That is, the four storage chips of the present embodiment are connected with the four calibration compensation circuits one by one, and are applied to the embodiment of full connection of the storage chip and the calibration compensation circuit.

[0086] The above-mentioned connection and setting described embodiments are only part of the embodiments of the present application, but not all the embodiments, and the equivalent structures based on the above-mentioned embodiments all belong to the protection scope of the present application.

[0087] Through the above-mentioned structure, the storage device of the present embodiment includes a storage unit and a plurality of calibration compensation circuits, the storage unit includes a plurality of storage chips, each storage chip is provided with a calibration network, the calibration compensation circuit is connected with the storage chip one by one to activate the calibration network for calibration matching, so that the storage chip adjusts its impedance through the calibration network to match the connected calibration compensation circuit, after matching, it is beneficial to improve the stability of the output signal of the storage chip, reduce the calibration mismatch of the storage chip, cause the product function to be incomplete or the problem to occur, and improve the stability and reliability of the storage device.​​

[0088] Based on the same concept, the application also provides a test system of the storage device, please refer to Figure 14 , Figure 14 is a structural schematic diagram of an embodiment of the test system of the storage device provided by the application.

[0089] The test system 300 of the storage device of the embodiment comprises a storage device 310, a test board 320 and a tester 330 connected in sequence. The tester 330 connects the storage device 310 through the test board 320 to perform relevant tests.

[0090] The storage device 310 comprises the storage device 100 of any of the above embodiments. Therefore, when the calibration compensation circuit in the storage device 310 is tested, the calibration network in the storage chip will be activated for calibration matching, so that the storage chip will adjust its impedance through the calibration network to match the calibration compensation circuit connected thereto. After matching, it is beneficial to improve the stability of the output signal of the storage chip, reduce the calibration mismatch of the storage chip, cause the product function to be incomplete or have problems, and improve the stability and reliability of the storage device.

[0091] In some embodiments, other calibration compensation circuits can be provided on the test board 320, and the other calibration compensation circuits are connected one by one with other storage chips in the storage device 310 that are not connected with the calibration compensation circuit to activate the calibration network of the other storage chips for calibration matching.

[0092] That is, when only part of the storage chips in the storage device 310 are provided with corresponding calibration compensation circuits, corresponding calibration compensation circuits are provided on the test board 320 for the remaining part of the storage chips to realize that each storage chip is connected with a corresponding calibration compensation circuit during testing.

[0093] The test system 300 of the storage device of the embodiment can be applied to pre-shipment testing and post-shipment maintenance of the storage device 310.

[0094] In some embodiments, the calibration method of the storage device can comprise:

[0095] Step S11: In response to detecting that the storage chip of the storage device has calibration mismatch through the tester, connecting the calibration compensation circuit of the storage device with the power supply and the corresponding storage chip respectively to activate the calibration network in the storage chip for calibration matching until the impedance of the storage chip matches the impedance of the calibration compensation circuit.

[0096] When the calibration mismatch of the storage chip is detected by the tester, i.e., the signal output is unstable, the calibration compensation circuit of the storage device is connected with the power supply and the corresponding storage chip, so as to start the calibration compensation circuit and activate the calibration network for calibration matching, until the impedance of the storage chip matches the impedance of the calibration compensation circuit.

[0097] After impedance matching, it is indicated that the signal output of the storage chip is stable.

[0098] Step S12: In response to the calibration matching of the storage chip detected by the tester, the end of the calibration compensation circuit of the storage device connected with the power supply is adjusted to be grounded.

[0099] When the tester detects the calibration matching of the storage chip, the end of the calibration compensation circuit of the storage device connected with the power supply is adjusted to be grounded, so that the calibration compensation circuit is powered off and silent, thereby not affecting the normal operation of the storage chip.

[0100] Through the above steps, the calibration compensation circuit of the calibration method of the storage device of the embodiment will activate the calibration network in the storage chip for calibration matching during testing, so that the storage chip adjusts its own impedance through the calibration network to match the connected calibration compensation circuit. After matching, it is beneficial to improve the stability of the output signal of the storage chip, reduce the calibration mismatch of the storage chip, and reduce the occurrence of incomplete product functions or problems, thereby improving the stability and reliability of the storage device.

[0101] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A storage device, characterized in that, The storage device includes: A storage unit, the storage unit comprising a plurality of storage chips, each of the storage chips having a calibration network disposed therein; Multiple calibration compensation circuits are provided, each connected to a corresponding memory chip, to activate the calibration network for calibration matching.

2. The storage device according to claim 1, characterized in that, The calibration compensation circuit includes a calibration resistor; One end of the calibration resistor is connected to the corresponding memory chip, and the other end of the calibration resistor is connected to the power supply or ground.

3. The storage device according to claim 2, characterized in that, The memory chip is provided with multiple pads, including internal signal pads, functional pads, and external signal pads. One end of the calibration resistor is connected to the internal signal pad of the corresponding memory chip.

4. The storage device according to claim 3, characterized in that, The storage unit includes a circuit board, multiple storage chips, and a molding compound. Multiple memory chips and the calibration compensation circuit are fixed to the first side of the circuit board. The molding layer encapsulates the first side of the circuit board and wraps each memory chip and the calibration compensation circuit for molding. The internal signal pads, functional pads, and external signal pads of the memory chip are connected to corresponding pads on the first side of the circuit board.

5. The storage device according to claim 4, characterized in that, The storage unit also includes a plurality of connectors disposed within the molding compound. One end of each connector is connected to the pad of the storage chip, and the other end of each connector is connected to a corresponding pad on the first side of the circuit board. The connector includes one or more of the following: a connecting wire, an electroplated connector, or a stamped connector.

6. The storage device according to claim 4, characterized in that, The circuit board is provided with a connecting mechanism, and a plurality of solder balls are fixedly provided on the second side of the circuit board; the connecting mechanism connects the pads on the first side of the circuit board and the corresponding solder balls respectively.

7. The storage device according to claim 4, characterized in that, The calibration compensation circuit includes wire bonding pads, a first trace, a first resistor pad, the calibration resistor, a second resistor pad, and a second trace connected in sequence. The wire bonding pad is also connected to the internal signal pad on the corresponding memory chip, and the end of the second trace away from the second resistor pad is grounded or connected to the power supply. The calibration resistor is soldered to the first side of the circuit board via the first resistor pad and the second resistor pad; the first trace and the second trace are embedded within the circuit board.

8. The storage device according to claim 4, characterized in that, Multiple memory chips are arranged on the first side of the circuit board by means of vertical stacking, side-by-side placement and / or stepped stacking; The memory chips are stacked and fixed together using adhesive.

9. The storage device according to claim 1, characterized in that, The calibration network includes a control circuit and a calibration adjustment circuit. The calibration adjustment circuit is connected to both the control circuit and the calibration compensation circuit. The control circuit is also connected to the calibration compensation circuit so that the control circuit performs impedance matching on the calibration adjustment circuit based on the impedance of the calibration compensation circuit.

10. A testing system for a storage device, characterized in that, The testing system for the storage device includes a storage device, a test board, and a tester connected in sequence; the storage device includes the storage device as described in any one of claims 1-9; The test board is equipped with other calibration compensation circuits, which are connected to other memory chips in the storage device that are not connected to the calibration compensation circuits, so as to activate the calibration network of the other memory chips for calibration matching.

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