Oscillation circuit, chip and electronic device
By introducing a crystal oscillator drive module, a self-biased reference module, and a current adjustment module into the oscillation circuit, and controlling the phased adjustment of the reference current, the problems of power consumption and start-up time in the oscillation circuit are solved, achieving the effects of fast start-up and low power consumption.
Patent Information
- Application Number
- CN202520101262.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2035-01-16
AI Technical Summary
Excessive drive current in an oscillating circuit can lead to high power consumption, while insufficient drive current may result in longer start-up time or failure to start oscillation.
An oscillation circuit design including a crystal oscillator drive module, a self-biased reference module, and a current adjustment module is adopted. The reference current in the oscillation stage is controlled to be greater than the reference current in the steady stage by the current adjustment module, so as to improve the oscillation speed and reduce the power consumption in the steady stage.
By increasing the crystal oscillation speed during the oscillation phase and reducing the power consumption for maintaining the oscillation during the stabilization phase, power consumption optimization is achieved.
Smart Images
Figure CN223872259U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, specifically to an oscillation circuit, a chip, and an electronic device. Background Technology
[0002] An oscillating circuit is an electronic circuit that generates continuous periodic signals. Among them, crystal oscillators are widely used in various electronic devices, such as communication networks, wireless data transmission, high-speed digital data transmission, color televisions, radar, and clocks, because they can provide stable and accurate clock signals.
[0003] However, if the drive current provided by the oscillation circuit to the crystal oscillator is too large, the overall power consumption will be high, while if the drive current is too small, the crystal oscillator may take longer to start oscillating, or even fail to start oscillating at all. Utility Model Content
[0004] In view of the above problems, embodiments of this application provide an oscillation circuit, a chip, and an electronic device to solve the above technical problems.
[0005] In a first aspect, embodiments of this application provide an oscillation circuit, which includes a crystal oscillator driving module, a self-biased reference module, and a current adjustment module. The self-biased reference module is used to generate a reference current. The current adjustment module is connected to the self-biased reference module and is used to control the reference current in the oscillation start-up stage to be greater than the reference current in the stable stage. The crystal oscillator driving module is connected to the self-biased reference module and is used to mirror the crystal oscillator driving current according to the reference current.
[0006] Secondly, embodiments of this application also provide a chip that includes the aforementioned oscillation circuit.
[0007] Thirdly, embodiments of this application also provide an electronic device, which includes a device body and the aforementioned oscillation circuit or chip disposed on the device body.
[0008] The oscillation circuit, chip, and electronic device provided in this application embodiment are connected to the self-biased reference module through a current adjustment module. This allows the reference current generated by the self-biased reference module during the oscillation start-up phase to be greater than the reference current generated by the self-biased reference module during the stabilization phase. This improves the oscillation start-up speed of the crystal oscillator during the oscillation start-up phase and reduces the oscillation maintenance power consumption during the stabilization phase.
[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 A first principle block diagram of the oscillation circuit provided in an embodiment of this application is shown.
[0012] Figure 2 The schematic diagram of the current adjustment module is shown.
[0013] Figure 3 The circuit diagrams of the switching unit and the impedance unit are shown.
[0014] Figure 4 The first circuit schematic of the self-biased reference module is shown.
[0015] Figure 5 The second circuit schematic of the self-biased reference module is shown.
[0016] Figure 6 The first circuit schematic of the crystal oscillator drive module is shown.
[0017] Figure 7 Another block diagram of the crystal oscillator driver module is shown.
[0018] Figure 8 A block diagram of the current adjustment unit is shown.
[0019] Figure 9 The circuit schematic of the first mirror component is shown.
[0020] Figure 10 The circuit schematic of the switching assembly is shown.
[0021] Figure 11 The circuit schematic of the second mirror component is shown.
[0022] Figure 12 A circuit schematic diagram of the oscillation circuit provided in an embodiment of this application is shown.
[0023] Figure 13 A second principle block diagram of the oscillation circuit provided in an embodiment of this application is shown.
[0024] Figure 14 The schematic diagram of the timing control module is shown.
[0025] Figure 15 The first principle block diagram of the comparison submodule is shown.
[0026] Figure 16 The circuit schematic of the first comparator is shown.
[0027] Figure 17 The circuit schematic of the second comparator is shown.
[0028] Figure 18 The second principle block diagram of the comparison submodule is shown.
[0029] Figure 19 The circuit schematic of the comparison submodule is shown.
[0030] Figure 20 The block diagram of the counting submodule is shown.
[0031] Figure 21 The circuit diagram of the frequency divider unit is shown.
[0032] Figure 22 The circuit schematics of the inverting unit and the output unit are shown.
[0033] Figure 23 A timing diagram of the timing control module is shown.
[0034] Figure 24 A schematic diagram of the chip structure provided in an embodiment of this application is shown.
[0035] Figure 25 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation
[0036] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0037] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0038] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0039] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0040] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0041] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0042] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0043] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.
[0044] This application provides an oscillation circuit 100, such as... Figure 1As shown, the oscillation circuit 100 includes a crystal oscillator drive module 10, a self-biased reference module 20, and a current adjustment module 30. The current adjustment module 30 is connected to the self-biased reference module 20, which can control the reference current generated by the self-biased reference module 20 in the oscillation start-up stage to be greater than the reference current generated by the self-biased reference module 20 in the stabilization stage. This can improve the oscillation start-up speed of the crystal oscillator in the oscillation start-up stage and reduce the oscillation maintenance power consumption in the stabilization stage.
[0045] This application provides an oscillation circuit 100. Please refer to [link / reference]. Figures 1 to 23 ,like Figure 1 As shown, the oscillation circuit 100 includes a crystal oscillator drive module 10, a self-biased reference module 20, and a current adjustment module 30. The self-biased reference module 20 is used to generate a reference current. The current adjustment module 30 is connected to the self-biased reference module 20 and is used to control the reference current in the oscillation stage to be greater than the reference current in the stable stage. The crystal oscillator drive module 10 is connected to the self-biased reference module 20 and is used to mirror the crystal oscillator drive current according to the reference current.
[0046] It is understood that the oscillation circuit 100 provided in this application embodiment is connected to the self-biased reference module 20 through the current adjustment module 30. It can control the reference current generated by the self-biased reference module 20 in the oscillation start-up stage to be greater than the reference current generated by the self-biased reference module 20 in the stabilization stage, thereby improving the oscillation start-up speed of the crystal oscillator in the oscillation start-up stage and reducing the oscillation maintenance power consumption in the stabilization stage.
[0047] Optionally, such as Figure 2 As shown, the current adjustment module 30 includes an impedance unit 31 and a switching unit 32. The impedance unit 31 is connected between the self-biased reference module 20 and the ground terminal GND. The switching unit 32 is connected in parallel with the impedance unit 31. The switching unit 32 is in the conducting state during the oscillation stage and in the disconnected state during the stabilization stage.
[0048] It should be noted that when the switching unit 32 is in the on state during the oscillation start-up phase, it can short-circuit the impedance unit 31, thereby preventing the impedance unit 31 from being connected to the self-biasing reference module 20. This increases the reference current generated by the self-biasing reference module 20, which in turn increases the crystal oscillator drive current and improves the start-up speed of the crystal oscillator. When the switching unit 32 is in the off state during the stabilization phase, the impedance unit 31 can be connected to the self-biasing reference module 20. This reduces the reference current generated by the self-biasing reference module 20, thereby reducing the crystal oscillator drive current and reducing power consumption when the oscillation is stable.
[0049] Optionally, such as Figure 3As shown, impedance unit 31 includes a first resistor R3, one end of which is connected to the self-biased reference module 20, and the other end of which is connected to the ground terminal GND. Switching unit 32 includes a first transmission gate T4, the first end of which is connected to one end of the first resistor R3, the second end of which is connected to the other end of the first resistor R3, the third end of which is connected to a first control signal SP1, and the fourth end of which is connected to a second control signal SN1.
[0050] It should be noted that when the first control signal SP1 is at a low level and the second control signal SN1 is at a high level, the first transmission gate T4 is in the on state. When the first control signal SP1 is at a high level and the second control signal SN1 is at a low level, the first transmission gate T4 is in the off state.
[0051] In some other embodiments, the first control signal SP1 is at a high level, the second control signal SN1 is at a low level, and the first transmission gate T4 is in the on state. Alternatively, the first control signal SP1 is at a low level, the second control signal SN1 is at a high level, and the first transmission gate T4 is in the off state.
[0052] Optionally, such as Figure 4 As shown, the self-biased reference module 20 includes a first transistor MP6, a second transistor MN2, a third transistor MP7, and a fourth transistor MN3. The first terminal of the first transistor MP6 is connected to the first power supply terminal VDD, and the control terminal of the first transistor MP6 is connected to the crystal oscillator drive module 10. The first terminal of the second transistor MN2 is connected to the control terminal of the second transistor MN2 and the second terminal of the first transistor MP6, and the second terminal of the second transistor MN2 is connected to the ground terminal GND. The first terminal of the third transistor MP7 is connected to the first terminal of the first transistor MP6, and the second terminal of the third transistor MP7 is connected to the control terminal of the third transistor MP7 and the crystal oscillator drive module 10. The first terminal of the fourth transistor MN3 is connected to the second terminal of the third transistor MP7 and the crystal oscillator drive module 10, the control terminal of the fourth transistor MN3 is connected to the control terminal of the second transistor MN2, and the second terminal of the fourth transistor MN3 is connected to one end of the first resistor R3 and the first end of the first transmission gate T4.
[0053] It should be noted that the first transistor MP6 and the third transistor MP7 form a current mirror structure. Since the first transistor MP6 and the second transistor MN2 are connected in series, the current flowing through the first transistor MP6 is equal to the current flowing through the second transistor MN2. Similarly, since the third transistor MP7 and the fourth transistor MN3 are connected in series, the current flowing through the third transistor MP7 is equal to the current flowing through the fourth transistor MN3. The reference current is either the current flowing through the third transistor MP7 or the current flowing through the fourth transistor MN3. VBIAS is the bias voltage generated by the self-biased reference module 20. The control electrode can be either the gate or the base.
[0054] Optionally, such as Figure 5 As shown, the self-biased reference module 20 also includes a second resistor R2. One end of the second resistor R2 is connected to the second terminal of the fourth transistor MN3, and the other end of the second resistor R2 is connected to one end of the first resistor R3 and the first end of the first transmission gate T4.
[0055] It should be noted that in other embodiments, the second resistor R2 can also be connected between the first resistor R3 and the ground terminal GND. The second resistor R2 not only serves to adjust the reference current, but also ensures that VBIAS does not fall below the preset potential.
[0056] Optionally, such as Figure 6 As shown, the crystal oscillator driving module 10 includes a crystal oscillator driving unit 11, which includes a fifth transistor MP8 and a sixth transistor MN4. The first terminal of the fifth transistor MP8 is connected to the first power supply terminal VDD, and the control terminal of the fifth transistor MP8 is connected to the control terminal of the third transistor MP7. The first terminal of the sixth transistor MN4 is connected to the second terminal of the fifth transistor MP8, the first terminal of the crystal oscillator Crystal, the first terminal of the third resistor RF, and one end of the second capacitor CL2. The control terminal of the sixth transistor MN4 is connected to the second terminal of the crystal oscillator Crystal, one end of the first capacitor CL1, and the second terminal of the third resistor RF. The second terminal of the sixth transistor MN4 is connected to the other end of the first capacitor CL1, the other end of the second capacitor CL2, and the ground terminal GND.
[0057] It should be noted that the fifth transistor MP8 and the first transistor MP6 form a current mirror structure. The current flowing through the fifth transistor MP8 is the crystal oscillator drive current. Due to the current mirror relationship, the crystal oscillator drive current will change in the positive direction with the reference current. Here, XO represents the potential of the first terminal of the crystal oscillator, and XI represents the potential of the second terminal of the crystal oscillator.
[0058] Optionally, such as Figure 7As shown, the crystal oscillator drive module 10 also includes a current adjustment unit 12, which is connected to the crystal oscillator drive unit 11. The current adjustment unit 12 is used to increase the crystal oscillator drive current during the start-up phase and not change the crystal oscillator drive current during the stable phase.
[0059] It should be noted that the current adjustment unit 12 can also be connected to the first power supply terminal VDD and the ground terminal GND.
[0060] Optionally, such as Figure 8 As shown, the current adjustment unit 12 includes a first mirror component 121, a switch component 122, and a second mirror component 123. The first mirror component 121 is connected to the control electrode of the fifth transistor MP8 and the first power supply terminal VDD. The first mirror component 121 is used to selectively mirror the crystal oscillator drive current. The switch component 122 is connected between the first mirror component 121 and the first terminal of the crystal oscillator Crystal. The second mirror component 123 is connected to the control electrode of the sixth transistor MN4, the first mirror component 121, and the ground terminal GND.
[0061] It should be noted that the first mirror component 121 can selectively form a current mirror structure with the fifth transistor MP8 to selectively mirror the crystal oscillator drive current. The switching component 122 can selectively be turned on or off to control the connection between the first mirror component 121 and the first terminal of the crystal oscillator. The second mirror component 123 can selectively form a current mirror structure with the sixth transistor MN4 to selectively mirror the crystal oscillator drive current.
[0062] Optionally, such as Figure 9 As shown, the first mirror component 121 includes a second transmission gate T1 and a seventh transistor MP9. The first terminal of the second transmission gate T1 is connected to the control electrode of the fifth transistor MP8, the second terminal of the second transmission gate T1 is connected to the first control signal SP1, and the third terminal of the second transmission gate T1 is connected to the second control signal SN1. The control electrode of the seventh transistor MP9 is connected to the fourth terminal of the second transmission gate T1, the first electrode of the seventh transistor MP9 is connected to the first power supply terminal VDD, and the second electrode of the seventh transistor MP9 is connected to the switching component 122.
[0063] It should be noted that when the first control signal SP1 is at a low potential and the second control signal SN1 is at a high potential, the second transmission gate T1 is in the on state. When the first control signal SP1 is at a high potential and the second control signal SN1 is at a low potential, the second transmission gate T1 is in the off state. When the second transmission gate T1 is on, the seventh transistor MP9 and the fifth transistor MP8 form a current mirror structure. Alternatively, when the second transmission gate T1 is off, the seventh transistor MP9 will not affect or change the crystal oscillator drive current.
[0064] Optionally, such as Figure 10 As shown, the switching assembly 122 includes a third transmission gate T2. The first end of the third transmission gate T2 is connected to the second terminal of the seventh transistor MP9. The second end of the third transmission gate T2 is connected to the first control signal SP1. The third end of the third transmission gate T2 is connected to the second control signal SN1. The fourth end of the third transmission gate T2 is connected to the first end of the crystal oscillator Crystal.
[0065] It should be noted that when the first control signal SP1 is at a low potential, the second control signal SN1 is at a high potential, the third transmission gate T2 is in the on state, and the second terminal of the seventh transistor MP9 is connected to the first terminal of the crystal oscillator. Alternatively, when the first control signal SP1 is at a high potential, the second control signal SN1 is at a low potential, the third transmission gate T2 is in the off state, and the second terminal of the seventh transistor MP9 is disconnected from the first terminal of the crystal oscillator.
[0066] In some other embodiments, the first control signal SP1 is at a high level, the second control signal SN1 is at a low level, and the third transmission gate T2 is in the on state. Alternatively, the first control signal SP1 is at a low level, the second control signal SN1 is at a high level, and the third transmission gate T2 is in the off state.
[0067] Optionally, such as Figure 11 As shown, the second mirror component 123 includes a fourth transmission gate T3 and an eighth transistor MN5. The first terminal of the fourth transmission gate T3 is connected to the control electrode of the sixth transistor MN4, the second terminal of the fourth transmission gate T3 is connected to the first control signal SP1, and the third terminal of the fourth transmission gate T3 is connected to the second control signal SN1. The control electrode of the eighth transistor MN5 is connected to the fourth terminal of the fourth transmission gate T3, the first electrode of the eighth transistor MN5 is connected to the first terminal of the third transmission gate T2 and the second electrode of the seventh transistor MP9, and the second electrode of the eighth transistor MN5 is connected to the ground terminal GND.
[0068] It should be noted that when the first control signal SP1 is at a low potential, the second control signal SN1 is at a high potential, the fourth transmission gate T3 is in the on state, and the eighth transistor MN5 and the sixth transistor MN4 form a current mirror structure. When the first control signal SP1 is at a high potential, the second control signal SN1 is at a low potential, the fourth transmission gate T3 is in the off state, and the eighth transistor MN5 is off.
[0069] In some other embodiments, the first control signal SP1 is at a high level, the second control signal SN1 is at a low level, and the fourth transmission gate T3 is in the on state. Alternatively, the first control signal SP1 is at a low level, the second control signal SN1 is at a high level, and the fourth transmission gate T3 is in the off state.
[0070] Optionally, such as Figure 12 As shown, the oscillation circuit 100 also includes a startup module 40. The startup module 40 includes a ninth transistor MP1, a tenth transistor MP2, an eleventh transistor MP3, a twelfth transistor MN1, a thirteenth transistor MP4, a fourteenth transistor MP5, a third capacitor C1, and a fourth resistor R1. The first terminal of the ninth transistor MP1 is connected to the first power supply terminal VDD, and the control terminal of the ninth transistor MP1 is connected to the enable signal EN. The first terminal of the tenth transistor MP2 is connected to the second terminal of the ninth transistor MP1, and the control terminal of the tenth transistor MP2 is connected to the control terminal of the ninth transistor MP1. The first terminal of the eleventh transistor MP3 is connected to the second terminal of the tenth transistor MP2, and the control terminal of the eleventh transistor MP3 is connected to the control terminal of the tenth transistor MP2. The first terminal of the twelfth transistor MN1 is connected to the second terminal of the eleventh transistor MP3. The control terminal of the twelfth transistor MN1 is connected to the control terminal of the eleventh transistor MP3, and the second terminal of the twelfth transistor MN1 is connected to the ground terminal GND; the first terminal of the thirteenth transistor MP4 is connected to the first terminal of the ninth transistor MP1, and the control terminal of the thirteenth transistor MP4 is connected to the control terminal of the ninth transistor MP1; the first terminal of the fourteenth transistor MP5 is connected to the second terminal of the thirteenth transistor MP4, and the control terminal of the fourteenth transistor MP5 is connected to the first terminal of the twelfth transistor MN1; one end of the third capacitor C1 is connected to the control terminal of the fourteenth transistor MP5 and the first terminal of the twelfth transistor MN1, and the other end of the third capacitor C1 is connected to the ground terminal GND; one end of the fourth resistor R1 is connected to the second terminal of the fourteenth transistor MP5, and the other end of the fourth resistor R1 is connected to the second terminal of the first transistor MP6.
[0071] It should be noted that the startup module 40 can control the working state of the self-biased reference module 20. After the first power supply terminal VDD is powered on, the enable signal EN is low, and the ninth transistor MP1, the tenth transistor MP2, and the eleventh transistor MP3 are all turned on, slowly charging the third capacitor C1. At this time, the thirteenth transistor MP4 and the fourteenth transistor MP5 are turned on, pulling up the gate voltage of the fourth transistor MN3. The fourth transistor MN3 is turned on, pulling down the gate voltage of the third transistor MP7. After the first capacitor CL1 is fully charged, the fourteenth transistor MP5 is automatically turned off, and the self-biased reference module 20 is working normally.
[0072] The fifth transistor MP8 and the seventh transistor MP9 mirror the current of the third transistor MP7, providing drive current for the Crystal oscillator. The crystal oscillator drive module 10 adopts a classic Pierce oscillator architecture, with the sixth transistor MN4 and the eighth transistor MN5 as amplifier transistors, and the first capacitor CL1 and the second capacitor CL2 as load capacitors. Negative resistance analysis is used to ensure that the sum of the transconductances of the sixth transistor MN4 and the eighth transistor MN5, acting as amplifier transistors, meets the oscillation condition, i.e., the sum of their transconductances must be greater than five times the critical transconductance. The third resistor RF provides bias voltage to the sixth transistor MN4, the eighth transistor MN5, and the Crystal oscillator, enabling the oscillation circuit 100 to operate normally.
[0073] The value of the third resistor RF should be much larger than the negative resistance, for example, in the MΩ range.
[0074] Optionally, such as Figure 13 As shown, the oscillation circuit 100 also includes a timing control module 50, which is connected to the crystal drive module 10 and the current adjustment module 30. The timing control module 50 is used to generate a first control signal SP1 and a second control signal SN1 to characterize the start-up stage and the stable stage based on the potential of the two ends of the crystal oscillator Crystal in the crystal drive module 10.
[0075] It should be noted that the first control signal SP1 is at a low potential, and the second control signal SN1 is at a high potential. This can be used to characterize the oscillation start-up stage. The first control signal SP1 is at a high potential, and the second control signal SN1 is at a low potential. This can be used to characterize the steady-state stage.
[0076] Optionally, such as Figure 14 As shown, the timing control module 50 includes a comparison submodule 51, a counting submodule 52, and a first inverting module 53. The comparison submodule 51 is connected to the crystal oscillator and is used to generate a clock signal CLK based on the potentials at both ends of the crystal oscillator. The counting submodule 52 is connected to the comparison submodule 51 and the current adjustment module 30 and is used to generate a first control signal SP1 based on the counting result of the clock signal CLK. The first inverting module 53 is connected to the counting submodule 52 and the current adjustment module 30 and is used to generate a second control signal SN1 that is inverted from the first control signal SP1.
[0077] It should be noted that the first inverting module 53 may include an odd number of inverters connected in series. Therefore, when the first control signal SP1 is at a low level, the second control signal SN1 is at a high level; or, when the first control signal SP1 is at a high level, the second control signal SN1 is at a low level.
[0078] Optionally, such as Figure 15 As shown, the comparison submodule 51 includes a first comparator 511 and a second comparator 512. The first comparator 511 is connected to the crystal oscillator Crystal and is used to generate a first pair of differential amplified signals based on the differential amplification result of the potentials at both ends of the crystal oscillator Crystal. The second comparator 512 is connected to the first comparator 511 and is used to generate a clock signal CLK based on the first pair of differential amplified signals.
[0079] It should be noted that after the sine wave generated by the low-speed crystal oscillator Crystal passes through the first comparator 511, since the rising and falling edges of the square wave output by the first comparator 511 are relatively slow, the second comparator 512 can further increase the slope of the pulse edge of the clock signal CLK.
[0080] Optionally, such as Figure 16 As shown, the first comparator 511 includes a fifteenth transistor MP14, a sixteenth transistor MP15, a seventeenth transistor MN9, an eighteenth transistor MP16, a nineteenth transistor MN12, a twentieth transistor MN10, and a twenty-first transistor MN11. The first terminal of the fifteenth transistor MP14 is connected to the first power supply terminal VDD, and the control terminal of the fifteenth transistor MP14 is connected to the self-biased reference module 20 and the crystal oscillator drive module 10. The first terminal of the sixteenth transistor MP15 is connected to the second terminal of the fifteenth transistor MP14, and the control terminal of the sixteenth transistor MP15 is connected to the second terminal of the crystal oscillator Crystal in the crystal oscillator drive module 10. The first terminal of the seventeenth transistor MN9 is connected to the control terminal of the seventeenth transistor MN9 and the second terminal of the sixteenth transistor MP15, and the second terminal of the seventeenth transistor MN9 is connected to the ground terminal GND. The eighteenth transistor MP14... The first terminal of transistor 6 is connected to the first terminal of transistor 16 MP15; the control terminal of transistor 18 MP16 is connected to the first terminal of crystal oscillator Crystal; the first terminal of transistor 19 MN12 is connected to the control terminal of transistor 19 MN12 and the second terminal of transistor 18 MP16; the second terminal of transistor 19 MN12 is connected to ground terminal GND; the first terminal of transistor 20 MN10 is connected to the second terminal of transistor 18 MP16; the control terminal of transistor 20 MN10 is connected to the control terminal of transistor 17 MN9; the second terminal of transistor 20 MN10 is connected to ground terminal GND; the first terminal of transistor 21 MN11 is connected to the second terminal of transistor 16 MP15; the control terminal of transistor 21 MN11 is connected to the control terminal of transistor 19 MN12; the second terminal of transistor 21 MN11 is connected to ground terminal GND.
[0081] It should be noted that the control electrode of the fifteenth transistor MP14 is connected to the self-biased reference module 20 and the crystal oscillator drive module 10, and can be connected to VBIAS to reduce the number of bias voltages used. The first comparator 511 is a differential amplifier structure with feedback, which can output the differential amplification result of the voltages (XI, XO) across the two ends of the crystal oscillator, namely the first pair of differential amplified signals (Vp1, Vn1).
[0082] Optionally, such as Figure 17 As shown, the second comparator 512 includes a twenty-second transistor MP17, a twenty-third transistor MN13, a twenty-fourth transistor MP18, and a twenty-fifth transistor MN14. The first terminal of the twenty-second transistor MP17 is connected to the second power supply terminal VDDL, and the control terminal of the twenty-second transistor MP17 is connected to its second terminal. The first terminal of the twenty-third transistor MN13 is connected to the second terminal of the twenty-second transistor MP17, and the control terminal of the twenty-third transistor MN13 is connected to the second terminal of the sixteenth transistor MP15. The second terminal of the twenty-third transistor MN13 is connected to the ground terminal GND. The first terminal of the twenty-fourth transistor MP18 is connected to the first terminal of the twenty-second transistor MP17, and the control terminal of the twenty-fourth transistor MP18 is connected to the control terminal of the twenty-second transistor MP17. The second terminal of the twenty-fourth transistor MP18 is used to output the clock signal CLK. The first terminal of the twenty-fifth transistor MN14 is connected to the second terminal of the twenty-fourth transistor MP18, and the control terminal of the twenty-fifth transistor MN14 is connected to the second terminal of the eighteenth transistor MP16. The second terminal of the twenty-fifth transistor MN14 is connected to the ground terminal GND.
[0083] It should be noted that the twenty-second transistor MP17 and the twenty-fourth transistor MP18 form a current mirror structure, and the twenty-third transistor MN13 and the twenty-fifth transistor MN14 compare the first pair of differential amplified signals (Vp1, Vn1) to generate the clock signal CLK.
[0084] Optionally, such as Figure 17 As shown, the first comparator 511 is connected to the first power supply terminal VDD, and the second comparator 512 is connected to the second power supply terminal VDDL. The voltage of the first power supply terminal VDD is higher than the voltage of the second power supply terminal VDDL.
[0085] It should be noted that after the sine wave generated by the low-speed crystal oscillator Crystal passes through the first comparator 511, since the rising and falling edges of the square wave output by the first comparator 511 are relatively slow, the second comparator 512 uses a second power supply terminal VDDL with a lower potential than the first power supply terminal VDD, which can reduce power consumption.
[0086] Optionally, such as Figure 18 As shown, the comparison submodule 51 also includes a shaping unit 513, which is connected to the second comparator 512. The shaping unit 513 is used to generate a clock signal CLK based on the output signal of the second comparator 512.
[0087] It should be noted that the shaping unit 513 can further improve the slope of the rising and falling edges of the output signal of the second comparator 512.
[0088] Optionally, such as Figure 19 As shown, the shaping unit 513 includes at least one second inverter 5131 connected in series. The input terminal of the at least one second inverter 5131 is connected to the output terminal of the second comparator 512, and the output terminal of the at least one second inverter 5131 is used to output the clock signal CLK.
[0089] It should be noted that as the number of series-connected second inverters 5131 increases, the rising and falling edges of the output clock signal CLK will be closer to the ideal state. For example, the number of series-connected second inverters 5131 can be an integer such as 1, 2, 3, or 4. Figure 19 An example is given of three second inverters 5131 connected in series, wherein the first inverter consists of the twenty-sixth transistor MP19 and the twenty-seventh transistor MN15, the second inverter consists of the twenty-eighth transistor MP20 and the twenty-ninth transistor MN16, and the third inverter consists of the thirtieth transistor MP21 and the thirty-first transistor MN17.
[0090] Optionally, such as Figure 20 As shown, the counting submodule 52 includes a frequency divider unit 521, an inverting unit 522, and an output unit 523. The frequency divider unit 521 is connected to the comparison submodule 51 and is used to divide the clock signal CLK. The inverting unit 522 is connected to the frequency divider unit 521 and is used to invert the frequency-divided clock signal CLK. The output unit 523 is connected to the inverting unit 522 and is used to generate a first control signal SP1 based on the frequency-divided and inverted clock signal CLK.
[0091] It should be noted that the frequency divider unit 521 can divide the clock signal CLK by at least one level.
[0092] Optionally, such as Figure 21As shown, the frequency divider unit 521 includes at least one cascaded first flip-flop. The data input terminal of each first flip-flop is connected to the inverted output terminal of each first flip-flop. The reset terminal of each first flip-flop is connected to the enable signal EN. The clock terminal of the first stage of the first flip-flop in the at least one first flip-flop is connected to the clock signal CLK. The non-inverted output terminal of the last stage of the first flip-flop in the at least one first flip-flop is connected to the input terminal of the inverting unit 522. The non-inverted output terminal of the first flip-flop of the previous stage is connected to the clock terminal of the first flip-flop of the next stage.
[0093] It should be noted that this connection relationship of each first flip-flop can achieve at least one stage of frequency division of the clock signal CLK. If the number of cascaded first flip-flops is n, then the duration of the oscillation phase is 2. n One cycle.
[0094] in, Figure 21 The frequency divider unit 521 in the example includes four cascaded first flip-flops, namely Q_D1, Q_D2, Q_D3, and Q_D4. Reset is used to represent the reset terminal, Clk is used to represent the clock terminal, D is used to represent the data input terminal, Q is used to represent the non-inverting output terminal, and Q is used to represent the inverting output terminal.
[0095] Optionally, such as Figure 22 As shown, the inverter unit 522 includes a third inverter INV3. The input terminal of the third inverter INV3 is connected to the output terminal of the frequency divider unit 521, and the output terminal of the third inverter INV3 is connected to the output unit 523. The output unit 523 includes a second flip-flop. The clock terminal of the second flip-flop is connected to the output terminal of the third inverter INV3. The reset terminal of the second flip-flop is connected to the clock signal CLK, the data input terminal of the second flip-flop is connected to a high-level signal, and the non-inverting output terminal of the second flip-flop is used to output the first control signal SP1.
[0096] It should be noted that TieH is used to represent a high-level signal.
[0097] Figure 23 A timing diagram of the timing control module 50 is shown. Q_D1 represents the waveform of the non-inverting output of the first flip-flop, Q_D2 represents the waveform of the non-inverting output of the second flip-flop, Q_D3 represents the waveform of the non-inverting output of the third flip-flop, Q_D4 represents the waveform of the non-inverting output of the fourth flip-flop, and INV3 represents the output waveform of the third inverter INV3.
[0098] Q_D1, Q_D2, Q_D3, and Q_D4 are respectively the frequency dividers of the clock signal CLK by 2, 4, 8, and 16. INV3 is the waveform after inverting Q_D4. Before the rising edge of INV3 arrives, the first control signal SP1 remains low and the second control signal SN1 remains high. After the rising edge of INV3 arrives, the non-inverting output of the second flip-flop outputs a high-level TieH as the output signal, the first control signal SP1 remains high, and the second control signal SN1 remains low. In this way, the oscillation start-up stage and the stabilization stage can be identified by the first control signal SP1 and the second control signal SN1, and the state of the corresponding transmission gate can be controlled during the oscillation start-up stage and the stabilization stage, thereby realizing the rapid oscillation start-up and low power consumption of the oscillation circuit 100.
[0099] This application embodiment also provides a chip 200, such as Figure 24 As shown, the chip 200 includes the aforementioned oscillation circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.
[0100] It is understood that since the chip 200 provided in this application embodiment includes the above-mentioned oscillation circuit 100, it can also be connected to the self-biased reference module 20 through the current adjustment module 30. It can control the reference current generated by the self-biased reference module 20 in the oscillation start-up stage to be greater than the reference current generated by the self-biased reference module 20 in the stabilization stage, thereby improving the oscillation start-up speed of the crystal oscillator in the oscillation start-up stage and reducing the oscillation maintenance power consumption in the stabilization stage.
[0101] This application also provides an electronic device 300, such as... Figure 25As shown, the electronic device 300 includes a device body and the aforementioned oscillation circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.
[0102] It is understood that since the electronic device 300 provided in this application embodiment includes the above-mentioned oscillation circuit 100 or chip 200, it can also be connected to the self-biased reference module 20 through the current adjustment module 30. It can control the reference current generated by the self-biased reference module 20 in the oscillation start-up stage to be greater than the reference current generated by the self-biased reference module 20 in the stabilization stage, thereby increasing the oscillation start-up speed of the crystal oscillator in the oscillation start-up stage and reducing the oscillation maintenance power consumption in the stabilization stage.
[0103] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. An oscillation circuit, characterized in that, The oscillation circuit includes: A self-biased reference module is used to generate a reference current; A current adjustment module is connected to the self-biased reference module, and the current adjustment module is used to control the reference current in the oscillation stage to be greater than the reference current in the steady stage. A crystal oscillator driving module is connected to the self-biased reference module, and the crystal oscillator driving module is used to mirror the crystal oscillator driving current according to the reference current.
2. The oscillation circuit as described in claim 1, characterized in that, The current adjustment module includes: An impedance unit is connected between the self-biased reference module and the ground terminal; A switching unit is connected in parallel with the impedance unit. The switching unit is in a conducting state during the oscillation start-up phase and in a disconnected state during the stabilization phase.
3. The oscillation circuit as described in claim 2, characterized in that, The impedance unit includes a first resistor, one end of which is connected to the self-biased reference module, and the other end of which is connected to the ground terminal. The switching unit includes a first transmission gate, a first end of the first transmission gate is connected to one end of the first resistor, a second end of the first transmission gate is connected to the other end of the first resistor, a third end of the first transmission gate is connected to a first control signal, and a fourth end of the first transmission gate is connected to a second control signal.
4. The oscillation circuit as described in claim 3, characterized in that, The self-biased reference module includes: The first transistor has its first terminal connected to a first power supply terminal, and its control terminal connected to the crystal oscillator driving module. The second transistor has its first terminal connected to the control terminal of the second transistor and the second terminal of the first transistor, and its second terminal connected to the ground terminal. The third transistor has its first terminal connected to the first terminal of the first transistor, and its second terminal connected to the control terminal of the third transistor and the crystal oscillator driving module. The fourth transistor has its first terminal connected to the second terminal of the third transistor and the crystal oscillator driving module, its control terminal connected to the control terminal of the second transistor, and its second terminal connected to one end of the first resistor and the first end of the first transmission gate. The second resistor has one end connected to the second terminal of the fourth transistor, and the other end connected to one end of the first resistor and the first end of the first transmission gate.
5. The oscillation circuit as described in claim 4, characterized in that, The crystal oscillator driving module includes a crystal oscillator driving unit and a current adjustment unit. The crystal oscillator driving unit is connected to the current adjustment unit and the self-biased reference module. The current adjustment unit is used to increase the crystal oscillator driving current during the oscillation start-up phase and not change the crystal oscillator driving current during the stabilization phase.
6. The oscillation circuit as described in claim 5, characterized in that, The crystal oscillator driving unit includes: The fifth transistor has its first terminal connected to the first power supply terminal, and its control terminal connected to the control terminal of the third transistor. The sixth transistor has its first terminal connected to the second terminal of the fifth transistor, the first terminal of the crystal oscillator, the first terminal of the third resistor, and one terminal of the second capacitor. The control terminal of the sixth transistor is connected to the second terminal of the crystal oscillator, one terminal of the first capacitor, and the second terminal of the third resistor. The second terminal of the sixth transistor is connected to the other terminal of the first capacitor, the other terminal of the second capacitor, and the ground terminal.
7. The oscillation circuit as described in claim 6, characterized in that, The current adjustment unit includes: A first mirror component is connected to the control electrode and the first power supply terminal of the fifth transistor. The first mirror component is used to selectively mirror the crystal oscillator drive current. A switching assembly, wherein the switching assembly is connected between the first mirror assembly and the first terminal of the crystal oscillator; The second mirror component is connected to the control electrode of the sixth transistor, the first mirror component, and the ground terminal.
8. The oscillation circuit as described in claim 7, characterized in that, The first image component includes: The second transmission gate has its first end connected to the control electrode of the fifth transistor, its second end connected to the first control signal, and its third end connected to the second control signal. The seventh transistor has its control electrode connected to the fourth terminal of the second transmission gate, its first electrode connected to the first power supply terminal, and its second electrode connected to the switching assembly.
9. The oscillation circuit as described in claim 8, characterized in that, The switching assembly includes a third transmission gate, the first end of which is connected to the second terminal of the seventh transistor, the second end of which is connected to the first control signal, the third end of which is connected to the second control signal, and the fourth end of which is connected to the first terminal of the crystal oscillator.
10. The oscillation circuit as described in claim 9, characterized in that, The second mirror component includes: The fourth transmission gate has its first end connected to the control electrode of the sixth transistor, its second end connected to the first control signal, and its third end connected to the second control signal. The eighth transistor has its control electrode connected to the fourth terminal of the fourth transmission gate, its first electrode connected to the first terminal of the third transmission gate and the second electrode of the seventh transistor, and its second electrode connected to the ground terminal.
11. The oscillation circuit according to any one of claims 1 to 10, characterized in that, The oscillation circuit further includes a timing control module, which is connected to the crystal oscillator driving module and the current adjustment module. The timing control module is used to generate a first control signal and a second control signal to characterize the oscillation start-up stage and the stable stage based on the potentials at both ends of the crystal oscillator in the crystal oscillator driving module.
12. The oscillation circuit as described in claim 11, characterized in that, The timing control module includes: A comparator submodule, which is connected to the crystal oscillator, is used to generate a clock signal based on the potentials at both ends of the crystal oscillator. A counting submodule, which is connected to the comparison submodule and the current adjustment module, is used to generate the first control signal based on the counting result of the clock signal; A first inverting module is connected to the counting submodule and the current adjustment module. The first inverting module is used to generate a second control signal that is inverted from the first control signal.
13. The oscillation circuit as described in claim 12, characterized in that, The comparison submodule includes: A first comparator is connected to the crystal oscillator and is used to generate a first pair of differential amplified signals based on the differential amplification result of the potentials at both ends of the crystal oscillator. A second comparator is connected to the first comparator and is used to generate the clock signal based on the first pair of differential amplified signals.
14. The oscillation circuit as described in claim 13, characterized in that, The first comparator is connected to a first power supply terminal, and the second comparator is connected to a second power supply terminal. The voltage at the first power supply terminal is higher than the voltage at the second power supply terminal.
15. The oscillation circuit as described in claim 13, characterized in that, The comparison submodule further includes a shaping unit, which is connected to the second comparator and is used to generate the clock signal based on the output signal of the second comparator.
16. The oscillation circuit as described in claim 15, characterized in that, The shaping unit includes at least one second inverter connected in series. The input of the at least one second inverter is connected to the output of the second comparator, and the output of the at least one second inverter is used to output the clock signal.
17. The oscillation circuit as described in claim 12, characterized in that, The counting submodule includes: A frequency division unit is connected to the comparison submodule, and the frequency division unit is used to divide the clock signal. An inverting unit is connected to the frequency divider unit, and the inverting unit is used to invert the frequency-divided clock signal; An output unit is connected to the inverting unit and is used to generate the first control signal based on the clock signal after frequency division and inversion.
18. The oscillation circuit as described in claim 17, characterized in that, The frequency division unit includes at least one cascaded first flip-flop. The data input terminal of each first flip-flop is connected to the inverted output terminal of each first flip-flop. The reset terminal of each first flip-flop is connected to an enable signal. The clock terminal of the first stage of the at least one first flip-flop is connected to the clock signal. The non-inverted output terminal of the last stage of the at least one first flip-flop is connected to the input terminal of the inverting unit. The non-inverted output terminal of the first stage of the previous stage is connected to the clock terminal of the first stage of the next stage.
19. The oscillation circuit as described in claim 17, characterized in that, The inverting unit includes a third inverter, the input terminal of which is connected to the output terminal of the frequency divider unit, and the output terminal of which is connected to the output unit. The output unit includes a second flip-flop, the clock terminal of which is connected to the output terminal of the third inverter, the reset terminal of which is connected to a clock signal, the data input terminal of which is connected to a high-level signal, and the non-inverting output terminal of which is used to output the first control signal.
20. A chip, characterized in that, The chip includes an oscillation circuit as described in any one of claims 1 to 19.
21. An electronic device, characterized in that, The electronic device includes a device body and an oscillation circuit as described in any one of claims 1 to 20 or a chip as described in claim 20 disposed in the device body.