Program-controlled hard reset circuit

Abstract

The utility model discloses a program control hard reset circuit which comprises an LDO chip U1, a pin Vi of the LDO chip U1 is respectively connected with one end of a resistor R2, one end of a capacitor C1 and a charging interface, a pin CE of the LDO chip U1 is respectively connected with the other end of the resistor R2 and a collector electrode of a triode Q1, and a base electrode of the triode Q1 is respectively connected with one end of a resistor R3, one end of a resistor R6 and an electronic product MCU through a resistor R4. The other end of the resistor R3 is connected with the other end of the capacitor C1, the other end of the resistor R6, an emitting electrode of the triode Q1 and a pin G of the LDO chip U1 are respectively grounded, a pin Vo of the LDO chip U1 is connected with an electronic product MCU and outputs a power supply VCC to supply power, and whether the electronic product needs to be subjected to hardware reset or not when the electronic product is inserted into a USB charging line to be charged is determined according to the input or output state of an IO port CRTRST of the electronic product MCU. The stability of the product is enhanced, and the user experience is not affected.

Description

[Technical Field]

[0001] This utility model relates to a programmable hard reset circuit. [Background Technology]

[0002] In existing electronic devices, especially electronic scales, there is a problem where the hardware resets after the user plugs in the charging cable, requiring the user to weigh the item again, which greatly affects the user experience. [Utility Model Content]

[0003] This invention overcomes the shortcomings of the prior art and provides a programmable hard reset circuit.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A programmable hard reset circuit is characterized by: including an LDO chip U1, wherein pin Vi of LDO chip U1 is connected to one end of resistor R2, one end of capacitor C1 and charging interface (1) respectively, pin CE of LDO chip U1 is connected to the other end of resistor R2 and collector of transistor Q1 respectively, base of transistor Q1 is connected to one end of resistor R3, one end of resistor R6 and MCU of electronic product through resistor R4 respectively, the other end of resistor R3 is connected to the other end of capacitor C1, the other end of resistor R6, emitter of transistor Q1 and pin G of LDO chip U1 are grounded respectively, and pin Vo of LDO chip U1 is connected to the MCU of electronic product to output power supply VCC.

[0006] The programmable hard reset circuit described above is characterized in that: the Vo pin of the LDO chip U1 is connected to one end of capacitor C4 and one end of capacitor C5, and the other ends of capacitor C4 and capacitor C5 are respectively grounded.

[0007] The programmable hard reset circuit described above is characterized in that: it further includes a MOS transistor M1, the source terminal of the MOS transistor M1 is connected to the negative terminal of the diode D1, the positive terminal of the diode D1 is connected to the charging interface (1), the gate terminal of the MOS transistor M1 is connected to one end of the resistor R1 and one end of the resistor R5 respectively, the other end of the resistor R1 is connected to the charging interface (1), the other end of the resistor R5 is grounded, the drain terminal of the MOS transistor M1 is connected to pin 2 of the connection terminal CN1, pin 1 of the connection terminal CN1 is grounded, the connection terminal CN1 is connected to the rechargeable battery, and the positive terminal of the rechargeable battery is connected to pin 2 of the connection terminal CN1, and the negative terminal of the rechargeable battery is connected to pin 1 of the connection terminal CN1.

[0008] The programmable hard reset circuit described above is characterized in that: capacitors C2 and C3 are connected in parallel between pin 1 and pin 2 of the connection terminal CN1.

[0009] The programmable hard reset circuit described above is characterized in that: the charging interface (1) is a USB charging interface (1).

[0010] The programmable hard reset circuit described above is characterized in that: the USB charging interface (1) inputs a +5V power supply.

[0011] The programmable hard reset circuit described above is characterized in that: transistor Q1 is an NPN transistor.

[0012] The programmable hard reset circuit described above is characterized in that: MOS transistor M1 is a PMOS transistor.

[0013] The beneficial effects of this utility model are:

[0014] This invention determines whether an electronic product needs a hardware reset when it is plugged into a USB charging cable by using the input or output state of the MCU's CRT_RST port. This enhances product stability without affecting the user experience. [Image Description]

[0015] Figure 1 This is the circuit diagram of this utility model. [Detailed Implementation]

[0016] The technical solutions in the embodiments of this utility model will now be clearly and completely described in conjunction with the accompanying drawings.

[0017] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this utility model are only used to explain the relative positional relationship and movement of the components in a specific posture (as shown in the attached figure). If the specific posture changes, the directional indication will also change accordingly. Furthermore, descriptions involving "preferred," "second-best," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "preferred" or "second-best" may explicitly or implicitly include at least one of those features.

[0018] like Figure 1As shown, a programmable hard reset circuit includes an LDO chip U1. Pin Vi of the LDO chip U1 is connected to one end of resistor R2, one end of capacitor C1, and charging interface 1, respectively. Pin CE of the LDO chip U1 is connected to the other end of resistor R2 and the collector of transistor Q1, respectively. The base of transistor Q1 is connected to one end of resistor R3, one end of resistor R6, and the MCU of an electronic product via resistor R4, respectively. The other end of resistor R3 is connected to the other end of capacitor C1. The other end of resistor R6, the emitter of transistor Q1, and pin G of the LDO chip U1 are grounded, respectively. Pin Vo of the LDO chip U1 is connected to the MCU of the electronic product to output power supply VCC. Among them, charging interface 1 is USB charging interface 1; USB charging interface 1 inputs +5V power supply; CRT_RST is an IO port of MCU; power supply VCC is the output voltage of the output pin Vo of LDO chip U1, power supply VCC supplies power to MCU and other peripheral devices, resistor R2 is the pull-up resistor of the enable pin CE of LDO chip U1; transistor Q1 is NPN transistor; C1 is +5V charging DC blocking and AC passing capacitor.

[0019] like Figure 1 As shown, when the electronic product is powered on, the MCU control IO port CTR_RST is at a low level. When the user inserts a USB charging cable into charging interface 1 to charge the product, the base of transistor Q1 is kept at a low level. At this time, transistor Q1 is not turned on, the enable pin CE of LDO chip U1 is at a high level, and the output pin Vo of LDO chip U1 outputs power supply VCC to power the MCU of the electronic product. At this time, the product will not be hardware reset.

[0020] When the electronic product is powered off, the MCU control I / O port CTR_RST is in a high-impedance state. When the user plugs in a USB cable to charge the product, the +5V power input from the USB charging cable charges capacitor C1. Current flows through capacitor C1, resistor R3, and resistor R6 to form a circuit. At this time, the CTR_RST voltage becomes high, turning on transistor Q1. The enable pin CE of LDO chip U1 is low, and the output pin Vo of LDO chip U1 has no output, causing the MCU and other peripheral devices to lose power. When capacitor C1 is fully charged, no current flows through resistors R3 and R6, and the CTR_RST voltage becomes low. At this time, transistor Q1 does not conduct, the enable pin CE of LDO chip U1 is high, and the output pin Vo of LDO chip U1 outputs power VCC, causing the product to be hardware reset.

[0021] like Figure 1 As shown, pin Vo of LDO chip U1 is connected to one end of capacitor C4 and one end of capacitor C5. The other ends of capacitor C4 and capacitor C5 are grounded respectively. Capacitors C4 and C5 are the filter energy storage capacitors output by LDO chip U1, realizing the filtering function.

[0022] like Figure 1 As shown, the device also includes a MOSFET M1. The source of MOSFET M1 is connected to the negative terminal of diode D1, and the positive terminal of diode D1 is connected to charging interface 1. The gate of MOSFET M1 is connected to one end of resistor R1 and one end of resistor R5. The other end of resistor R1 is connected to charging interface 1, and the other end of resistor R5 is grounded. The drain of MOSFET M1 is connected to pin 2 of connection terminal CN1, and pin 1 of connection terminal CN1 is grounded. Connection terminal CN1 is connected to a rechargeable battery, with the positive terminal of the rechargeable battery connected to pin 2 of connection terminal CN1 and the negative terminal of the rechargeable battery connected to pin 1 of connection terminal CN1. MOSFET M1 is a PMOS transistor. When the user inserts a USB charging cable into charging interface 1 to charge the product, MOSFET M1 conducts, enabling charging of the rechargeable battery connected to connection terminal CN1.

[0023] like Figure 1 As shown, capacitors C2 and C3 are connected in parallel between pin 1 and pin 2 of terminal CN1. Capacitors C2 and C3 are the filter energy storage capacitors of the rechargeable battery, which realize the filtering function.

[0024] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural transformations made based on the inventive concept of this utility model and the contents of this utility model specification and drawings, or direct or indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A programmable hard reset circuit, characterized in that: It includes an LDO chip U1. The pin Vi of the LDO chip U1 is connected to one end of resistor R2, one end of capacitor C1 and charging interface (1) respectively. The pin CE of the LDO chip U1 is connected to the other end of resistor R2 and the collector of transistor Q1 respectively. The base of transistor Q1 is connected to one end of resistor R3, one end of resistor R6 and MCU of electronic product through resistor R4 respectively. The other end of resistor R3 is connected to the other end of capacitor C1. The other end of resistor R6, the emitter of transistor Q1 and pin G of LDO chip U1 are grounded respectively. The pin Vo of LDO chip U1 is connected to the MCU of electronic product to output power supply VCC.

2. The programmable hard reset circuit according to claim 1, characterized in that: The Vo pin of the LDO chip U1 is connected to one end of capacitor C4 and one end of capacitor C5, while the other ends of capacitor C4 and capacitor C5 are grounded respectively.

3. The programmable hard reset circuit according to claim 1, characterized in that: It also includes a MOS transistor M1, the source of which is connected to the negative terminal of diode D1, the positive terminal of diode D1 is connected to the charging interface (1), the gate of MOS transistor M1 is connected to one end of resistor R1 and one end of resistor R5 respectively, the other end of resistor R1 is connected to the charging interface (1), the other end of resistor R5 is grounded, the drain of MOS transistor M1 is connected to pin 2 of connection terminal CN1, pin 1 of connection terminal CN1 is grounded, connection terminal CN1 is connected to the rechargeable battery, and the positive terminal of the rechargeable battery is connected to pin 2 of connection terminal CN1, and the negative terminal of the rechargeable battery is connected to pin 1 of connection terminal CN1.

4. A programmable hard reset circuit according to claim 3, characterized in that: Capacitors C2 and C3 are connected in parallel between pin 1 and pin 2 of terminal CN1.

5. A programmable hard reset circuit according to claim 1 or 3, characterized in that: The charging port (1) is a USB charging port (1).

6. A programmable hard reset circuit according to claim 5, characterized in that: USB charging port (1) Input +5V power.

7. A programmable hard reset circuit according to claim 1, characterized in that: Transistor Q1 is an NPN transistor.

8. A programmable hard reset circuit according to claim 3, characterized in that: MOSFET M1 is a PMOS transistor.

Images