Package and package structure

Abstract

The utility model provides a packaging structure, comprising a first crystal grain and a second crystal grain which are embedded in a first insulating material; a first redistribution structure on the first die and the second die; a second molding material on portions of the first die and the second die, where the second molding material is between the first portion and the second portion of the first redistribution structure; a first via extending through the second molding material, where the first via is electrically connected to the first die; a second via extending through the second molding material, where the second via is electrically connected to the second die; and a silicon bridge electrically coupled to the first via and the second via.

Description

Technical Field

[0001] This utility model relates to packaging structures, and more particularly to silicon bridges. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, and the like. These improvements in integration density primarily stem from the continuous shrinking of minimum structural dimensions to integrate more components into a given area. The growing demand for smaller electronic devices creates a need for smaller and more innovative semiconductor die packaging technologies. Utility Model Content

[0003] In one embodiment, the package includes a first die and a second die embedded in a first molding material; a first redistribution structure located on the first die and the second die; a second molding material located on portions of the first die and the second die, wherein the second molding material is located between a first portion and a second portion of the first redistribution structure; a first via extending through the second molding material, wherein the first via is electrically connected to the first die; a second via extending through the second molding material, wherein the second via is electrically connected to the second die; and a silicon bridge electrically coupled to the first via and the second via.

[0004] In one embodiment, the first through-hole physically contacts a first grain connector of the first grain, and the second through-hole physically contacts a second grain connector of the second grain.

[0005] In one embodiment, the second molding material is in physical contact with the first grain and the second grain.

[0006] In one embodiment, a third portion of the first rewiring structure is located between the second molding material and the first and second grains.

[0007] In one embodiment, the first via physically contacts a first conductive pad in a third portion of the first rewiring structure, and the second via physically contacts a second conductive pad in the third portion of the first rewiring structure. In another embodiment, the package structure includes a first die and a second die embedded in a first insulating material; a first rewiring structure located on the first die and the second die, and the first rewiring structure includes a dielectric layer; a first conductive pad physically contacts a first die connector of the first die; a second conductive pad physically contacts a second die connector of the second die; a second insulating material extending partially through the first rewiring structure, wherein the material of the second insulating material is different from the material of the dielectric layer; a first via extending through the second insulating material to physically contact the first conductive pad; and a second via extending through the second insulating material to physically contact the second conductive pad.

[0008] In one embodiment, the package structure further includes a silicon bridge coupled to the first via and the second via, wherein the first die is electrically connected to the second die via the silicon bridge.

[0009] In one embodiment, the packaging structure further includes: a packaging member electrically coupled to the first rewiring structure, wherein the first rewiring structure is located between the packaging member and the silicon bridge.

[0010] In one embodiment, the first width of the silicon bridge in a direction parallel to the upper surface of the second insulating material is less than or equal to the minimum width of the second insulating material from the first outermost sidewall to the second outermost sidewall.

[0011] In one embodiment, the packaging structure further includes: a packaging substrate coupled to the first rewiring structure, wherein the first rewiring structure is located between the packaging substrate and the first die.

[0012] The embodiments of this disclosure described above have at least the following advantages or beneficial effects:

[0013] The advantages of one or more embodiments disclosed herein include a reduction in the length of the in-line interconnects between the first integrated circuit die and the second integrated circuit die. Furthermore, the first and second through-insulator vias may include larger diameters, which can reduce resistance and improve electrical performance. Additionally, the molding material formed around the first and second through-insulator vias can provide high rigidity, which can prevent breakage in the molding material and improve the reliability of the integrated circuit package. Attached Figure Description

[0014] Figure 1 These are cross-sectional views of an integrated circuit die in some embodiments.

[0015] Figures 2 to 16 These are cross-sectional views of intermediate steps in the process of forming the package, as described in some embodiments.

[0016] Figure 17 This is a cross-sectional view of an intermediate step in the process of forming the package, as described in other embodiments.

[0017] The annotations in the attached figures are explained as follows:

[0018] α1: Angle

[0019] D1, D2: Diameter

[0020] H1: Height

[0021] W1, W2: Width

[0022] 15: Cutting line

[0023] 50: Integrated circuit die

[0024] 52: Semiconductor substrate

[0025] 54: Device

[0026] 56: Interlayer dielectric layer

[0027] 58: Conductive plug

[0028] 60: Internal Wiring Structure

[0029] 62: solder pads

[0030] 64: Passivation film

[0031] 66: Grain Connectors

[0032] 68,124,130,134,138,142: Dielectric layer

[0033] 100: First encapsulation component

[0034] 102: Carrier board

[0035] 104: Release layer

[0036] 110, 110A, 110B, 110C, 111: Package

[0037] 116: Seed crystal layer

[0038] 119: Adhesive

[0039] 120, 146, 208: Conductive vias

[0040] 120A: First through hole

[0041] 120B: Second through hole

[0042] 122: Front Rewiring Structure

[0043] 126, 150, 156: Conductive pads

[0044] 128, 148, 214: Molding materials

[0045] 132, 136, 140, 147: Metallized patterns

[0046] 143, 145: Opening

[0047] 144: Masking layer

[0048] 152, 154, 164: Conductive connectors

[0049] 158: Silicon Bridge

[0050] 160,216: Subbase layer

[0051] 200: Second encapsulation component

[0052] 202:Substrate

[0053] 204, 206, 304: Bonding pads

[0054] 210A, 210B: Stacked grains

[0055] 212: Wiring Connection

[0056] 300: Packaging substrate

[0057] 302: Substrate core

[0058] 306: Solder resist layer. Detailed Implementation

[0059] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0060] The following disclosure provides many different embodiments or examples to implement different structures of the present invention. The specific components and arrangements described below are intended to simplify the present invention and not to limit it. For example, a description of a first component forming on a second component includes direct contact between the two, or the two being separated by other additional components rather than in direct contact. Furthermore, multiple embodiments of the present invention may use repeated reference numerals and / or symbols to simplify and clarify the description, but these repetitions do not represent the same correspondence between elements with the same reference numerals in multiple embodiments.

[0061] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0062] Various embodiments provide methods for forming an integrated circuit package, including a front redistribution structure on a first integrated circuit die and a second integrated circuit die. A portion of the front redistribution structure is removed to form an opening in the front redistribution structure, and a first through-insulator (BII) via and a second through-insulator (BII) via are formed in the opening, wherein the first BII via is electrically connected to the first integrated circuit die, and the second BII via is electrically connected to the second integrated circuit die. A molding material is formed around the first BII via and the second BII via in the opening, and a silicon bridge is formed on and coupled to the first BII via and the second BII via. An advantage of one or more embodiments disclosed herein is that it can reduce the length of the in-line interconnects between the first integrated circuit die and the second integrated circuit die. Furthermore, the first BII via and the second BII via may include a larger diameter, which can reduce resistance and improve electrical performance. Furthermore, the molding material formed around the first and second through-insulator vias provides high rigidity, which can prevent breakage in the molding material and improve the reliability of integrated circuit packaging.

[0063] Figure 1 These are cross-sectional views of integrated circuit die 50 in some embodiments. Subsequent processes may package the integrated circuit die 50 to form an integrated circuit package. The integrated circuit die 50 may be a logic die (such as a central processing unit, single-chip system, application processor, microcontroller, or the like), a memory die (such as a dynamic random access memory die, a static random access memory die, or the like), a power management die (such as a power management integrated circuit die), a radio frequency die, a baseband transceiver die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (such as a digital signal processing die), a front-end die (such as an analog front-end die), a high-performance computing die, an artificial intelligence die, an automotive die, the like, or a combination thereof.

[0064] Integrated circuit dies 50 can be formed in a wafer, which may include different device regions, and subsequent steps may cleave the device regions to form multiple integrated circuit dies. Integrated circuit dies 50 can be processed according to feasible manufacturing processes to form integrated circuits. For example, integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer on a semiconductor substrate over an insulating layer. The semiconductor substrate 52 may include other semiconductor materials (such as germanium), semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium), or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. The semiconductor substrate 52 has an active surface (such as... Figure 1 The surface facing upwards (sometimes considered the front side) and the non-active surface (such as...) Figure 1 The surface facing downwards is sometimes considered as the dorsal side.

[0065] Device 54 (transistor in the figures) may be formed on the front surface of semiconductor substrate 52. Device 54 may be an active device (such as a transistor, diode, or the like), capacitor, resistor, or the like. Interlayer dielectric layer 56 is located on the front surface of semiconductor substrate 52. Interlayer dielectric layer 56 may surround and cover device 54. Interlayer dielectric layer 56 may include one or more dielectric layers, and its composition may be phosphosilicate glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like.

[0066] A conductive plug 58 extends through the interlayer dielectric layer 56 to electrically and physically couple device 54. For example, when device 54 is a transistor, the conductive plug 58 can couple the gate and source / drain regions of the transistor. The conductive plug 58 may be composed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure 60 is located on the interlayer dielectric layer 56 and the conductive plug 58. The interconnect structure 60 can interconnect device 54 to form an integrated circuit. For example, the interconnect structure 60 may be formed by forming a metallization pattern in the dielectric layer on the interlayer dielectric layer 56. The metallization pattern includes metal lines and vias formed in one or more low-dielectric-constant dielectric layers. The metallization pattern of the interconnect structure 60 can be electrically coupled to device 54 via the conductive plug 58.

[0067] The integrated circuit die 50 also includes pads 62, such as aluminum pads, for connection to external interconnects. The pads 62 are located on the active side of the integrated circuit die 50, for example, within and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, for example, on portions of the interconnect structure 60 and the pads 62. Openings extend through the passivation films 64 to the pads 62. Die interconnects 66, such as conductive pillars (which may be composed of metals such as copper), may extend through the openings in the passivation films 64 and be physically and electrically coupled to individual pads 62. For example, the die interconnects 66 may be formed by electroplating or similar methods. The die interconnects 66 may electrically couple to individual integrated circuits of the integrated circuit die 50.

[0068] Solder areas (such as solder balls or solder bumps) may be located on pad 62, depending on the situation. Solder balls can be used for chip probe testing on integrated circuit die 50 to confirm whether integrated circuit die 50 is a known good die. Therefore, only integrated circuit dies 50 that are known good dies are processed and packaged, while dies that fail the chip probe test are not packaged. The solder areas can be removed in subsequent process steps after testing.

[0069] The dielectric layer 68 may or may not be located on the active side of the integrated circuit die 50, for example, it may be located on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally seals the die connector 66 and is laterally adjacent to the integrated circuit die 50. The die connector 66 may initially be embedded in the dielectric layer 68, i.e., the top surface of the dielectric layer 68 may be higher than the top surface of the die connector 66. In some embodiments, solder regions are located on the die connector 66, and the dielectric layer 68 may also embed solder regions. In other embodiments, solder regions may be removed before the dielectric layer 68 is formed.

[0070] The dielectric layer 68 may be a polymer (such as polybenzoxazole, polyimide, benzocyclobutene, or the like), a nitride (such as silicon nitride or the like), an oxide (such as silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, or the like), the like, or a combination thereof. For example, the dielectric layer 68 may be formed by spin coating, lamination, chemical vapor deposition, or similar methods. In some embodiments, the die connector 66 may be exposed from the dielectric layer 68 during the formation of the integrated circuit die 50. In some embodiments, the die connector 66 may be buried and exposed during subsequent processes for packaging the integrated circuit die 50. The method for exposing the die connector 66 may be to remove any solder areas present on the die connector 66.

[0071] Figures 2 to 14 This is a cross-sectional view of an intermediate step in the process of forming the first package component 100 in some embodiments. One or more integrated circuit dies 50 are packaged to form an integrated circuit package, which can also be viewed as an integrated fan-out package.

[0072] exist Figure 2 In this process, a carrier plate 102 is provided, and a release layer 104 is formed on the carrier plate 102. The carrier plate 102 may be a glass carrier plate, a ceramic carrier plate, or the like. The carrier plate 102 may be a wafer, and multiple packages may be formed on the carrier plate 102 simultaneously.

[0073] Release layer 104 may be composed of a polymer-based material and may be removed together with the carrier plate 102 formed in subsequent steps. In some embodiments, release layer 104 is an epoxy-based heat release material that loses its adhesive properties upon heating, such as a photothermal conversion release coating. In other embodiments, release layer 104 may be a UV adhesive that loses its adhesive properties upon exposure to UV light. Liquid release layer 104 may be applied and then cured. Release layer 104 may also be a laminated film pressed onto carrier plate 102, or other similar materials. The upper surface of release layer 104 may be flush and may have high flatness.

[0074] exist Figure 3In this configuration, the conductive via 120 extends away from the upper surface of the release layer 104. For example, the method of forming the conductive via 120 may involve forming a seed layer 116 on the release layer 104. In some embodiments, the seed layer 116 is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers of different materials. In a specific embodiment, the seed layer 116 includes a titanium layer and a copper layer on top of the titanium layer. For example, the seed layer 116 may be formed using physical vapor deposition or similar methods. A patterned photoresist may be formed on the seed layer 116. The photoresist may be formed by spin coating or similar methods, and then exposed for a patterning process. The photoresist pattern may correspond to the conductive via 120. The patterning process may form openings through the photoresist to expose the seed layer 116. A conductive material is formed on the exposed portion of the seed layer and within the openings in the photoresist. The conductive material can be formed by electroplating (e.g., electroplating or electroless plating) or similar methods. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The photoresist layer and portions of the conductive material not on which the seed layer is formed can be removed. The photoresist layer can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer 116 can be removed, and the removal method can be an acceptable etching process such as wet etching or dry etching. The seed layer 116 and the retained portions of the conductive material form conductive vias 120. In one embodiment, adjacent first sets of conductive vias 120 may form a plurality of first vias 120A, and adjacent second sets of conductive vias 120 may form a plurality of second vias 120B, wherein the plurality of first vias 120A and the plurality of second vias 120B are located in different regions of the carrier plate 102.

[0075] exist Figure 4 In this process, one or more integrated circuit dies 50 are adhered to the release layer 104 using adhesive 119. For example, a pick-and-place process or similar process can be used to adhere the integrated circuit dies 50 to the release layer 104. Although Figure 4Two integrated circuit dies 50 are bonded to release layer 104, but any desired type and number of integrated circuit dies 50 can be bonded to release layer 104. In the illustrated embodiment, the two bonded integrated circuit dies 50 are adjacent to each other and located between a plurality of first vias 120A and a plurality of second vias 120B. The integrated circuit dies 50 may be logic devices such as central processing units, graphics processors, single-chip systems, microcontrollers, memory devices (such as dynamic random access memory dies, static random access memory dies, hybrid memory cube modules, or high-bandwidth memory modules), or the like. In some embodiments, all integrated circuit dies 50 may be dies of the same type, such as single-chip system dies. Integrated circuit dies 50 may be formed in the same technology node process as other integrated circuit dies 50. In other embodiments, integrated circuit dies 50 are each formed in a different technology node process. Integrated circuit dies 50 and other integrated circuit dies 50 may each have different dimensions (e.g., different heights and / or surface areas) or the same dimensions (e.g., the same height and / or surface area).

[0076] Adhesive 119 is located on the back side of the integrated circuit die 50 and adheres the integrated circuit die 50 to the release layer 104. Adhesive 119 can be any suitable adhesive, epoxide, die-attachment film, or the like. Adhesive 119 can be applied to the back side of the integrated circuit die 50 or to the surface of the release layer 104. For example, adhesive 119 can be applied to the back side of the integrated circuit die 50 before the integrated circuit die 50 is cut apart.

[0077] exist Figure 5 In this process, the electrically insulating molding material 128 (or molding compound) can be formed in... Figure 4 The structure shown includes, for example, the conductive via 120 on its upper surface and sidewalls, the integrated circuit die 50 on its upper surface and sidewalls, the adhesive 119 on its sidewalls, and the release layer 104 on its upper surface. Molding material 128 fills the spaces between each conductive via 120, between adjacent integrated circuit dies 50, and between each integrated circuit die 50 and the nearest conductive via 120. Molding material 128 may include dielectric materials such as silicon-based materials, silicon dioxide-containing epoxy molding compounds, or the like, which can provide electrical isolation between each conductive via 120 and other structures of the first package member 100. The molding material 128 can be formed using various forming techniques, such as spin coating, deposition, injection molding, or similar processes.

[0078] exist Figure 6In this process, excess portions of the molding material 128 can be planarized by grinding, chemical mechanical polishing, or similar methods to remove a portion of the molding material 128 and expose the upper surface of the conductive via 120. During planarization, a portion of the dielectric layer 68 of each of the multiple integrated circuit dies 50 can also be removed to expose the upper surface of the die interconnect 66. For example... Figure 6 As shown, the planarization process causes the upper surfaces of the conductive vias 120 and the die connectors 66 to be flush with the upper surface of the molding material 128. The conductive vias 120 can each be electrically connected to the front redistribution structure 122 (e.g., Figure 8 (As shown).

[0079] exist Figure 7 In this process, conductive pads 126 (which can also be considered as metallization patterns) are formed on the integrated circuit die 50, conductive vias 120, and molding material 128. The conductive pads 126 are part of the front redistribution structure 122 (e.g., ...). Figure 8 (As shown). The conductive pad 126 can physically contact and electrically connect to the respective die connector 66 and conductive via 120 of the integrated circuit die 50. To form the conductive pad 126, a seed layer can first be formed on the upper surface of the integrated circuit die 50, the conductive via 120, and the molding material 128. For example, the metal seed layer may include a double layer of titanium and copper (e.g., a copper layer on top of a titanium layer), a single copper layer, or other suitable metal layer, and its deposition method may be physical vapor deposition (e.g., sputtering) or a similar method. The seed layer can have any suitable thickness. Next, a conductive material layer is deposited on the seed layer. The conductive material layer may be copper or the like, and the deposition may be performed using an electroplating process, such as electroplating, electroless plating, dip plating, or a similar process. Then, the seed layer and the conductive material layer can be patterned using acceptable photolithography and etching techniques to remove portions of the seed layer and the conductive material layer. The seed layer and the remaining portion of the conductive material above form the conductive pad 126.

[0080] like Figure 7 As shown, a dielectric layer 124 is formed on the conductive pads 126. The dielectric layer 124 is formed to embed the conductive pads 126 therein. For example, the dielectric layer 124 may be a polymer material layer such as low-temperature polyimide, polybenzoxazole, benzocyclobutene, or other electrically insulating polymer materials. The dielectric layer 124 can be formed using lamination, coating (e.g., spin coating), chemical vapor deposition, or similar methods. In one embodiment, the dielectric layer 124 can be formed using a coating process followed by a curing process. After the dielectric layer 124 is formed, a planarization step such as chemical mechanical polishing can be performed to remove excess portions of the dielectric layer 124 and expose the upper surface of the conductive pads 126. In summary, the upper surface of the dielectric layer 124 may be flush with the upper surface of the conductive pads 126.

[0081] exist Figure 8In this process, the remaining portion of the front-side redistribution structure 122 is formed on the molding material 128, the conductive via 120, and the integrated circuit die 50. The front-side redistribution structure 122 includes dielectric layers 124, 130, 134, 138, and 142, and metallization patterns 132, 136, 140, and 147. The metallization patterns can also be considered as redistribution layers or redistribution lines. A structure larger than... Figure 8 The structure shown has more or fewer dielectric layers and metallization patterns in the front redistribution structure 122. If fewer dielectric layers and metallization patterns are required, the following steps and processes can be omitted. If more dielectric layers and metallization patterns are required, the following steps and processes can be repeated.

[0082] like Figure 8 As shown, dielectric layer 130 is deposited on dielectric layer 124 and conductive pads 126. For example, dielectric layer 130 may be a polymer material layer such as low-temperature polyimide, polybenzoxazole, benzocyclobutene, or other electrically insulating polymer materials. The dielectric layer 130 may be formed using lamination, coating (such as spin coating), chemical vapor deposition, or similar methods. The dielectric layer 130 may then be patterned. The patterning process forms openings to expose portions of the conductive pads 126. For example, the patterning process may be an acceptable process such as etching, which may employ anisotropic etching.

[0083] Next, a metallization pattern 132 is formed. The metallization pattern 132 includes conductive units located on the main surface of the dielectric layer 130 and extending along and through the dielectric layer 130 to be physically and electrically coupled to the conductive pads 126, conductive vias 120, and the integrated circuit die 50. For example, to form the metallization pattern 132, a seed layer may be formed on the dielectric layer 130 and extending through an opening in the dielectric layer 130. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer consisting of multiple sublayers of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located on the titanium layer. For example, the seed layer may be formed using physical vapor deposition or a similar method. Next, a patterned photoresist may be formed on the seed layer. The photoresist may be formed using spin coating or a similar method, and the photoresist may be exposed for patterning. The photoresist pattern corresponds to the metallization pattern 132. A patterning process creates openings through the photoresist to expose the seed layer. A conductive material is then formed within the openings in the photoresist and over the exposed portion of the seed layer. The conductive material can be formed by electroplating (e.g., electroplating or electroless plating) or similar methods. The conductive material can include metals such as copper, titanium, tungsten, aluminum, or the like. The conductive material and the underlying portion of the seed layer form a metallized pattern 132. The photoresist and the portion of the seed layer over which the conductive material is not formed can be removed. The photoresist can be removed using an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer can be removed, for example, using an acceptable etching process such as wet etching or dry etching.

[0084] After forming the metallization pattern 132, a dielectric layer 134 is deposited on the metallization pattern 132 and the dielectric layer 130. The method and material of forming the dielectric layer 134 can be similar to those of forming the dielectric layer 130.

[0085] Next, a metallization pattern 136 is formed. A portion of the metallization pattern 136 is located on and extends along the main surface of the dielectric layer 134. The metallization pattern 136 also includes portions extending through the dielectric layer 134 to physically and electrically couple with a metallization pattern 132. The formation method and materials of the metallization pattern 136 may be similar to those of the metallization pattern 132. In some embodiments, the dimensions of the metallization pattern 136 differ from those of the metallization pattern 132. For example, the conductive lines and / or vias of the metallization pattern 136 may be wider or thicker than the conductive lines and / or vias of the metallization pattern 132. Furthermore, the spacing of the metallization patterns 136 may be greater than the spacing of the metallization patterns 132.

[0086] After forming the metallization pattern 136, a dielectric layer 138 is deposited on the metallization pattern 136 and the dielectric layer 134. The dielectric layer 138 can be formed in a similar manner to the dielectric layers 130 and 134, and the material of the dielectric layer 138 can be similar to the material of the dielectric layers 130 and 134.

[0087] Next, a metallization pattern 140 is formed. A portion of the metallization pattern 140 is located on and extends along the main surface of the dielectric layer 138. The metallization pattern 140 also includes a portion extending through the dielectric layer 138 to physically and electrically couple a metallization pattern 136. The formation method and materials of the metallization pattern 140 can be similar to those used for the formation of metallization patterns 132 and 136.

[0088] After forming the metallization pattern 140, a dielectric layer 142 is deposited on the metallization pattern 140 and the dielectric layer 138. The formation method and material of the dielectric layer 142 can be similar to those of the dielectric layer 138. The dielectric layer 142 is the topmost dielectric layer of the front redistribution structure 122.

[0089] Next, a metallization pattern 147 is formed. A portion of the metallization pattern 147 extends through the dielectric layer 142 to physically and electrically couple with the metallization pattern 140. The formation method and materials of the metallization pattern 147 can be similar to those of the metallization patterns 132, 136, and 140. The metallization pattern 147 is the topmost metallization pattern of the front redistribution structure 122. In this way, all intermediate metallization patterns of the front redistribution structure 122 (such as metallization patterns 132, 136, and 140) are located between the metallization pattern 147 and the integrated circuit die 50. In some embodiments, the dimensions of the metallization pattern 147 are different from the dimensions of the metallization patterns 132, 136, and 140. For example, the conductive lines and / or vias of the metallization pattern 147 may be wider or thicker than the conductive lines and / or vias of the metallization pattern 132. Furthermore, the spacing of the metallization pattern 147 may be greater than the spacing of the metallization pattern 140.

[0090] A front redistribution structure 122 is formed, such that the central area of ​​the front redistribution structure 122 has no metallization pattern. The central area of ​​the front redistribution structure 122 is located on a first conductive pad (126), which is electrically connected to and overlaps with the first die connector 66 of the integrated circuit die 50. The central area of ​​the front redistribution structure 122 is also located on a second conductive pad (126), which is electrically connected to and overlaps with the second die connector 66 of the integrated circuit die 50. The first and second integrated circuit dies 50 are adjacent to each other.

[0091] exist Figure 9 In this process, a masking layer (such as a photoresist) can be formed on the front redistribution structure 122, and then the masking layer can be patterned to expose the upper surface of the front redistribution structure 122. The masking layer can expose the central area of ​​the front redistribution structure 122 without any metal pattern. The masking layer can then be used as an etching mask and a suitable etching process can be performed to form an opening 143 in the front redistribution structure 122. The etching process can be a dry etching process or a wet etching process. The opening 143 exposes a portion of the upper surface of the dielectric layer 124. In addition, the opening 143 exposes the upper surface of the first conductive pad (126) that overlaps with and is electrically connected to the die interconnect 66 of the first integrated circuit die 50. The opening 143 also exposes the upper surface of the second conductive pad (126) that overlaps with and is electrically connected to the die interconnect 66 of the second integrated circuit die 50. The first integrated circuit die 50 can be adjacent to the second integrated circuit die 50. After the opening 143 is formed, the sidewall of the opening 143 can form an angle α1 with the upper surface of the dielectric layer 124, wherein the angle α1 can be 80° to 89°.

[0092] exist Figure 10 In the middle, the masking layer 144 is formed in Figure 9 The structure shown may include, for example, the front redistribution structure 122 and the opening 143. The mask layer 144 may be a photoresist or the like, and its formation may be achieved using spin coating or deposition processes. The mask layer 144 may be patterned using acceptable development and exposure techniques to form the opening 145 (or via), and the conductive via 146 (e.g., Figure 11 As shown, it will be formed therein. The opening 145 exposes the upper surfaces of the first conductive pad (126) and the second conductive pad (126).

[0093] exist Figure 11 In this process, conductive material is formed on the exposed upper surfaces of the first conductive pad (126) and the second conductive pad (126) respectively, to at least partially fill the opening 145 and form a conductive via 146. The conductive material may be a copper layer or other suitable metal, and its formation method may be an electrochemical plating process or a similar process. In the electrochemical plating process, the conductive material may be vertically deposited on the lower surface of the opening 145, so that the conductive via 146 fills the bottom of the opening 145. In this manner, the upper surface of the masking layer 144 is higher than the upper surface of the conductive via 146.

[0094] exist Figure 12Suitable removal processes such as ashing (e.g., ozone plasma ashing) or chemical stripping (e.g., wet acid cleaning) can be employed. Electrically insulating molding material 148 (or molding compound) is formed on the upper surface and sidewalls of the conductive vias 146, and on the upper surface and sidewalls of the front redistribution structure 122. The molding material 148 fills the spaces between adjacent conductive vias 146, and between each conductive via 146 and an adjacent sidewall of the front redistribution structure 122. The molding material 148 can be formed using various techniques, such as spin coating, deposition, injection molding, compression molding, or similar processes. The upper surface of the molding material 148 is higher than the upper surfaces of the conductive vias 146 and the topmost surface of the front redistribution structure 122. The molding material 148 may include dielectric materials such as silicon-based materials, epoxy molding compounds containing silicon oxide fillers, or the like, which can provide electrical isolation between each conductive via 146 and other structures of the first encapsulation member 100. In one embodiment, the molding compound, such as molding material 148, may have a silica filler content of less than 70 wt%. In one embodiment, the silica filler content of molding material 148 differs from that of molding material 128. Having a silica filler content of less than 70 wt% in the molding compound, such as molding material 148, offers several advantages. These advantages include a dielectric constant of 2.8 to 4.2 for molding material 148, which can improve the electrical performance of the first package member 100. Furthermore, the molding material 148 formed around each conductive via 146 provides high rigidity, which can prevent breakage within the molding material 148 and improve the reliability of the integrated circuit package.

[0095] exist Figure 13In this process, excess portions of the molding material 148 and the conductive via 146 can be planarized by grinding, chemical mechanical polishing, or similar methods to remove portions of the molding material 148 and the conductive via 146. After the planarization process, the upper surface of the conductive via 146 can be exposed, which can be flush with the upper surface of the molding material 148 and the front redistribution structure 122. The conductive vias 146 can each be connected to the die connector 66 of the integrated circuit die 50. The molding material 148 can provide electrical isolation between each conductive via 146 and other structures of the first package member 100. In one embodiment, the aspect ratio of each conductive via 146 (e.g., the ratio of the height H1 of the conductive via 146 to the diameter D1 of the conductive via 146) is less than or equal to 10. In one embodiment, the first conductive pad (126) and the second conductive pad (126) may each have a diameter D2, wherein the first conductive pad (126) and the second conductive pad (126) may each be electrically and physically connected to the conductive via 146. In one embodiment, the ratio of diameter D1 to diameter D2 may be less than or equal to 1. A ratio of diameter D1 to diameter D2 of 1, and an aspect ratio (e.g., the ratio of height H1 of the conductive via 146 to diameter D1) of less than 10, achieve these advantages. These advantages include reduced resistance and improved electrical performance.

[0096] exist Figure 14 In this configuration, conductive pads 150 are formed on the front redistribution structure 122, conductive vias 146, and molding material 148. The first conductive pad 150 is physically and electrically connected to the conductive via 146. In this manner, the first conductive pad 150 is also electrically connected to the respective die interconnects 66 of the integrated circuit die 50. Furthermore, the second conductive pad 150 is physically and electrically connected to the front redistribution structure 122 via a metallization pattern 147. To form the conductive pad 150, a seed layer is first formed on the upper surfaces of the front redistribution structure 122, conductive vias 146, and molding material 148. For example, the metal seed layer may include a double layer of titanium and copper (e.g., a copper layer on top of a titanium layer), a single copper layer, or other suitable metal layers, and its deposition method may employ physical vapor deposition (e.g., sputtering) or a similar process. The seed layer may have any suitable thickness. A conductive material layer is then deposited on the seed layer. The conductive material layer can be copper or similar, and its deposition method can employ electroplating processes such as electroplating, electroless plating, immersion plating, or similar processes. Then, acceptable photolithography and etching techniques can be used to pattern the seed layer and the conductive material layer to remove portions of the seed layer and the conductive material layer. The remaining portions of the seed layer and the overlying conductive material layer can form conductive pads 150.

[0097] After the conductive pads 150 are formed, conductive connections 154 may be formed on the first conductive pad 150. The conductive connections 154 may be solder balls, metal pillars, microbumps, or the like. The conductive connections 154 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connections 154 may be formed initially by forming a solder layer via vapor deposition, electroplating, printing, solder transfer, or similar methods. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connections 154 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar methods. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by an electroplating process.

[0098] After the conductive interconnect 154 is formed, the silicon bridge 158 (sometimes considered as a local silicon interconnect) can be coupled to the first of the conductive pads 150. The silicon bridge 158 can provide electrical communication between two adjacent integrated circuit dies 50. In some embodiments, the silicon bridge 158 includes one or more interconnect layers (not shown in the figure). Figure 14 The silicon bridge 158 is located on a semiconductor substrate (such as a silicon substrate). Furthermore, the silicon bridge 158 may include conductive pads 156 formed on its upper surface, wherein the conductive pads 156 are electrically connected to an interconnect layer. The interconnect layer provides electrical communication between two adjacent integrated circuit dies 50. The interconnect layer may include metal lines distributed in multiple layers (the composition of which may be metals such as copper, aluminum, tungsten, or titanium), and metal lines interconnecting different layers via vias. The method of forming one or more interconnect layers may employ the methods used to form interconnect lines in an integrated circuit. In some embodiments, the silicon bridge 158 may not have active devices (such as transistors) and passive devices (such as transistors, resistors, and capacitors). In other embodiments, the silicon bridge 158 includes passive devices but does not include active devices. In other embodiments, the silicon bridge 158 includes both active and passive devices therein.

[0099] To couple the conductive connector 154 to the silicon bridge 158, the conductive connector 154 is allowed to reflow. The conductive connector 154 is electrically and / or physically coupled to the silicon bridge 158 to the first package member 100. In some embodiments, an underfill layer 160 may be formed between the first package member 100 and the silicon bridge 158, and surrounding the conductive connector 154. The underfill layer 160 may be formed by a capillary flow process after bonding the silicon bridge 158, or by a suitable deposition method before bonding the silicon bridge 158. In one embodiment, the minimum width of the molding material 148 from the first outermost sidewall to the second outermost sidewall of the molding material 148 is equal to the width W1. In one embodiment, the width of the silicon bridge 158 in a direction parallel to the upper surface of the molding material 148 is equal to the width W2, and the width W2 is less than or equal to the width W1. In this embodiment, the molding material 148 may be wider than the silicon bridge 158, even at the narrowest point of the molding material 148. The width W2 of the silicon bridge 158 in the direction parallel to the upper surface of the molding material 148 can be equal to or less than the width of the molding material 148 to achieve these advantages. These advantages include an appropriate amount of molding material that can surround and support the conductive via 146. This improves the reliability of the integrated circuit package.

[0100] After the first package member 100 is coupled to the silicon bridge 158, conductive connections 152 are formed on a second of the conductive pads 150. The conductive connections 152 may be ball grid array connections, solder balls, or the like. The conductive connections 152 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connections 152 are formed initially via vapor deposition, electroplating, printing, solder transfer, placement of balls, or similar methods to form a solder layer. Once the solder layer is formed on the structure, it can be reflowed to shape the material into the desired bump shape. The conductive connections 152 can be used to bond the first package member 100 to another package member, such as a package substrate or the like.

[0101] exist Figure 15 In this process, a carrier separation process is performed to separate the carrier 102 from the first packaging component 100 (such as the integrated circuit die 50, conductive via 120, and molding material 128). In some embodiments, the separation process includes projecting light, such as laser light or ultraviolet light, onto the release layer 104, causing the release layer 104 to decompose under photothermal conditions, and the carrier 102 can be removed. The structure is then flipped over and placed on a tape (not shown).

[0102] After the first packaging member 100 separates from the carrier plate 102, conductive connections 164 can be formed on the upper surface of the conductive via 120 to physically contact the upper surface of the conductive via 120. The conductive connections 164 can be solder balls or the like. The conductive connections 164 can include conductive materials such as solder or the like. In some embodiments, the conductive connections 164 can initially be formed by vapor deposition, electroplating, printing, solder transfer, or similar methods to form a solder layer. Once the solder layer is formed on the structure, it can be reflowed to shape the material into the desired bump shape.

[0103] like Figure 15 As shown, a second package member 200 is coupled to a first package member 100 to form an integrated circuit device stack such as package 110. For example, the second package member 200 includes a substrate 202 with one or more stacked dies 210 (e.g., 210A and 210B) coupled to the substrate 202. Although the figures show a set of stacked dies 210 (210A and 210B), other embodiments may have multiple stacked dies (each having one or more stacked dies) arranged side-by-side to the same surface of the substrate 202. The substrate 202 may be composed of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, or the like may also be used. Furthermore, the substrate 202 may be a semiconductor-on-insulator substrate. Generally speaking, a semiconductor substrate on an insulating layer includes a semiconductor material layer such as epitaxial silicon, germanium, or silicon-germanium, such as silicon on an insulating layer, silicon-germanium on an insulating layer, or a combination thereof.

[0104] In other embodiments, substrate 202 is essentially an insulating core, such as a glass fiber reinforced resin core. An example of a core material is a glass fiber resin such as FR4. The core material may be changed to include bismaleimide-triazine resin, or to other printed circuit board materials or films. Laminated films such as Ajinomoto laminates or other laminates may also be used for substrate 202.

[0105] The substrate 202 may include active and passive devices (not shown). Various devices such as transistors, capacitors, resistors, combinations thereof, or the like may be used to produce the structure and function required for the design of the second package component 200. Any suitable method may be used to form the devices.

[0106] The substrate 202 may also include a metallization layer and conductive vias 208. The metallization layer may be formed on active and passive devices and is designed to connect multiple devices to form a functional circuit. The metallization layer may consist of interleaved dielectric material layers (such as low dielectric constant dielectric materials) and conductive material layers (such as copper) and interconnecting conductive material layers within the vias, and its formation method may be any suitable process (such as deposition, damascene, dual damascene, or similar processes). In some embodiments, the substrate 202 substantially does not contain active or passive devices.

[0107] The substrate 202 may have bonding pads 204 on a first side of the substrate 202 for coupling to a stacked die 210, and bonding pads 206 on a second side of the substrate 202 for coupling to a conductive interconnect 152, with the first and second sides of the substrate 202 facing each other. In some embodiments, the bonding pads 204 and 206 are formed by forming recesses (not shown) in dielectric layers (not shown) on the first and second sides of the substrate 202. The recesses allow the bonding pads 204 and 206 to be buried in the dielectric layer. In other embodiments, the recesses may be omitted, and the bonding pads 204 and 206 may be formed on the dielectric layer. In some embodiments, the bonding pads 204 and 206 include a thin seed layer (not shown), the composition of which may be copper, titanium, nickel, gold, palladium, the like, or a combination thereof. Conductive material for the bonding pads 204 and 206 may be deposited on the thin seed layer. The conductive material can be formed by electrochemical plating, electroless plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, similar methods, or combinations thereof. In one embodiment, the conductive material of the bonding pads 204 and 206 is copper, tungsten, aluminum, silver, gold, the like, or combinations thereof.

[0108] In some embodiments, bonding pads 204 and 206 are under-bump metallization layers, which may include three layers of conductive material such as a titanium layer, a copper layer, and a nickel layer. Other configurations of materials and layers, such as chromium / chromium-copper alloy / copper / gold, titanium / titanium-tungsten / copper, or copper / nickel / gold, may be used to form bonding pads 204 and 206. Any suitable materials or material layers used for bonding pads 204 and 206 are fully included within the scope of this embodiment. In some embodiments, a conductive via 208 extends through the substrate 202 and couples at least one bonding pad 204 to at least one bonding pad 206.

[0109] In the described embodiment, the stacked die 210 is coupled to the substrate 202 via wiring bonding 212, but other connections such as conductive bumps may also be used. For example, the stacked die 210 may be a memory die such as a low-power double data rate (LPDDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules. In other embodiments, the stacked die 210 may be a memory die, which may include a dynamic random access memory die or a flash memory die.

[0110] Molding material 214 can seal the stacked die 210 and the wiring junction 212. For example, compression molding can be used to mold the molding material 214 onto the stacked die 210 and the wiring junction 212. In some embodiments, the molding material 214 is a molding compound, polymer, epoxide, silica filler material, the like, or a combination thereof. A curing process can be performed to cure the molding material 214, and the curing process can be thermosetting, UV curing, a similar process, or a combination thereof.

[0111] In some embodiments, the stacked dies 210 and wiring connections 212 are embedded in the molding material 214. After the molding material 214 is cured, a planarization step such as grinding may be performed to remove excess portions of the molding material 214 and provide a substantially flat surface for the second encapsulation member 200.

[0112] After the second package component 200 is formed, the second package component 200 may be mechanically and electrically bonded to the first package component 100 via conductive connector 164, bonding pad 206, and conductive via 120. In some embodiments, the stacked die 210 may be coupled to the integrated circuit die 50 via wiring bonding 212, bonding pads 204 and 206, conductive via 208, conductive connector 164, conductive via 120, and front redistribution structure 122.

[0113] An underfill layer 216 is formed between the first encapsulation member 100 and the second encapsulation member 200 to surround the conductive connector 164. The underfill layer reduces stress and protects the interface formed by the reflow of the conductive connector 164. The underfill layer can be formed by a capillary flow process after bonding the second encapsulation member 200, or by a suitable deposition method before bonding the second encapsulation member 200.

[0114] exist Figure 16 Next, the package 110 is placed on the strip, which can be secured to the frame. In some embodiments, along the cut line area (e.g. Figure 15The cutting process is performed using the cutting line 15 shown to cut package 110 into multiple packages (such as packages 110A to 110C) with identical structures. In some embodiments, the cutting process is performed after the second package member 200 is coupled to the first package member 100. In other embodiments (not shown), the cutting process is performed before the second package member 200 is coupled to the first package member 100.

[0115] like Figure 16 As shown, each package 110 can then be embedded into the package substrate 300 using conductive connectors 152. The package substrate 300 includes a substrate core 302 and bonding pads 304 located on the substrate core 302. The substrate core 302 may be composed of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, or the like may be used. Furthermore, the substrate core 302 may be a semiconductor-on-insulator (SBI) substrate. Generally, an SBI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, or silicon germanium, such as silicon-on-insulator, silicon germanium-on-insulator, or combinations thereof. In other embodiments, the substrate core 302 is essentially an insulating core such as a glass fiber reinforced resin core. An example of a core material is a glass fiber resin such as FR4. The core material may be changed to include bismaleimide-triazine resin, or to other printed circuit board materials or films. Laminated films, such as Ajinomoto laminated films or other laminates, can also be used in substrate core 302.

[0116] The substrate core 302 may include active and passive devices (not shown). Various devices such as transistors, capacitors, resistors, combinations thereof, or the like may be used to produce the structure and function required for the device stack design. Any suitable method may be used to form the devices.

[0117] The substrate core 302 may also include a metallization layer and vias (not shown), with bonding pads 304 physically and / or electrically coupled to the metallization layer and vias. The metallization layer may be formed on active and passive devices and designed to connect various devices to form a functional circuit. The metallization layer may consist of interleaved dielectric material layers (such as low-dielectric-constant dielectric materials) and conductive material layers (such as copper), as well as conductive material layers for interconnects within the vias, and its formation method may be any suitable process (such as deposition, damascene, dual damascene, or similar processes). In some embodiments, the substrate core 302 substantially does not contain active or passive devices.

[0118] In some embodiments, the conductive connector 152 is reflowed to adhere the package 110 to the bonding pad 304. The conductive connector 152 is electrically and / or physically coupled to the package substrate 300 to the first package member 100, and the package substrate contains a metallization layer in the substrate core 302. In some embodiments, a solder mask 306 is formed on the substrate core 302. The conductive connector 152 may be located in an opening in the solder mask 306 to be electrically and mechanically coupled to the bonding pad 304. The solder mask 306 can be used to protect areas of the substrate core 302 from external damage. These advantages are achieved by forming a first package member 100 containing a front-side redistribution structure 122 on the first integrated circuit die (50) and the second integrated circuit die (50). A portion of the front redistribution structure 122 is removed to form an opening 143 in the front redistribution structure 122, and a first conductive via (146) and a second conductive via (146) are formed in the opening 143, wherein the first conductive via (146) is electrically connected to the first integrated circuit die (50), and the second conductive via (146) is electrically connected to the second integrated circuit die (50). A molding material 148 is formed around and between the first conductive via (146) and the second conductive via (146) to fill the opening 143, and a silicon bridge 158 is coupled to the first conductive via (146) and the second conductive via (146). These advantages include reducing the length of the in-wire interconnect between the first integrated circuit die (50) and the second integrated circuit die (50). In addition, the first conductive via (146) and the second conductive via (146) have a large diameter. This reduces resistance and improves electrical performance. In addition, molding material 148 is formed around the first conductive via (146) and the second conductive via (146) to provide high rigidity, which can prevent breakage in the molding material 148 and improve the reliability of integrated circuit packaging.

[0119] Figure 17 Show package 111. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments described below) denote... Figures 1 to 16 Similar structures formed by similar processes in the illustrated embodiments. In summary, the manufacturing steps and feasible materials will not be described again.

[0120] Package 111 can be used with Figure 16The package 110 is similar. However, the dielectric layer 124 and conductive pads 126 located between the molding material 148 and the first integrated circuit die (50) may be omitted in the package 111. Furthermore, there are no conductive pads 126 and dielectric layer 124 located between the molding material 148 and the second integrated circuit die (50). The molding material 148 extends completely through the front redistribution structure 122, so that the molding material 148 physically contacts the first integrated circuit die (50) and the second integrated circuit die (50). In addition, the first conductive via (146) and the second conductive via (146) extend completely through the molding material 148 to physically contact the die connector (66) of the first integrated circuit die (50) and the second die connector (66) of the second integrated circuit die (50), respectively. The first conductive via (146) and the second conductive via (146) are electrically coupled to the silicon bridge 158.

[0121] This embodiment of the invention has several advantages. The embodiment can form an integrated circuit package including a front redistribution structure on a first integrated circuit die and a second integrated circuit die. A portion of the front redistribution structure is removed to form an opening in the front redistribution structure, and a first through-insulator (BII) via and a second through-insulator (BII) via are formed in the opening, wherein the first BII via is electrically connected to the first integrated circuit die, and the second BII via is electrically connected to the second integrated circuit die. A molding material is formed around the first BII via and the second BII via to fill the opening, and a silicon bridge is formed on and coupled to the first BII via and the second BII via. An advantage is that it can reduce the length of the in-line interconnects between the first integrated circuit die and the second integrated circuit die. Furthermore, the first BII via and the second BII via may include a larger diameter. This can reduce resistance and improve electrical performance. Furthermore, the molding material formed around the first and second through-insulator vias provides high rigidity, preventing breakage within the molding material. This improves the reliability of integrated circuit packaging.

[0122] In one embodiment, the package includes a first die and a second die embedded in a first molding material; a first redistribution structure located on the first die and the second die; a second molding material located on portions of the first die and the second die, wherein the second molding material is situated between a first portion and a second portion of the first redistribution structure; a first via extending through the second molding material, wherein the first via is electrically connected to the first die; a second via extending through the second molding material, wherein the second via is electrically connected to the second die; and a silicon bridge electrically coupled to the first via and the second via. In one embodiment, the first via physically contacts a first die connector of the first die, and the second via physically contacts a second die connector of the second die. In one embodiment, the second molding material physically contacts the first die and the second die. In one embodiment, a third portion of the first redistribution structure is located between the second molding material and the first die and the second die. In one embodiment, the first via physically contacts a first conductive pad in the third portion of the first redistribution structure, and the second via physically contacts a second conductive pad in the third portion of the first redistribution structure. In one embodiment, the silica filler content of the second molding material is less than 70 wt%.

[0123] In one embodiment, the package structure includes a first die and a second die embedded in a first insulating material; a first rewiring structure located on the first die and the second die, and the first rewiring structure includes a dielectric layer; a first conductive pad physically contacting a first die connector of the first die; a second conductive pad physically contacting a second die connector of the second die; a second insulating material extending partially through the first rewiring structure, wherein the material of the second insulating material is different from the material of the dielectric layer; a first via extending through the second insulating material to physically contact the first conductive pad; and a second via extending through the second insulating material to physically contact the second conductive pad. In one embodiment, the package structure further includes a silicon bridge coupled to the first via and the second via, wherein the first die is electrically connected to the second die via the silicon bridge. In one embodiment, the package structure further includes a package member electrically coupled to the first rewiring structure, wherein the first rewiring structure is located between the package member and the silicon bridge. In one embodiment, the first width of the silicon bridge in a direction parallel to the upper surface of the second insulating material is less than or equal to the minimum width of the second insulating material from the first outermost sidewall to the second outermost sidewall. In one embodiment, the packaging structure further includes a packaging substrate coupled to a first rewiring structure, wherein the first rewiring structure is located between the packaging substrate and the first die. In one embodiment, the dielectric constant of the second insulating material is 2.8 to 4.2. In one embodiment, the silicon oxide filler content of the second insulating material is less than 70 wt%.

[0124] In one embodiment, a method of forming an integrated circuit package includes forming a first redistribution structure on a first die and a second die; performing an etching process to form an opening in the redistribution structure on the first die and the second die; forming a first via and a second via in the opening, wherein the first via is electrically connected to the first die and the second via is electrically connected to the second die; filling the opening with a molding material, wherein the molding material surrounds each of the first via and the second via; and coupling a silicon bridge to the first via and the second via. In one embodiment, after the etching process, the opening exposes a first contact pad and a second contact pad of the first redistribution structure, wherein the first contact pad physically contacts a first die connector of the first die, and the second contact pad physically contacts a second die connector of the second die. In one embodiment, the step of forming the first via and the second via includes electroplating a conductive material onto the upper surfaces of the first contact pad and the second contact pad, respectively. In one embodiment, the dielectric constant of the molding material is from 2.8 to 4.2. In one embodiment, after the etching process, an opening exposes the first grain connector of the first grain and the second grain connector of the second grain. In one embodiment, the step of forming the first through-hole and the second through-hole includes electroplating conductive materials onto the first grain connector of the first grain and the second grain connector of the second grain, respectively. In one embodiment, after forming a molding material in the opening, the molding material physically contacts the first grain and the second grain.

[0125] The features of the above embodiments are beneficial for those skilled in the art to understand this utility model. Those skilled in the art should understand that this utility model can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this utility model, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this utility model.

Claims

1. A package, characterized in that, include: A first grain and a second grain are embedded in a first molding material; A first wiring structure is located on the first die and the second die; A second molding material is located on a portion of the first grain and the second grain, wherein the second molding material is located between the first portion and the second portion of the first rewiring structure; A first through-hole extends through the second molded material, wherein the first through-hole is electrically connected to the first grain; A second through-hole extends through the second molded material, wherein the second through-hole is electrically connected to the second grain; and A silicon bridge is electrically coupled to the first via and the second via.

2. The packaging as claimed in claim 1, characterized in that, The first through-hole physically contacts a first grain connector of the first grain, and the second through-hole physically contacts a second grain connector of the second grain.

3. The packaging as described in claim 2, characterized in that, The second molding material is in physical contact with the first grain and the second grain.

4. The packaging as claimed in claim 1 or 2, characterized in that, The third part of the first rewiring structure is located between the second molding material and the first and second grains.

5. The packaging as claimed in claim 4, characterized in that, The first through-hole physically contacts a first conductive pad in the third part of the first rewiring structure, and the second through-hole physically contacts a second conductive pad in the third part of the first rewiring structure.

6. A packaging structure, characterized in that, include: A first grain and a second grain are embedded in a first insulating material; as well as A first overlay structure is located on the first die and the second die, and the first overlay structure includes: One dielectric layer; A first conductive pad, physically contacting a first grain connector of the first grain; A second conductive pad, physically contacting a second grain connector of the second grain; A second insulating material extends partially through the first rewiring structure, wherein the material of the second insulating material is different from the material of the dielectric layer; A first through-hole extends through the second insulating material to physically contact the first conductive pad; and A second through hole extends through the second insulating material to physically contact the second conductive pad.

7. The packaging structure as claimed in claim 6, characterized in that, Also includes: A silicon bridge is coupled to the first via and the second via, wherein the first die is electrically connected to the second die via the silicon bridge.

8. The packaging structure as described in claim 7, characterized in that, Also includes: A package component electrically coupled to the first rewiring structure, wherein the first rewiring structure is located between the package component and the silicon bridge.

9. The packaging structure as claimed in claim 7, characterized in that, The first width of the silicon bridge in the direction parallel to the upper surface of the second insulating material is less than or equal to the minimum width of the second insulating material from the first outermost sidewall to the second outermost sidewall.

10. The packaging structure as claimed in claim 6 or 7, characterized in that, Also includes: A packaging substrate is coupled to the first rewiring structure, wherein the first rewiring structure is located between the packaging substrate and the first die.

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