Power-on and power-off time sequence control circuit of GPU (Graphics Processing Unit) and intelligent computing card

Abstract

The utility model relates to the technical field of time sequence control circuits, in particular to a power-on and power-off time sequence control circuit of a GPU (Graphics Processing Unit) and an intelligent computing card. Comprising a plurality of Schmidt inversion modules; each path of output end of the Schmidt inversion module is respectively connected with different power-on pins of a target GPU; each path of input end of the Schmidt inversion module is connected with the first end of one delay control module; each delay control module has different delay settings based on the corresponding resistance value difference; the second ends of all the delay control modules are connected with the first end of the trigger module, the second end of the trigger module is connected with an external first signal source, and the third end of the trigger module is grounded; and the third end of each delay control module is connected with an external second signal source. According to the invention, the defects of a CPLD and MCU control mode in the aspect of occupying the area of a power-on circuit can be overcome, the requirement for the small size of a mainboard is met, and the stability and reliability of a system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of timing control circuit, and particularly relates to a power-on and power-off timing control circuit of GPU and a smart computing card. BACKGROUND

[0002] In the existing timing control field, the common CPLD (Complex Programmable Logic Device) and MCU (Microcontroller Unit) control mode has some defects that cannot be ignored. Specifically speaking:

[0003] Chip size and peripheral device problem: The size of the conventional CPLD and MCU chips is large. For example, the size of the common MCU_48Pin model chip reaches 7mm*9mm, the size of the MCU_64Pin model chip is 12mm*12mm, and the size of the CPLD_48Pin model chip is 9mm*9mm. Moreover, these devices need peripheral devices such as crystal oscillators in actual use. This leads to the problem that the area of the circuit board occupied in the overall layout cannot be ignored. In some application scenarios with strict requirements on the size of the mainboard, the relatively large occupied area becomes a prominent problem, which limits the flexibility and compactness of the circuit design.

[0004] Program burning and stability problem: Before being put into use, the CPLD and MCU need to be programmed by professional software engineers, and the program burning operation needs to be performed by the factory in the production process. This process not only increases the complexity and cost of the production link, but also introduces the risk of loss of program data. Once the medium storing the program fails or is disturbed by the outside world, the program data may be lost or damaged, thereby affecting the normal operation of the entire system.

[0005] In summary, how to overcome the defects of the CPLD and MCU control mode in the aspect of occupying the power-on circuit area, meet the demand for the small size of the mainboard, and improve the stability and reliability of the system is a technical problem to be solved. CONTENT OF THE INVENTION

[0006] In order to overcome the defects of the prior art, the present application provides a power-on and power-off timing control circuit of GPU and a smart computing card, so as to overcome the defects of the CPLD and MCU control mode in the aspect of occupying the power-on circuit area, meet the demand for the small size of the mainboard, and improve the stability and reliability of the system.

[0007] The technical scheme adopted by the present application to solve the technical problems is:

[0008] The first aspect of the application provides a power-on and power-off timing control circuit of a GPU, comprising: a Schmidt inverter module provided with multiple paths; each output end of the Schmidt inverter module is connected to a different power-on pin of a target GPU;

[0009] Each input end of the Schmidt inverter module is connected to a first end of a delay control module; each delay control module has different delay settings based on corresponding differences in resistance values;

[0010] The second end of each delay control module is connected to the first end of the trigger module, the second end of the trigger module is connected to an external first signal source, and the third end of the trigger module is grounded;

[0011] The third end of each delay control module is connected to an external second signal source, when the first signal source sends a first enable signal to the trigger module, if the second signal source sends a second enable signal to all the delay control modules, then according to the corresponding delay settings of each delay control module, the multiple output ends of the Schmidt inverter module are sequentially pulled high, realizing power-on timing control;

[0012] The first end of the trigger module is also connected to an external third signal source, when the first signal source sends a first enable signal to the trigger module, if the third signal source sends a third enable signal to all the delay control modules, then according to the corresponding delay settings of each delay control module, the multiple output ends of the Schmidt inverter module are sequentially pulled low, realizing power-off timing control.

[0013] Optionally, the trigger module comprises a circuit trigger unit and an over-temperature protection unit;

[0014] The first end of the circuit trigger unit is connected to the second end of all the delay control modules, and the second end of the circuit trigger unit is connected to the first signal source;

[0015] The third end of the circuit trigger unit is connected to the first end of the over-temperature protection unit, the second end of the over-temperature protection unit is connected to the over-temperature protection end of the target GPU, and the third end of the over-temperature protection unit is grounded;

[0016] When the target CPU sends an over-temperature power-off protection signal to the over-temperature protection unit, the circuit trigger unit is used to prohibit each output end of the Schmidt inverter module to power on the target GPU, realizing over-temperature power-off protection.

[0017] Optionally, the Schmidt inverter module comprises multiple Schmidt inverters;

[0018] Each input end of the Schmidt inverter is connected with a first end of the delay control module, and each output end of the Schmidt inverter is connected with a different power-on pin of the target GPU.

[0019] Optionally, the delay control module comprises a first delay unit group, a second delay unit and a third delay unit group.

[0020] The first delay unit group comprises one or more first delay units, and each first delay unit is provided with a first resistor, a second resistor, a first capacitor and a first diode; in each first delay unit, the second signal source is connected with one input end of the Schmidt inverter and one end of the first resistor through the first capacitor, the other end of the first resistor is connected with the anode of the first diode and one end of the second resistor, and the other end of the second resistor and the cathode of the first diode are both connected with the first end of the circuit trigger unit.

[0021] The second delay unit is provided with a third resistor and a second capacitor; in the second delay unit, the second signal source is connected with one input end of the Schmidt inverter and one end of the third resistor through the second capacitor, and the other end of the third resistor is connected with the first end of the circuit trigger unit.

[0022] The third delay unit group comprises one or more third delay units, and each third delay unit is provided with a fourth resistor, a fifth resistor, a third capacitor and a second diode; in each second delay unit, the second signal source is connected with one input end of the Schmidt inverter and one end of the fourth resistor through the third capacitor, the other end of the fourth resistor is connected with one end of the fifth resistor and the cathode of the second diode, and the other end of the fifth resistor and the anode of the second diode are both connected with the first end of the circuit trigger unit.

[0023] Each input end of the Schmidt inverter is connected with one first delay unit, one second delay unit or one third delay unit.

[0024] Optionally, the circuit trigger unit comprises a sixth resistor, a first MOS tube, a seventh resistor and an eighth resistor.

[0025] The second end of each delay control module is connected with the drain of the first MOS tube and one end of the sixth resistor, and the other end of the sixth resistor is connected with the third signal source.

[0026] The gate of the first MOS tube is connected with the first signal source through the seventh resistor; the source of the first MOS tube is connected with the first end of the over-temperature protection unit and connected with the ground through the eighth resistor.

[0027] Optionally, the over-temperature protection unit comprises a second MOS tube and a ninth resistor.

[0028] The drain of the second MOS tube is connected with the source of the first MOS tube through the ninth resistor, the gate of the second MOS tube is connected with the over-temperature protection end of the target GPU, and the source of the second MOS tube is grounded.

[0029] Optionally, the timing control circuit applied to the ZhiGai100 chip, the target GPU is the ZhiGai100 chip, and the model of the Schmitt inverter is RS6G14.

[0030] Optionally, the first delay unit group comprises two first delay units.

[0031] The resistances of the first resistors in all the first delay units are different from each other, and the resistances of the second resistors in all the first delay units are different from each other.

[0032] Optionally, the third delay unit group comprises three third delay units.

[0033] The resistances of the fourth resistors in all the third delay units are different from each other, and the resistances of the fifth resistors in all the third delay units are different from each other.

[0034] In a second aspect, the present application provides a smart card loaded with the power-on and power-off timing control circuit.

[0035] The technical scheme has the advantages that the Schmitt inverter module is used to replace the traditional complex programmable logic device (CPLD) or micro control unit (MCU), so that the power-on and power-off timing control of the GPU is realized on a small circuit board. Specifically, this design reduces the area occupied by the circuit layout, because the Schmitt inverter module has a smaller size than the CPLD and MCU; at the same time, the complex burning process is no longer needed, and the power-on and power-off processes are directly controlled by an external signal source, thereby improving the stability and reliability of the system.

[0036] Specifically, the workflow is as follows: when the external signal source sends the power-on control signal, the delay control module is activated in turn, indirectly drives the Schmidt inverter module through the trigger module, so that the GPU realizes accurate power-on timing control; on the contrary, when the power-off control signal is generated, the delay control module will drive the Schmidt inverter module to discharge in turn, and complete the power-off process of the GPU. Such design makes the control process of the whole system complete under a unified signal source, avoids the risk of program loss that may occur during the burning process, and thus has high reliability and adaptability, and is especially suitable for application scenarios with strict requirements on the size of the motherboard. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a module connection diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application;

[0038] Figure 2 is a circuit principle diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application;

[0039] Figure 3 is a working logic diagram of the Schmidt inverter of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application;

[0040] Figure 4 is a power-on timing diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application;

[0041] Figure 5 is a power-off timing diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application;

[0042] Figure 6 is a circuit principle diagram of the trigger module of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application.

[0043] Reference signs: R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; Q1, first MOS tube; Q2, second MOS tube; D1, first diode; D2, second diode. DETAILED DESCRIPTION

[0044] The present application will be further described below in conjunction with the drawings and embodiments.

[0045] The concept, specific structure and generated technical effects of the present application will be described clearly and completely in combination with the embodiments and drawings, so as to fully understand the purpose, features and effects of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments, and based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. In addition, all the coupling / connection relations involved in the patent do not mean that the components are directly connected, but that a better coupling structure can be composed by adding or reducing coupling accessories according to the specific implementation. The technical features in the creation of the present application can be combined interactively without contradiction and conflict.

[0046] Reference Figure 1 , Figure 1 is a module connection diagram of the power-on / off timing control circuit of the GPU provided by the embodiments of the present application, comprising a Schmidt inverter module provided with multiple channels, a delay control module for realizing timing control, and a trigger module for starting the timing control module, which will be described in detail as follows:

[0047] It comprises a Schmidt inverter module provided with multiple channels; each output end of the Schmidt inverter module is connected to a different power-on pin of the target GPU.

[0048] Specifically, the Schmidt inverter module comprises a Schmidt inverter, which is provided with multiple inputs and multiple outputs corresponding to the multiple inputs, and the multiple outputs are respectively connected to multiple power-on pins of the target GPU. In the embodiments of the present application, when the timing control circuit provided by the present application is in the power-on mode, the multiple outputs of the Schmidt inverter are pulled up one by one according to the preset order, thereby meeting the power-on timing requirements of the target GPU.

[0049] Further, each input end of the Schmidt inverter module is connected to the first end of one delay control module; each delay control module has different delay settings based on the difference in corresponding resistance values.

[0050] Specifically, the Schmidt inverter in the Schmidt inverter module is provided with multiple inputs, and each output is connected to one delay control module. In each delay control module, different RC delay effects are produced based on the different resistance values set therein.

[0051] In the embodiment, if in the power-on mode, an external signal source controls all the delay control modules to start at the same time, based on different delay settings of each delay control module, all the input ends of the Schmidt inverter module are sequentially pulled low, thereby all the output ends of the corresponding Schmidt inverter module are sequentially pulled high, and the power-on of the target GPU is realized; if in the power-off mode, another external signal source controls all the delay control modules to start, based on different diode connection and resistance value settings in each delay control module, all the input ends of the Schmidt inverter module are sequentially pulled high, thereby all the output ends of the Schmidt inverter module are sequentially pulled low, and the timing power-off is realized.

[0052] Further, the second end of all the delay control modules is connected to the first end of the trigger module, the second end of the trigger module is connected to an external first signal source, and the third end of the trigger module is grounded.

[0053] Specifically, the delay control module is controlled to power off by the trigger module, including active power-off and forced power-off. When active power-off, the first signal source outputs a level signal, the level signal makes the switch in the trigger module turn off, the delay control module sends a high level to each input end of the Schmidt inverter module, based on the delay setting, the input end of the Schmidt inverter module is sequentially pulled high, thereby the power-off effect is realized.

[0054] More specifically, the delay control module is connected to an external second signal source, when the first signal source sends a first enable signal to the trigger module, if the second signal source sends a second enable signal to all the delay control modules, according to the delay setting corresponding to each delay control module, the multiple output ends of the Schmidt inverter module are sequentially pulled high, thereby the power-on timing control is realized.

[0055] More specifically, the first end of the trigger module is further connected to an external third signal source, the third signal source can be an independent signal source or the same as the first signal source. When the first signal source sends a first enable signal to the trigger module, if the third signal source sends a third enable signal to all the delay control modules, according to the delay setting corresponding to each delay control module, the multiple output ends of the Schmidt inverter module are sequentially pulled low, thereby the power-off timing control is realized.

[0056] Further, in order to realize the forced power-off function of the trigger module, the application proposes that the trigger module is composed of a circuit trigger unit and an over-temperature protection unit, specifically:

[0057] The first end of the circuit trigger unit is connected to the second end of all the delay control modules, and the second end of the circuit trigger unit is connected to the first signal source.

[0058] The third end of the circuit trigger unit is connected to the first end of the over-temperature protection unit, the second end of the over-temperature protection unit is connected to the over-temperature protection end of the target GPU, and the third end of the over-temperature protection unit is grounded.

[0059] Specifically, when the target CPU sends an over-temperature power-off protection signal to the over-temperature protection unit, the circuit trigger unit is used to disable each output end of the Schmitt inverter module to power on the target GPU, thereby achieving over-temperature power-off protection.

[0060] More specifically, when the target GPU has completed power-on and is in a running state, based on real-time detection of the temperature inside the chip of the target GPU, an over-temperature power-off protection signal is output. When the chip temperature of the target GPU reaches a preset temperature threshold, the over-temperature protection end of the target GPU sends a corresponding over-temperature power-off protection signal, so that the over-temperature protection unit forcibly turns off the entire trigger module, and all output ends of the Schmitt inverter module are sequentially pulled low, thereby achieving the effect of forced power-off protection. The over-temperature power-off protection signal can be a level signal, for example, a low-level signal.

[0061] Further, referring to Figure 2 , Figure 2 is a circuit schematic diagram of a power-on and power-off timing control circuit of a GPU provided by the embodiment of the present application, which provides a specific implementation of each of the above modules, and the following will be specifically described with reference to Figure 2 each module:

[0062] The Schmitt inverter module includes a plurality of Schmitt inverters.

[0063] Each input end of the Schmitt inverter is connected to the first end of one of the delay control modules, and each output end of the Schmitt inverter is connected to a different power-on pin of the target GPU.

[0064] Specifically, the plurality of Schmitt inverters have a plurality of input ends and a plurality of output ends corresponding to the plurality of input ends. In the embodiment of the present application, the target GPU is taken as the Zhijie 100 chip as an example. In order to meet the power-on and power-off requirements of the Zhijie 100 chip, a 6-channel Schmitt inverter with a model number of RS6G14 is used.

[0065] Referring to Figure 3 , Figure 3 is a working logic diagram of a Schmitt inverter of a power-on and power-off timing control circuit of a GPU provided by the embodiment of the present application. In combination with Figure 3 As can be seen from the left drawing, the 6-channel Schmitt inverter is provided with 6 input ends and corresponding 6 output ends, in combination with Figure 3As can be seen from the right graph, when each input end is at high level (H), the corresponding output end is at low level (L) to sequentially power up the multiple power pins of the target GPU; conversely, when each input end is at low level (L), the corresponding output end is at high level (H) to sequentially pull down the multiple power pins of the target GPU, thereby achieving timing power down.

[0066] Further, the delay control module comprises a first delay unit group, a second delay unit and a third delay unit group, wherein each input end of the Schmitt inverter is connected to the first delay unit, the second delay unit or the third delay unit.

[0067] The first delay unit group comprises one or more first delay units, each of which is provided with a first resistor R1, a second resistor R2, a first capacitor C1 and a first diode D1; in each first delay unit, the second signal source is connected to the input end of one of the Schmitt inverters and one end of the first resistor R1 through the first capacitor C1, the other end of the first resistor R1 is connected to the anode of the first diode D1 and one end of the second resistor R2, and the other end of the second resistor R2 and the cathode of the first diode D1 are both connected to the first end of the circuit trigger unit.

[0068] Specifically, referring to Figure 2 , Figure 2 In the provided embodiment, the first delay unit group comprises two first delay units, and taking one of them (the first one) as an example, when in the power-up mode, the second signal source (P3VP) is sequentially connected to the ground through the first capacitor C1, the first resistor R1, the first diode D1 and the trigger module output, so as to pull down the input end of the Schmitt inverter, thereby pulling up the corresponding output end and completing the power-up of the corresponding pin of the output end; when in the power-down mode, the signal sent by the third signal source connected through the trigger module pulls up the input end of the Schmitt inverter through the second resistor R2 and the first resistor R1, thereby pulling down the corresponding output end and completing the power-down of the corresponding pin of the output end.

[0069] The second delay unit is provided with a third resistor R3 and a second capacitor C2; in the second delay unit, the second signal source is connected to one end of the third resistor R3 and the input end of one of the Schmitt inverters through the second capacitor C2, and the other end of the third resistor R3 is connected to the first end of the circuit trigger unit.

[0070] Specifically, the second delay unit is for a branch with a resistance value at a middle value among all the branches, for example, the third branch or the fourth branch in the six branches (in this embodiment, the third branch in the six branches), the fourth branch in the seven branches, to ensure timing stability, the second delay unit has only one branch, compared with other branches, it does not need to be equipped with a diode and does not need to be additionally equipped with a resistor, only needs to set the delay of the front and rear branches to be reasonable, thereby reducing the use of components, and the effect of the up and down timing control can also be achieved.

[0071] The third delay unit group includes one or more third delay units, each of which is provided with a fourth resistor R4, a fifth resistor R5, a third capacitor C3 and a second diode D2; in each of the second delay units, the second signal source connects one end of the fourth resistor R4 and the input end of one of the Schmitt inverters through the third capacitor C3, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5 and the negative electrode of the second diode D2, and the other end of the fifth resistor R5 and the positive electrode of the second diode D2 are both connected to the first end of the circuit trigger unit.

[0072] Specifically, referring to Figure 2 In this embodiment, three third delay units are included, taking one of them as an example (the fourth branch), when in the power-on mode, the second signal source (P3VP) sequentially passes through the third capacitor C3, the fourth resistor R4, the fifth resistor R5, the trigger module to the ground, so that the input end level of the Schmitt inverter in this branch is pulled low, thereby pulling up the output end of the Schmitt inverter in this branch, and realizing the power-on of this branch; when in the power-off mode, the signal sent by the third signal source connected through the trigger module pulls up the input end level of the Schmitt inverter in this branch through the second diode D2 and the fourth resistor R4, so that the output end of the Schmitt inverter in this branch is pulled down, and the power-off is realized.

[0073] For intuitive display, the above description about the power-on mode and the power-off mode can be combined, and the following Figure 4 and Figure 5 can be referred to to deepen the understanding of the timing control, wherein Figure 4 is a power-on timing diagram of the power-on and power-off timing control circuit of the GPU provided in this embodiment; Figure 5 is a power-off timing diagram of the power-on and power-off timing control circuit of the GPU provided in this embodiment.

[0074] The embodiment of the application also provides a parameter embodiment of the RC delay setting of the power-on part for reference:

[0075]

[0076] Further, the circuit triggering unit comprises a sixth resistor R6, a first MOS Q1, a seventh resistor R7 and an eighth resistor R8;

[0077] The second end of all the delay control modules is connected to the drain of the first MOS Q1 and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the third signal source.

[0078] The gate of the first MOS Q1 is connected to the first signal source through the seventh resistor R7, and the source of the first MOS Q1 is connected to the first end of the over-temperature protection unit and the ground through the eighth resistor R8.

[0079] Specifically, referring to Figure 2 In the present application, one end of each of the plurality of delay control modules is connected to the drain of the first MOS Q1. If it is not in an over-temperature state (i.e., the over-temperature protection unit is in normal operation), when the first signal source sends a high level, the gate of the first MOS Q1 will be pulled high, thereby turning on the first MOS Q1. The turned-on first MOS Q1 will make the drain of the first MOS Q1 grounded through its source and the over-temperature protection unit, thereby pulling down the level of each input end of the Schmitt inverter.

[0080] If it is in an over-temperature state, in this case the over-temperature protection unit is equivalent to being disconnected. In this case, regardless of the on-off state of the first MOS Q1, the source of the first MOS Q1 will be pulled high, thereby pulling up the level of each input end of the Schmitt inverter, achieving the effect of power-down.

[0081] Further, the over-temperature protection unit comprises a second MOS Q2 and a ninth resistor R9;

[0082] The drain of the second MOS Q2 is connected to the source of the first MOS Q1 through the ninth resistor R9, the gate of the second MOS Q2 is connected to the over-temperature protection end of the target GPU, and the source of the second MOS Q2 is grounded.

[0083] Specifically, referring to Figure 6 , Figure 6 is the circuit schematic diagram of the triggering module of the power-on and power-down timing control circuit of the GPU provided by the present application. The second MOS Q2 is connected to the over-temperature protection end of the target GPU at position two. When the chip temperature of the target GPU is in a normal range, it is a high level. This high level will pull up the gate of the second MOS Q2, thereby turning on the second MOS Q2 (i.e., the over-temperature protection unit is in a normal state).

[0084] When the chip temperature of the target GPU reaches or exceeds the preset temperature threshold, in this case the target GPU outputs a thermal shutdown protection signal through its thermal protection end, which is a low-level signal corresponding to the high level in the normal state. At this time, the gate of the second MOS tube Q2 is pulled low, and the second MOS tube Q2 is turned off. In this case, even if the first MOS tube Q1 is pulled high by the first signal source (position one), the gate of the first MOS tube Q1 will be pulled high due to the presence of the eighth resistor R8, causing the input end of the Schmidt inverter to be pulled high, the output end of the Schmidt inverter to be pulled low, and the power supply to be disconnected.

[0085] In a second aspect, the application provides a smart card loaded with the power-on and power-off timing control circuit described above.

[0086] The above is a specific description of the preferred implementation of the application, but the application creation is not limited to the described embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the application. These equivalent modifications or replacements are all included in the scope defined by the claims of the application.

Claims

1. A power-up timing control circuit of a GPU, characterized by, The application relates to a power supply circuit for a target GPU (Graphics Processing Unit). The application comprises: a plurality of Schmitt inverter modules, each of which is connected to a different power-on pin of the target GPU; each input end of the Schmitt inverter modules is connected to the first end of a delay control module, and each delay control module has different delay settings based on the difference in corresponding resistance values; the second end of all the delay control modules is connected to the first end of a trigger module, the second end of the trigger module is connected to an external first signal source, and the third end of the trigger module is grounded; the third end of each delay control module is connected to an external second signal source, and when the first signal source sends a first enable signal to the trigger module, if the second signal source sends a second enable signal to all the delay control modules, the plurality of output ends of the Schmitt inverter modules are sequentially pulled high according to the corresponding delay settings of each delay control module, thereby realizing power-on timing control; 2. The power-up and power-down timing control circuit of a GPU according to claim 1, wherein, the first end of the trigger module is also connected to an external third signal source, and when the first signal source sends a first enable signal to the trigger module, if the third signal source sends a third enable signal to all the delay control modules, the plurality of output ends of the Schmitt inverter modules are sequentially pulled low according to the corresponding delay settings of each delay control module, thereby realizing power-off timing control. The trigger module comprises a circuit trigger unit and an over-temperature protection unit; the first end of the circuit trigger unit is connected to the second end of all the delay control modules, and the second end of the circuit trigger unit is connected to the first signal source; the third end of the circuit trigger unit is connected to the first end of the over-temperature protection unit, the second end of the over-temperature protection unit is connected to the over-temperature protection end of the target GPU, and the third end of the over-temperature protection unit is grounded; 3. The power-up and power-down timing control circuit of a GPU according to claim 2, wherein, when the target CPU sends an over-temperature power-off protection signal to the over-temperature protection unit, the circuit trigger unit is used for inhibiting each output end of the Schmitt inverter modules to power on the target GPU, thereby realizing over-temperature power-off protection. The Schmitt inverter module comprises a plurality of Schmitt inverters; 4. The power-up and power-down timing control circuit of a GPU according to claim 3, wherein, each input end of the Schmitt inverters is connected to the first end of one delay control module, and each output end of the Schmitt inverters is connected to a different power-on pin of the target GPU. The delay control module comprises a first delay unit group, a second delay unit and a third delay unit group; the first delay unit group comprises one or more first delay units, each of which is provided with a first resistor, a second resistor, a first capacitor and a first diode; in each first delay unit, the second signal source is connected to the input end of one Schmitt inverter and one end of the first resistor through the first capacitor, the other end of the first resistor is connected to the anode of the first diode and one end of the second resistor, and the other end of the second resistor and the cathode of the first diode are both connected to the first end of the circuit trigger unit; The second delay unit is provided with a third resistor and a second capacitor; in the second delay unit, one end of the third resistor is connected to the input end of one of the Schmitt inverters through the second capacitor by the second signal source, and the other end of the third resistor is connected to the first end of the circuit trigger unit; The third delay unit group comprises one or more third delay units, and each third delay unit is provided with a fourth resistor, a fifth resistor, a third capacitor and a second diode; in each second delay unit, one end of the fourth resistor is connected to the input end of one of the Schmitt inverters through the third capacitor by the second signal source, the other end of the fourth resistor is connected to one end of the fifth resistor and the negative electrode of the second diode, and the other end of the fifth resistor and the positive electrode of the second diode are both connected to the first end of the circuit trigger unit; Wherein, the input end of each of the Schmitt inverters is connected to one of the first delay unit, the second delay unit or the third delay unit.

5. The power-up and power-down timing control circuit of a GPU according to claim 2, wherein, The circuit trigger unit comprises a sixth resistor, a first MOS tube, a seventh resistor and an eighth resistor; The second end of all the delay control modules is connected to the drain of the first MOS tube and one end of the sixth resistor, and the other end of the sixth resistor is connected to the third signal source; The gate of the first MOS tube is connected to the first signal source through the seventh resistor; the source of the first MOS tube is connected to the first end of the over-temperature protection unit, and is connected to the ground through the eighth resistor.

6. The power-up and power-down timing control circuit of a GPU according to claim 5, wherein, The over-temperature protection unit comprises a second MOS tube and a ninth resistor; The drain of the second MOS tube is connected to the source of the first MOS tube through the ninth resistor, the gate of the second MOS tube is connected to the over-temperature protection end of the target GPU, and the source of the second MOS tube is grounded.

7. The power-up and power-down timing control circuit of a GPU according to claim 4, wherein, The timing control circuit is applied to a ZhiGai100 chip, the target GPU is a ZhiGai100 chip, and the model of the Schmitt inverter is RS6G14.

8. The power-up and power-down timing control circuit of claim 7, wherein, The first delay unit group comprises two first delay units; The resistances of the first resistors in all the first delay units are different from each other, and the resistances of the second resistors of all the first delay units are different from each other.

9. The power-up and power-down timing control circuit of claim 7, wherein, The third delay unit group comprises three third delay units; The resistances of the fourth resistors in all the third delay units are different from each other, and the resistances of the fifth resistors in all the third delay units are different from each other.

10. An intelligent card, characterized by The timing control circuit is loaded with the power-on and power-off timing control circuit according to any one of claims 1-9.

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