Semiconductor structure

Abstract

A semiconductor device includes a memory cell connected to a signal line, a first voltage line for receiving a power supply voltage, and a second voltage line for receiving an electrical ground voltage, a logic unit configured to provide a logic function to the memory cell, a transition region, and an interconnect structure. A transition region extends from a first boundary of the memory cell to a second boundary of the logic cell, and an interconnect structure is over the memory cell and the logic cell. The interconnection structure comprises a signal line, a first voltage line and a second voltage line which are located on the same metal line layer of the interconnection structure. A signal line extends from within the second boundary of the logic cell into the first boundary of the memory cell. The transition region includes one or more functional transistors electrically coupled to the memory cell.

Description

TECHNICAL FIELD

[0001] The present utility model relates to a semiconductor structure, in particular to a semiconductor structure integrating a memory cell and a logic cell of a compute-in-memory (CIM) system. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. The pace of that growth is expected to continue well into the future, but there are signs that the industry is reaching an inflection point. As designers of ICs struggle to devise circuits that can reliably operate with ever-decreasing feature sizes, the industry is seeking ways to enhance the speed and efficiency of ICs. One way to improve the performance of ICs is to increase the amount and / or density of logic circuits incorporated in the ICs. However, as the density of logic circuits increases, the power consumption of the ICs also increases. As a result, the amount of heat generated by the ICs also increases.

[0003] Memory is widely used in ICs. For example, a static random-access memory (SRAM) is a volatile memory that is used in electronic applications that require high speed, low power consumption, and simple operation. In practical applications, SRAM is very popular in high-speed communication, image processing, and system-on-chip (SOC) applications. SRAM has the advantage of being able to save data without refreshing. After artificial intelligence (AI) has brought changes to people's lives through automation and independent decision-making capabilities, SRAM has become a suitable candidate for AI hardware implementation because it has better performance than other similar devices. However, current AI hardware (such as neural networks (NNs)) often accesses data outside the chip, which slows down the overall performance of the system. A compute-in-memory (CIM) structure can reduce off-chip data access transactions. An SRAM structure includes a plurality of SRAM cells and a plurality of logic cells. Although existing SRAM structures for memory-based ICs can generally adapt to traditional memory applications, the integration of SRAM cells and logic cells is not fully suitable for CIM applications. SUMMARY

[0004] The present utility model aims to provide a semiconductor structure to solve at least one of the above problems.

[0005] In one example of an embodiment, the utility model discloses a semiconductor structure. The semiconductor structure includes a memory cell, a signal line, a first voltage line for receiving a supply voltage, and a second voltage line for receiving an electrical ground voltage. The semiconductor structure also includes a logic cell configured to provide logic functionality to the memory cell, wherein the logic cell is connected to the signal line, the first voltage line, and the second voltage line. The semiconductor structure also includes a transition region extending from a first boundary of the memory cell to a second boundary of the logic cell. The semiconductor structure also includes an interconnect structure over the memory cell and the logic cell. The interconnect structure includes the signal line, the first voltage line, and the second voltage line on a same metal line layer of the interconnect structure. The signal line extends from within the second boundary of the logic cell into the first boundary of the memory cell. The transition region includes one or more functional transistors electrically coupled to the memory cell.

[0006] According to one embodiment of the utility model, the memory cell is a static random access memory cell, and the one or more functional transistors in the transition region are electrically coupled to the logic cell.

[0007] According to one embodiment of the utility model, the signal line is a bit line or a complementary bit line.

[0008] According to one embodiment of the utility model, the first boundary of the memory cell has a first width, the second boundary of the logic cell has a second width, and the first width and the second width are equal.

[0009] According to one embodiment of the utility model, the memory cell includes an active region that extends continuously along a first direction through the transition region and into the logic cell, and at least one of the one or more functional transistors in the transition region is formed over the active region.

[0010] According to one embodiment of the utility model, the first voltage line and the second voltage line respectively overlap a first edge and a second edge of the first boundary of the memory cell, and the first edge and the second edge are opposite each other. Also, the first voltage line and the second voltage line respectively overlap a third edge and a fourth edge of the second boundary of the logic cell, and the third edge and the fourth edge are opposite each other.

[0011] In another example of embodiments, the utility model discloses a semiconductor structure. The semiconductor structure includes a memory cell having a first boundary, a logic cell having a second boundary, and an interconnect structure over the memory cell and the logic cell. The interconnect structure includes a signal line extending continuously from within the second boundary of the logic cell into the first boundary of the memory cell along a first direction, and a computing element, wherein the computing element is within the first boundary of the memory cell when viewed from above the semiconductor structure, and the computing element is suspended over the signal line when viewed from the side of the semiconductor structure.

[0012] According to one embodiment of the utility model, the computing element is a metal-insulator-metal capacitor, and the computing element is electrically coupled to an output node of the memory cell.

[0013] According to one embodiment of the utility model, the memory cell includes a first active region and a second active region, the first active region and the second active region extend continuously from within the first boundary of the memory cell into the second boundary of the logic cell along the first direction, and the outline of the computing element overlaps or does not overlap the first active region and the second active region when viewed from above the semiconductor structure.

[0014] In yet another example of embodiments, the utility model discloses a semiconductor structure. The semiconductor structure includes a static random access memory (6T-SRAM) cell having six transistors, the 6T-SRAM cell having a plurality of first metal paths parallel to each other, and a logic cell having a plurality of second metal paths parallel to each other. The number of the first metal paths is the same as the number of the second metal paths. Each of the first metal paths is aligned with one of the second metal paths. One of the second metal paths includes a signal line extending into the 6T-SRAM cell. BRIEF DESCRIPTION OF DRAWINGS

[0015] The complete disclosure of the following description and drawings is hereby incorporated in its entirety by reference. It is emphasized that, according to the general practice of the industry, the illustrations may not necessarily be drawn to scale, and are merely intended for descriptive purposes. In fact, the dimensions of the elements can be arbitrarily increased or decreased in size in order to make the description clear.

[0016] Figure 1A And Figure 1B For block diagrams of a semiconductor device described in accordance with some embodiments of the utility model, the semiconductor device includes a memory macro for compute-in-memory (CIM) applications.

[0017] Figure 2 A circuit diagram of a single-port static random-access memory (SRAM) cell according to some embodiments of the present application.

[0018] Figure 3 A side view of a plurality of layers of a memory device according to some embodiments of the present application.

[0019] Figure 4 And Figure 5 A layout of device layers and metal layers of a SRAM cell according to some embodiments of the present application. Figure 2

[0020] Figure 6 A layout of a metal layer of a logic cell according to some embodiments of the present application.

[0021] Figure 7 A layout of metal layers and active regions of a portion of a memory macro according to some embodiments of the present application.

[0022] Figure 8 A circuit diagram of a CIM circuit according to some embodiments of the present application, the CIM circuit comprising two memory cells.

[0023] Figure 9 A circuit diagram of a multiplier circuit according to some embodiments of the present application.

[0024] Figure 10 A layout of a portion of a memory macro according to some embodiments of the present application, the memory macro for implementing a CIM circuit according to some embodiments of the present application. Figure 8

[0025] Figure 11 A circuit diagram of a memory cell according to some embodiments of the present application, the memory cell comprising a capacitor as a computing element.

[0026] Figure 12 A layout of a portion of a memory macro according to some embodiments of the present application, the memory macro implementing a capacitor as a computing element in each memory cell.

[0027] Reference signs are as follows:

[0028] 10: circuit macro / macro

[0029] 12: static random-access memory (SRAM) array ​​

[0030] 14, 50, 50': SRAM cell

[0031] 16, 500: computation circuitry

[0032] 18: computation element

[0033] 30: SRAM cell block

[0034] 40: logic cell block

[0035] 45: circuit area

[0036] 48: active region transition region / transition region

[0037] 50a: first SRAM cell

[0038] 50b: second SRAM cell

[0039] 52, 54: inverter

[0040] 56: capacitor

[0041] 58: read transistor

[0042] 60: semiconductor substrate / base

[0043] 62: doped region

[0044] 64: insulating feature

[0045] 66: dielectric layer

[0046] 68, 112, 114, 116, 118, 120, 122: gate structure

[0047] 70: suspended channel layer

[0048] 72: source / drain

[0049] 74: gate electrode

[0050] 76: gate dielectric

[0051] 78: gate spacer

[0052] 80: device element

[0053] 80a: top electrode

[0054] 80b: dielectric layer

[0055] 80c: bottom electrode

[0056] 100, 200, 300, 600, 700: layout

[0057] 102, 104: active region

[0058] 140: boundary

[0059] 150C, 150D, 150E, 150F: gate contacts

[0060] 160A, 160B, 160C, 160D, 160E, 160F, 160G, 160H: source / drain contacts

[0061] 170C, 170D, 170E, 170F, 170G, 170H: source / drain contact vias

[0062] 108A, 180G: global metal line

[0063] 180B, 180C, 180D, 180E, 180F: local metal line

[0064] 202: cell boundary

[0065] 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7, 204-8, 204-9, 204-10, 204-11: metal line

[0066] 400: compute-in-memory (CIM) circuit

[0067] 402: word line driver

[0068] 404: multiplier circuit

[0069] 406, 408, 414: NAND gate

[0070] 410: first OR gate

[0071] 412: second OR gate

[0072] PG-1, PG-2: pass-gate transistor

[0073] PU-1, PU-2: pull-up transistor

[0074] PD-1, PD-2: pull-down transistor

[0075] VDD, VSS: power supply voltage

[0076] CD1: first common drain

[0077] CD2: second common drain

[0078] SN: storage node

[0079] SNB: storage node / complementary storage node

[0080] BL: bit line

[0081] BLB: complementary bit line / bit line

[0082] WL: word line

[0083] DL: device layer

[0084] MLI: multi-layer interconnect structure

[0085] T: transistor

[0086] MD: source / drain contact

[0087] VD: source / drain via

[0088] W, CW: cell width

[0089] H, CH: cell height

[0090] S1: spacing

[0091] Wa, Wb: width

[0092] XIN: input signal

[0093] XINB: inverted input signal

[0094] RSEL[0], RSEL[1]: read select signal

[0095] RWLB[0], RWLB[1]: read word line signal

[0096] DB[0], DB[1]: data signal

[0097] OUT: output signal

[0098] P0, P1, P2, P3: PMOS transistor

[0099] N0, N1, N2, N3: NMOS transistor

[0100] RBL: first read bit line

[0101] RWL: first read word line

[0102] WL1P, WL1N, WL2P, WL2N: control signal DETAILED DESCRIPTION

[0103] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Some of these embodiments can be discussed to provide a context for discussing the various features. Of course, it should be understood that these are merely examples and are not intended to limit the scope of the application. For example, when a first feature is described as being formed on or over a second feature, this can include embodiments where the first feature is formed directly on the second feature, as well as embodiments where additional features can be formed between the first and second features such that the first and second features are not directly in contact. Also, the various embodiments can use the same reference numerals for similar elements, and / or like Symbology. Such repetition is for the purpose of simplicity and clarity and is not intended to limit the scope of the various embodiments or the structural relationships of the various embodiments to one another. Furthermore, in the following description of various embodiments, numerous specific details are discussed to provide a thorough understanding of the embodiments. However, it will be apparent to one of ordinary skill in the art that embodiments can be practiced without these specific details. In other instances, well-known methods have not been described in detail in order to avoid unnecessarily obscuring the embodiments. Also, although the term "exemplary" can be used in connection with various examples, it should be understood that the term "exemplary" is intended to be used only in the sense of providing an example, and not in the sense of being an ideal or perfect example.

[0104] In addition, the present application can repeat reference signs and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed. Furthermore, in the following description of various embodiments, the formation of a feature on, connected to, and / or coupled to another feature can include embodiments where the feature is formed directly on the other feature, and also embodiments where additional features can be formed between the feature and the other feature such that the feature can not be directly in contact with the other feature. Moreover, spatially relative terms, such as "under", "above", "horizontal", "vertical", "up", "down", "top", "bottom", "side", and the like, are used for the purpose of describing the relationship of one element to another element(s) as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. Further, the spatially relative terms can be used herein for purposes of

[0105] The present application relates to compute-in-memory (CIM) systems and, more particularly, to integration of memory cells and logic cells for CIM applications. A CIM system stores information in memory (e.g., a computer's random-access memory (RAM)) and performs computations on a hierarchy of memory cells, rather than moving large amounts of data between memory and a processor at each computational step. Because data is accessed and processed in the same memory, programs run faster, enabling faster response and decision-making for business and machine learning applications. Efforts are being made to improve the performance of CIM systems.

[0106] Artificial intelligence (AI) uses deep learning techniques in which a computer system can be organized as a neural network with multiple interconnected processing nodes to enable data analysis. Neural networks include multiple layers of computing nodes, with lower layers computing based on results of computations performed by higher layers. Further, in some neural networks, weights are computed and used to compute on input data.

[0107] AI systems include machine learning systems in which computer algorithms improve automatically with experience and data accumulation. Machine learning algorithms build models based on sample data (i.e., training data) to make predictions or decisions without being directly programmed. In these systems, input data is compared to training data, i.e., the attributes of known data (e.g., training data) are computationally analyzed. Examples of systems can be found in the field of object recognition in which the system analyzes attributes of a plurality of known images (e.g., one thousand or more images) to determine patterns that can be used to statistically analyze input images / objects for recognition. In some embodiments, the AI system is referred to as a convolutional neural network (CNN).

[0108] Machine learning is very computationally intensive, where machine learning neural networks compute weights to compute on input data. Machine learning includes performing inner product computations and absolute difference computations on multiple vectors, where the inner product computations and absolute difference computations can be computed by multiply-accumulate (MAC) operations on data, which can be input data or weights. Computing on large and deep neural networks involves multiple data elements, such that storing data into a processor cache memory is not practical because the memory size of the processor cache memory and the cost of the cache memory is very expensive. Furthermore, transferring data between other memory sources, such as between a RAM and a processor, is very time consuming and becomes a bottleneck for machine learning systems. Moreover, as the size of the data set increases, the time to move the data and the energy / power consumption becomes several times more than the computation using the processor.

[0109] Accordingly, CIM circuits are developed for performing neural network computations. CIM circuits perform local operations by a memory without the need to send data to a host processor. This reduces the amount of data transfer between the memory and the host processor, resulting in higher throughput and efficiency. Furthermore, reducing the amount of data transfer also reduces the energy / power consumed by the system.

[0110] In some CIM systems, a memory array includes a plurality of memory cells (e.g., static random-access memory (SRAM) cells) for storing weight data and a plurality of logic cells (e.g., standard cells including inverters (INV) and AND, OR, NAND, NOR, NOT, scan, etc.) for providing logic (e.g., input / output (I / O)) functions. During the integrated circuit (IC) design process, a designer takes the needed cells from a cell library and places them at desired locations. Then, routing is performed to establish connections between the memory cells and the logic cells, thereby producing the desired IC. For example, an SRAM structure typically includes a multi-layer interconnect structure to provide metal paths (e.g., metal lines) for interconnecting a plurality of memory cells and logic cells with a plurality of power lines and signal lines therebetween. However, the interconnect structure can be composed of one set of metal paths in the memory region and another set of metal paths in the logic region, which are typically not the same paths and thus not directly connected. Therefore, to connect with the upper metal layers, metal transitions are needed to electrically connect the metal paths in the memory region and the logic region. Such metal transitions increase the resistance and capacitance values in the interconnect structure and cause performance, yield, and cost challenges. According to observations, in advanced IC technology nodes, these higher resistance and / or higher capacitance values due to the interconnects can significantly delay (and in some cases, can also block) signals from being effectively routed to or from the IC devices (e.g., transistors), thereby negatively impacting the improved performance of the IC devices in advanced technology nodes. Such transistors can be implemented in edge cells inserted between the memory region and the logic region, but also consume valuable area on the chip and increase production costs. Thus, the integration of memory cells and logic cells for CIM applications has not yet fully met all needs.

[0111] Reference will now be made to Figure 1A and Figure 1B As shown, a circuit macro (and hereinafter referred to as a macro) 10 is depicted. The macro 10 can be located in a semiconductor device (or an IC). In some embodiments, the macro 10 is a static random-access memory (SRAM) macro. The macro 10 includes a memory region 12 and a logic region 14. The memory region 12 includes a plurality of memory cells 16 (e.g., SRAM cells) for storing weight data. The logic region 14 includes a plurality of logic cells 18 (e.g., standard cells including inverters (INV) and AND, OR, NAND, NOR, NOT, scan, etc.) for providing logic (e.g., input / output (I / O)) functions.

[0112] The macro 10 is shown as a single-port SRAM macro, a dual-port SRAM macro, or other types of SRAM macros. However, the present disclosure contemplates embodiments in which the macro 10 is other types of memory, such as a dynamic random-access memory (DRAM), a non-volatile random-access memory (NVRAM), a flash memory, or other suitable memory. Figure 1A and Figure 1B The present disclosure has been simplified to better understand the innovative technology. Additional features can be added to the macro 10, and some features of the macro 10 described below can be replaced, adjusted, or removed in other embodiments.

[0113] In some embodiments, the macro 10 includes memory cells and peripheral circuits. The memory cells, also referred to as bit cells, are configured to store memory bits. The peripheral cells, also referred to as logic cells, are interspersed among the bit cells and are configured to perform various logic functions. For example, the logic functions of the logic cells include write and / or read decoding, word line selection, bit line selection, data driving, and memory self-test. Various logic functions of the logic cells are contemplated by the present disclosure.

[0114] Figure 1A An embodiment of a CIM structure is shown, in which a SRAM array 12 and additional compute circuitry 16 are interconnected to facilitate CIM programming. The SRAM cells 14 are distributed into columns and rows of an array, where each SRAM cell 14 can store a bit of data. Column circuitry selects specific SRAM columns for data fetch or memory programming, while row circuitry is interconnected with the SRAM rows. A controller directs the overall programming of the SRAM array 12, including data flow to and from the compute circuitry 16. The compute circuitry 16 is proximate to the SRAM array 12 and is used to perform the programming operations necessary for neural network inference tasks on data fetched from the memory cells, such as multiply-accumulate (MAC) functions. Such integration allows for data processing directly in memory, reducing the need to transfer data between memory and a separate processor, thereby improving the speed and efficiency of data center appliances.

[0115] Figure 1BAnother embodiment of a CIM structure is described, in which the compute circuit 16 is further divided into multiple compute elements 18 integrated to each SRAM cell 14. Such granular integration allows for parallel program processing within the memory array, thereby increasing compute density and efficiency. Each SRAM cell 14 not only stores data, but actively participates in computation, thus enabling significant speedup of tasks commonly used in machine learning applications, such as vector matrix multiplication. Figure 1B The column circuitry, row circuitry, and controller in the memory array of FIG. 1 maintain their respective roles of managing selection of columns and overall operation of the array. However, these peripheral circuits now play a more important role in input and output signals to and from the computations in the SRAM cells. Such a structural adjustment reinforces the array's ability to perform in-memory computations, making the array more suitable for tasks of intensive digital signal processing and in-memory computations.

[0116] In the macro 10, the plurality of transistors in the memory cells and logic cells can be implemented as a plurality of P-type transistors and N-type transistors, such as planar transistors or non-planar transistors, including, for example, Fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, or combinations thereof. GAA transistors are transistors having a gate electrode wrapped around a channel of the transistor, such as vertical stack gate-all-around horizontal nanowire or nanosheet metal oxide semiconductor field effect transistor (MOSFET) devices. The following description of the present disclosure will continue with one or more GAA examples to describe embodiments of the present disclosure. However, it should be understood that the application is not limited to one particular type of device, unless specifically limited. For example, embodiments of the present disclosure can also be applied to FinFET or planar FET-based implementations.

[0117] Figure 2A circuit diagram of one example of SRAM cell 50, which can be implemented as a memory cell of a SRAM array, is shown in accordance with embodiments of the present application. In some embodiments, SRAM cell 50 is implemented as SRAM cell 14 of macro 10 (FIG. 1). In the illustrated embodiment, SRAM cell 50 is a single-port (SP) 6-transistor (6T) SRAM (6T-SRAM) cell. In various embodiments, SRAM cell can be other types of memory cells, such as dual-port memory cells or memory cells having more than 6 transistors. Figure 2 The present application has been simplified to better understand the innovative technology. Additional features can be added to single-port SRAM cell 50, and some features can be substituted, adjusted, or removed in other embodiments of single-port SRAM cell 50 as described below.

[0118] The example SRAM cell 50 is a single-port SRAM cell including six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. During operation, pass-gate transistors PG-1 and PG-2 provide access to a storage portion of SRAM cell 50, which includes a pair of cross-coupled inverters 52 and 54. Inverter 52 includes pull-up transistor PU-1 and pull-down transistor PD-1, while inverter 54 includes pull-up transistor PU-2 and pull-down transistor PD-2. In some embodiments, pull-up transistors PU-1, PU-2 are configured as P-type FinFET or P-type GAA transistors, while pull-down transistors PD-1, PD-2 are configured as N-type FinFET or N-type GAA transistors.

[0119] A gate of pull-up transistor PU-1 is between a source (electrically coupled to a power supply voltage (VDD)) and a first common drain (CD1), and a gate of pull-down transistor PD-1 is between a source (electrically coupled to a power supply voltage (VSS), which is typically an electrically grounded voltage) and the first common drain. A gate of pull-up transistor PU-2 is between a source (electrically coupled to the power supply voltage (VDD)) and a second common drain (CD2), and a gate of pull-down transistor PD-2 is between a source (electrically coupled to the power supply voltage (VSS)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) that stores data in true form, and the second common drain (CD2) is a complementary storage node (SNB) that stores data in complement form. The gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 are coupled to the second common drain (CD2), and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 are coupled to the first common drain (CD1). A gate of pass-gate transistor PG-1 is between a source (electrically coupled to a bit line BL) and a drain (electrically coupled to the first common drain (CD1)). A gate of pass-gate transistor PG-2 is between a source (electrically coupled to a complementary bit line BLB) and a drain (electrically coupled to the second common drain (CD2)). In the following, the bit line BL and the complementary bit line BLB can be collectively referred to as a bit line unless otherwise indicated. The gates of pass-gate transistors PG-1, PG-2 are electrically coupled to a word line WL. In some embodiments, the pass-gate transistors PG-1, PG-2 provide access to the storage node SN and the complementary storage node SNB during read and / or write operations. For example, the pass-gate transistors PG-1, PG-2 couple the storage node SN and the complementary storage node SNB to the bit line BL, BLB, respectively, in response to a voltage provided to the gates of the pass-gate transistors PG-1, PG-2 by the word line WL.

[0120] Figure 3 A side view of components of a plurality of layers (or tiers) fabricated on a semiconductor substrate (or wafer) 60 according to embodiments of the present disclosure, wherein the layers (or tiers) are used to form a portion of a memory (e.g., the aggregate 10 of FIG. 1) and / or a SRAM cell (e.g., the SRAM cell 50 of FIG. 1). Figure 2 A side view of components of a plurality of layers (or tiers) fabricated on a semiconductor substrate (or wafer) 60 according to embodiments of the present disclosure, wherein the layers (or tiers) are used to form a portion of a memory (e.g., the aggregate 10 of FIG. 1) and / or a SRAM cell (e.g., the SRAM cell 50 of FIG. 1). Figure 3In some embodiments, the device layer DL includes a substrate 60, a plurality of doped regions 62 (e.g., N-wells and / or P-wells) in the substrate 60, a plurality of insulating features 64, and a plurality of transistors T. In the described embodiments, the transistors T include a plurality of suspended channel layers 70 and a plurality of gate structures 68 between source / drain 72, where the gate structures 68 wrap around and / or surround the suspended channel layers 70. Each gate structure 68 has a metal gate stack formed by a gate electrode 74, where the gate electrode 74 is on a gate dielectric 76 and a plurality of gate spacers 78 on both sides of the metal gate stack. The multilayer interconnect structure MLI is electrically coupled to the devices and / or components of the device layer DL such that the devices and / or components can be operated in a particular state as required by the memory design.

[0121] In described embodiments, a multilayer interconnect structure MLI includes a contact (CO) layer (or CO level), a via zero (V0) layer (or V0 level), a metal zero (M0) layer (or M0 level), a via one (V1) layer (or V1 level), a metal one (M1) layer (or M1 level), a via two (V2) layer (or V2 level), a metal two (M2) layer (or M2 level), a via three (V3) layer (or V3 level), a metal three (M3) layer (or M3 level), and so on up to a via x (Vx) layer (or Vx level) and a metal x (Mx) layer (or Mx level). The present disclosure contemplates that a multilayer interconnect structure MLI can have more or fewer layers and / or levels, for example, a multilayer interconnect structure MLI can have a total of N (e.g., N = x + 1) metal layers (or levels), where N is a positive integer from 2 to 10. Each level of a multilayer interconnect structure MLI includes a plurality of conductive features (e.g., metal lines, metal vias, and / or metal contacts) located in one or more dielectric layers (an interlayer dielectric (ILD) layer) and a contact etch stop layer (CESL). In some embodiments, conductive features of the same level of a multilayer interconnect structure MLI (e.g., M0 level) are formed simultaneously. In some embodiments, conductive features of the same level of a multilayer interconnect structure MLI have a top layer and / or a bottom layer that is substantially coplanar with other conductive features of the same level.The CO tier includes a plurality of source / drain contacts (MD) in a dielectric layer 66; the VO tier includes a plurality of gate vias VG, a plurality of source / drain contact vias VD, and a plurality of landing pads in the dielectric layer 66; the MO tier includes a plurality of MO metal lines in the dielectric layer 66, wherein the gate vias VG connect a plurality of gate structures to the MO metal lines, the source / drain contact vias VD connect a plurality of source / drain contacts to the MO metal lines, and the landing pads connect the gate structures and the source / drain contacts together to the MO metal lines; the VI tier includes a plurality of VI vias in the dielectric layer 66, wherein the VI vias connect the MO metal lines to the Ml metal lines; the Ml tier includes a plurality of Ml metal lines in the dielectric layer 66; the V2 tier includes a plurality of V2 vias in the dielectric layer 66, wherein the V2 vias connect the Ml metal lines to the M2 metal lines; the M2 tier includes a plurality of M2 metal lines in the dielectric layer 66; the V3 tier includes a plurality of V3 vias in the dielectric layer 66, wherein the V3 vias connect the M2 metal lines to the M3 metal lines; and so on, until the plurality of Vx vias and the plurality of Mx metal lines.

[0122] In the described embodiment, the multilayer interconnect structure MLI further includes one or more device elements 80 over the transistors T, wherein the device elements 80 are also electrically connected through metal lines and vias and the source / drain 72 of the transistors T. For example, in some embodiments, the device elements can be configured as a capacitor or other semiconductor device, wherein the capacitor can be a metal-insulator-metal (MIM) capacitor, and in an example, the MIM capacitor includes at least a top electrode 80a, a bottom electrode 80c, and a dielectric layer 80b stacked between the top electrode 80a and the bottom electrode 80c. Further in other embodiments, each SRAM cell can have a corresponding MIM capacitor formed within the SRAM cell in a top view, but above the SRAM cell in a side view. The device elements 80 can be Figure 1B a compute element 18 or a portion of a compute element 18, and in one SRAM cell in the CIM system. Figure 3 The features have been simplified to better illustrate the innovative technology of the present disclosure. Additional features can be added to the tiers of the memory, and some of the illustrated features can be substituted, modified, or eliminated in other embodiments of the memory. Figure 3 This is merely an example, and does not reflect the true side view of the macro 10 and / or the SRAM cell 50 described in more detail below.

[0123] Figure 4 and Figure 5 An example of a layout 100 of the SRAM cell 50 is described, wherein Figure 2 the SRAM cell 50 includes a plurality of transistors T, a plurality of source / drain contacts 72, a plurality of gate structures 74, a plurality of landing pads 76, a plurality of MIM capacitors 80, and a plurality of metal lines 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180, 182, 184, 186, 188, 190, 192, 194, 196, 198, 200, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250, 252, 254, 256, 258, 260, 262, 264, 266, 268, 270, 272, 274, 276, 278, 280, 282, 284, 286, 288, 290, 292, 294, 296, 298, 300, 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, 334, 336, 338, 340, 342, 344, 346, 348, 350, 352, 354, 356, 358, 360, 362, 364, 366, 368, 370, 372, 374, 376, 378, 380, 382, 384, 386, 388, 390, 392, 394, 396, 398, 400, 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 422, 424, 426, 428, 430, 432, 434, 436, 438, 440, 442, 444, 446, 448, 450, 452, 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476, 478, 480, 482, 484, 486, 488, 490, 492, 494, 496, 498, 500, 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, 556, 558, 560, 562, 564, 566, 568, 570, 572, 574, 576, 578, 580, 582, 584, 586, 588, 590, 592, 594, 596, 598, 600, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, 634, 636, 638, 640, 642, 644, 646, 648, 650, 652, 654, 656, 658, 660, 662, 664, 666, 668, 670, 672, 674, 676, 678, 680, 682, 684, 686, 688, 690, 692, 694, 696, 698, 700, 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, 726, 728, 730, 732, 734, 736, 738, 740, 742, 744, 746, 748, 750, 752, 754, 756, 758, 760, 762, 764, 766, 768, 770, 772, 774, 776, 778, 780, 782, 784, 786, 788, 790, 792, 794, 796, 798, 800, 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 824, 826, 828, 830, 832, 834, 836, 838, 840, 842, 844, 846, 848, 850, 852, 854, 856, 858, 860, 862, 864, 866, 868, 870, 872, 874, 876, 878, 880, 882, 884, 886, 888, 890, 892, 894, 896, 898, 900, 902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, 924, 926, 928, 930, 932, 934, 936, 938, 940, 942, 944, 946, 948, 950Figure 4 The DL, CO, and VO tiers of the layout 100 are described, while Figure 5 The VO and M0 tiers of the layout 100 are described. The SRAM cell 50 includes a plurality of active regions 102 and 104. In Figure 4 In the described embodiment, the active regions 102, 104 extend lengthwise along the X direction. In the described embodiment, the active regions 104 belong to pull-up transistors PU-1 and PU-2, which are P-type MOS (PMOS) devices. Thus, the active regions 104 are formed over an N-type well. Meanwhile, the active regions 102 belong to pass-gate transistors PG-1, PG-2 and pull-down transistors PD-1, PD-2, which are N-type MOS (NMOS) devices. Thus, the active regions 102 are formed over a P-type well (or a P-type substrate).

[0124] The SRAM cell 50 also includes a plurality of gate structures 112, 114, 116, 118, 120, and 122. The gate structures 112-122 extend lengthwise along the Y direction. The gate structures 112 and 120 each extend across the active regions 102 to form the pass-gate transistors PG-2 and PG-1, respectively. The gate structures 114 and 116 each extend across two active regions 102, 104. Thus, the gate structure 114 is shared by the pull-down transistor PD-1 and the pull-up transistor PU-1, while the gate structure 116 is shared by the pull-down transistor PD-2 and the pull-up transistor PU-2. The gate structures 118 and 122 each extend across the active regions 104. However, the gate structures 118 and 122 are non-functional gates, and the transistors formed between the gate structures 118, 122 and the active regions 104 are also non-functional transistors. For example, the gate structures 118 and 122 are electrically floated or tied to a fixed voltage.

[0125] A dashed rectangular box is used to depict a boundary 140 of the SRAM cell 50. It should be noted that some active regions and gate structures can extend beyond the depicted boundary 140 as they can also be used to form other adjacent SRAM cells. The boundary 140 is longer in the X direction than in the Y direction. A first dimension of the boundary 140 along the X direction is denoted as a cell width W, and a second dimension of the boundary 140 along the Y direction is denoted as a cell height H. When the SRAM cell 50 is repeated in a memory array, the cell width W can represent and be referred to as a memory cell pitch of the memory array along the X direction, and the cell height H can represent and be referred to as a memory cell pitch of the memory array along the Y direction.

[0126] The cell size of the SRAM cell 50 is W x H, where the cell width W is about four times a poly pitch (e.g., the distance between the centers of two adjacent gate structures in the X direction), and the cell height H is about twice an isolation pitch (e.g., the distance between the centers of two shallow trench isolation (STI) features in the Y direction). The area of a poly pitch multiplied by an isolation pitch is a unit area, and each unit area includes interleaved portions of a gate structure and an active region, and the SRAM cell 50 utilizes eight times the cell size of a unit area to accommodate six functional transistors, which are the pass-gate transistors PG-1 and PG-2, the pull-up transistors PU-1 and PU-2, and the pull-down transistors PD-1 and PD-2.

[0127] A gate contact 150C electrically connects a gate (formed by the gate structure 112) of the pass-gate transistor PG-2 to a node of the word line (WL). A gate contact 150D electrically connects a gate (formed by the gate structure 120) of the pass-gate transistor PG-1 to a node of the word line (WL). A gate contact 150E electrically connects a gate (formed by the gate structure 114) of the pull-down transistor PD-2 and a gate (also formed by the gate structure 114) of the pull-up transistor PU-2 to the storage node (SN). A gate contact 150F electrically connects a gate (formed by the gate structure 116) of the pull-down transistor PD-1 and a gate (also formed by the gate structure 116) of the pull-up transistor PU-1 to the complementary storage node (SNB).

[0128] A source / drain contact 160A and a source / drain contact 160B are located on the source / drain regions of the non-functional transistor and remain electrically floating because no contact via is located on the corresponding source / drain. A source / drain contact 160C and a source / drain contact via 170C electrically connect a source region of pass-gate transistor PG-2 to a node of the complementary bit line (BLB). A source / drain contact 160D and a source / drain contact via 170D electrically connect a source region of pass-gate transistor PG-1 to a node of the bit line (BL). A source / drain contact 160E and a source / drain contact via 170E electrically connect a common drain region of pass-gate transistor PG-2 and pull-down transistor PD-2 and a drain region of pull-up transistor PU-2 to the complementary storage node (SNB). A source / drain contact 160F and a source / drain contact via 170F electrically connect a common drain region of pass-gate transistor PG-1 and pull-down transistor PD-1 and a drain region of pull-up transistor PU-1 to the storage node (SN). A source / drain contact 160G and a source / drain contact via 170G electrically connect a common source region of pull-down transistor PD-1 and pull-down transistor PD-2 to a node electrically grounded (power supply voltage VSS). A source / drain contact 160H and a source / drain contact via 170H electrically connect a common source region of write-port pull-up transistor PU-1 and write-port pull-up transistor PU-2 to a node of the power supply voltage (power supply voltage VDD). In the described embodiment, the source / drain contacts are elongated in the Y direction in a longitudinal direction parallel to the elongation direction of the gate structure.

[0129] The storage node SN includes a gate contact 150E and a source / drain contact via 170F located on either side of the gate structure 116. In more detail, a metal line in the M0 tier extends along the X direction to span the gate structure 116 and connect the gate contact 150E and the source / drain contact via 170F. In other words, a M0 metal line overhangs the gate structure 116 and provides a cross-coupling function between the gate contact 150E and the source / drain contact via 170F. Thus, in the layout 100, the gate contact 150E and the source / drain contact via 170F are located horizontally in the Y direction such that a metal line extending along the X direction can connect the two. Similarly, a complementary storage node (or inverted storage node) SNB includes a gate contact 150F and a source / drain contact via 170E located on either side of the gate structure 114. In more detail, another metal line in the M0 tier extends along the X direction to span the gate structure 114 and connect the gate contact 150F and the source / drain contact via 170E. In other words, another M0 metal line overhangs the gate structure 114 and provides a cross-coupling function between the gate contact 150F and the source / drain contact via 170E. Thus, in the layout 100, the gate contact 150F and the source / drain contact via 170E are located horizontally in the Y direction such that a metal line extending along the X direction can connect the two.

[0130] Figure 5 The V0 tier and the M0 tier of the layout 100 of the metal interconnect structure of the SRAM cell 50 are shown. In the M0 tier, the SRAM cell 50 includes metal paths assigned in a parallel arrangement. In particular, in the described embodiment of the layout 100, the SRAM cell 50 includes 6 metal paths arranged along the Y direction from a first metal path (M0 path 1) to a sixth metal path (M0 path 6). In the described embodiment of the layout 100, the metal paths are assigned in a parallel arrangement in the Y direction. In other words, the metal paths are arranged in a parallel arrangement in the Y direction. In the described embodiment of the layout 100, the metal paths are assigned in a parallel arrangement in the Y direction. In other words, the metal paths are arranged in a parallel arrangement in the Y direction. Figure 5 In the described embodiment of the layout 100, the midline of the metal paths is represented by a dotted line.

[0131] In layout 100, the first metal path "M0 Path 1" includes a global metal line 180A, which is a metal line connected to the power supply voltage VSS electrically coupled to the source / drain contact via 170G. The term "global metal line" refers to a metal line that runs along the X-direction through the entire SRAM cell 50. Conversely, it is referred to as a "local metal line." The global metal line 180A is located at an upper edge of the SRAM cell 50 and can be shared with an adjacent SRAM cell. The second metal path "M0 Path 2" includes a local metal line 180B for a landing pad for a word line (WL). The local metal line 180B is entirely located within the SRAM cell 50 and is electrically connected to gate contact 150C and gate contact 150D. The third metal path "M0 Path 3" includes two local metal lines 180C and 180D. The local metal line 180C provides a landing pad for a bit line bar (BLB). The local metal line 180C extends beyond a left side edge of the SRAM cell 50 and can be shared with an adjacent SRAM cell. The local metal line 180D provides a landing pad for a bit line (BL). The local metal line 180D extends beyond a right side edge of the SRAM cell 50 and can be shared with an adjacent SRAM cell. The fourth metal path "M0 Path 4" includes a local metal line 180E. The local metal line 180E is entirely located within the SRAM cell 50, where the local metal line 180E belongs to a complementary storage node (SNB) and provides cross-coupling between gate contact 150F and source / drain contact via 170E. As described above, the local metal line 180E crosses over the gate structure 114. The fifth metal path "M0 Path 5" includes a local metal line 180F. The local metal line 180F is entirely located within the SRAM cell 50, where the local metal line 180F belongs to a storage node (SN) and provides cross-coupling between gate contact 150E and source / drain contact via 170F. As described above, the local metal line 180F crosses over the gate structure 116. The sixth metal path "M0 Path 6" includes a global metal line 180G, which is a metal line connected to the power supply voltage VDD electrically coupled to the source / drain contact via 170H. The global metal line 180G is located at a lower edge of the SRAM cell 50 and can be shared with an adjacent SRAM cell.

[0132] A width of global metal line 180A is denoted as Wa, where half of the width Wa is in one SRAM cell and the other half is in an adjacent SRAM cell. A width of global metal line 180G can be practically the same as global metal line 180A, i.e., half in one SRAM cell and the other half in an adjacent SRAM cell. Other M0 metal lines (local metal lines 180B-180F) each have the same width denoted as Wb. A spacing between two adjacent M0 metal lines can be uniform and denoted as S1. Thus, a cell height H of the SRAM is equal to Wa+4*Wb+5*S1. Layout 100 of SRAM cell 50 has a cell height H corresponding to six metal paths. Details are described below in more detail, Figure 6 The illustrated SRAM cell 50 and logic cell can have the same cell height to allow each SRAM cell 50 to abut against one logic cell.

[0133] SRAM cell 50 can be fabricated in the same memory macro (e.g., macro 10 in FIG. 1) as a logic cell (commonly referred to as a standard cell). In such embodiments, the metal lines of the M0 level of SRAM cell 50 and the metal lines of the M0 level of the logic cell can be configured to optimize SRAM performance and logic density (i.e., jointly optimize). For example, Figure 6 A plurality of metal lines of a layout 200 according to embodiments of the present disclosure, where layout 200 is of the M0 level of two logic cells configured in a Y direction. The two logic cells each have a cell boundary 202 and are represented by dashed rectangular boxes. Cell boundary 202 has a first dimension (e.g., a cell width CW) along a first direction (e.g., an X direction) and a second dimension (e.g., a cell height CH) along a second direction (e.g., a Y direction).

[0134] The MO layer of a logic cell includes multiple metal lines electrically connected to a device layer. The device layer of the logic cell includes multiple transistors, such as N-type and P-type transistors, and has a gate located between a source and a drain, wherein the MO layer of the logic cell is electrically connected to at least one gate, at least one source, and / or at least one drain of the transistors. In some embodiments, the gates of the transistors of the logic cell extend in the same direction (vertical) as the gates in the SRAM cell 50, and the metal lines of the MO layer of the logic cell have a winding direction substantially perpendicular to the gate extension direction. In some embodiments, two adjacent logic cells have a total of 2*N+1 (i.e., an odd number) metal lines arranged in the Y direction, where N is a positive integer. In the described embodiment, N equals 5, and the two adjacent logic cells have 11 metal lines, designated as metal lines 204-1 to 204-11. In several embodiments, N may be a positive integer other than 5, such as 4 or 6. In some embodiments, two abutting logic units can be functionally viewed as a single logic unit having a unit height H, a unit width W, and 2*N+1 metal lines.

[0135] The metal lines in the M0 layer can each be configured on a corresponding metal track. Within the M0 layer, the SRAM structure may include multiple metal tracks configured to be parallel to each other (e.g., from track 1 to track 2*N+1). In the embodiment of the described layout 200, the logic cell includes 11 metal tracks arranged along the Y direction from the first (M0 track 1) to the eleventh (M0 track 11). The centerline of the metal track is... Figure 6 The dashed lines in the text represent...

[0136] In the described embodiment, the central metal path (i.e., the (N+1)th metal path, or in...) Figure 6 The middle path (M0 path 6) includes a metal wire (e.g.: Figure 6 Metal wire 204-6 in the above-mentioned metal wire is designated to be connected to the power supply voltage VSS. Two metal paths counting to the side from the central metal path (i.e., the (N-1)th metal path or the (N+3)th metal path, or in... Figure 6 The middle part (M0 path 4 or M0 path 8) includes a metal wire (e.g.: Figure 6 Metal line 204-4 or metal line 204-8 is designated as a signal line coupled to SRAM cell 50, wherein the aforementioned signal line is a bit line BL or complementary bit line (also known as reverse bit line) BLB. The first and last metal paths (the first and (2*N+1)th metal paths, or in...) Figure 6 M0 path 1 and M0 path 11 each include a metal wire (e.g., in...) Figure 6The metal lines of the M0 tier are evenly distributed along the Y direction with a pitch S1. The width of the metal line 204-1 (and 204-11) is Wa. The width of the metal line 204-6 can be practically the same as the width Wa of the metal line 204-1 (and 204-11). The other M0 metal lines can have the same width Wb as each other. Thus, the cell height CH of the logic cell is equal to Wa+4*Wb+5*S1, and is equal to the cell height H of the SRAM cell (i.e., H = CH), so that each logic cell can abut the SRAM cell 50 through the M0 metal paths, and so that the corresponding M0 metal lines between the SRAM cell 50 and the logic cell are aligned with each other.

[0137] The metal lines of the M0 tier are evenly distributed along the Y direction with a pitch S1. The width of the metal line 204-1 (and 204-11) is Wa. The width of the metal line 204-6 can be practically the same as the width Wa of the metal line 204-1 (and 204-11). The other M0 metal lines can have the same width Wb as each other. Thus, the cell height CH of the logic cell is equal to Wa+4*Wb+5*S1, and is equal to the cell height H of the SRAM cell (i.e., H = CH), so that each logic cell can abut the SRAM cell 50 through the M0 metal paths, and so that the corresponding M0 metal lines between the SRAM cell 50 and the logic cell are aligned with each other.

[0138] In some memory structures, the metal paths (and the respective metal lines of each metal path) in the SRAM cell and the logic cell are not aligned. One solution is to add one or more edge cells between the SRAM cell and the logic cell. In these edge cells, metal transitions are provided to electrically couple the metal lines of the M0 tier to other metal lines of higher tiers (e.g., M1 tier and / or M2 tier) to implement a bridge for connecting the signal lines in the SRAM cell and the logic cell. However, such metal transitions undesirably increase the wire resistance and parasitic capacitance of the signal lines, which are already sensitive to impedance and capacitance, thus increasing the resistance capacitance (RC) delay and reducing the speed (e.g., write / read speed) of the SRAM. Adding edge cells also wastes valuable layout space. In Figure 5 and Figure 6 In the described embodiments, the metal paths (and the corresponding metal lines) between the SRAM cell 50 and the logic cell are aligned, which allows the signal lines and the power lines to be directly extended from the logic cell into the SRAM cell 50 without additional metal transitions. The direct metal line connections reduce the wire resistance and parasitic capacitance, which simplifies the circuit layout, improves the circuit speed, and increases the layout space utilization.

[0139] Figure 7A layout 300 of a circuit region 45 in the macro 10 (Fig. 1) is shown, which includes a portion of the SRAM cell block 30 and a portion of the logic cell block 40, and extends across an interface between the SRAM cell block 30 and the logic cell block 40. The SRAM cell block 30 can be a portion of the SRAM array 12 (Fig. 1), and the logic cell block 40 can be a portion of the peripheral circuitry (e.g., column circuitry, row circuitry, and controller in Fig. 1). Figure 7 The present disclosure has been simplified to better understand the innovative technology. For example, only active regions in the DL level and metal lines in the V0 level are shown, while other features (e.g., gate structures, contacts, and vias) are omitted in the drawings. Figure 7

[0140] As mentioned above, the SRAM cells 50 and the logic cells can have the same cell height (e.g., H = CH). Figure 7 One row of two SRAM cells each is described, in which a first SRAM cell 50a abuts a first logic cell, and a second SRAM cell 50b abuts a second logic cell. The adjacent first and second SRAM cells 50a and 50b exhibit line symmetry with respect to a row boundary between them. That is, the second SRAM cell 50b is a flipped copy of the first SRAM cell 50a in the X-axis direction.

[0141] The active regions 102 and 104 in the SRAM cell block 30 are arranged to have long sides in the X direction and are evenly distributed in the Y direction. The active regions in the logic cell 40 are also arranged to have long sides in the X direction and are evenly distributed in the Y direction. In addition, the active regions in the SRAM cell block 30 and the logic cell block 40 have the same width and pitch. Thus, the active regions in the SRAM cell block 30 and the logic cell block 40 can be aligned. In addition, in the described embodiment, the active regions extend across the interface between the SRAM cell block 30 and the logic cell block 40. In other words, the transistors of the SRAM cell block 30 and the logic cell block 40 can share the same and continuous active regions.

[0142] ​The metal paths in the SRAM cell block 30 are also aligned with the metal paths in the logic cell block 40, thereby allowing the metal lines in the logic cells to extend into the SRAM cells. Thus, no edge cells are needed between the SRAM cell block 30 and the logic cell block 40 to provide metal transitions to the M0 level metal lines. M0 path 1 includes a metal line connected to the power supply voltage VDD, which extends through the first SRAM cell 50a and the first logic cell. M0 path 2 includes a local metal line to serve as a storage node SN in the first SRAM cell 50a and a signal line in the first logic cell. M0 path 3 includes a local metal line to serve as a complementary storage node SNB in the first SRAM cell 50a and a signal line in the first logic cell. M0 path 4 includes a local metal line to serve as a complementary bit line (or inverse bit line) BLB in the first SRAM cell 50a and a signal line in the first logic cell, where the signal line extends into the first SRAM cell 50a and merges with the metal line as a bit line BL in the first SRAM cell 50a. M0 path 5 includes a local metal line to serve as a word line WL in the first SRAM cell 50a and a signal line in the first logic cell. M0 path 6 includes a metal line connected to the power supply voltage VSS, which extends through the first SRAM cell 50a, the second SRAM cell 50b, the first logic cell, and the second logic cell. M0 path 7 includes a local metal line to serve as a word line WL in the second SRAM cell 50b and a signal line in the second logic cell. M0 path 8 includes a local metal line to serve as a complementary bit line (or inverse bit line) BLB in the second SRAM cell 50b and a signal line in the second logic cell, where the signal line extends into the second SRAM cell 50b and merges with the metal line as a bit line BL in the second SRAM cell 50b. M0 path 9 includes a local metal line to serve as a complementary storage node SNB in the second SRAM cell 50b and a signal line in the second logic cell. M0 path 10 includes a local metal line to serve as a storage node SN in the second SRAM cell 50b and a signal line in the second logic cell. M0 path 11 includes a metal line connected to the power supply voltage VDD, which extends through the second SRAM cell 50b and the second logic cell.

[0143] Between the boundary lines of the SRAM cells in the SRAM cell block 30 and the logic cells in the logic cell block 40, there is an active region transition region 48, or simply transition region 48. In the transition region 48, the active regions shared by the SRAM cells and the corresponding logic cells in the same column pass through the transition region 48.

[0144] The gate structures of the SRAM cells and the logic cells (not shown inFigure 7 The gate structures are arranged in a Y direction and evenly distributed along an X direction (as shown in FIG. 1), where two adjacent gate structures have a uniform distance. The uniform distance is denoted as a gate pitch or a poly pitch (PP). In an embodiment, the transition region 48 can have a width of two gate pitches in the X direction, although other widths are possible. For example, in other embodiments, the transition region 48 can have a width of three, four, five, six, seven, eight, or more gate pitches in the X direction.

[0145] When forming transistors, the gate structures intersect the active regions 102 and 104. In the SRAM cell block 30, the transistors formed in the intersection regions of the gate structures and the active regions 102 and 104 are used to form SRAM cells. In the logic cell block 40, the transistors formed in the intersection regions of the gate structures and the active regions 102 and 104 are used to form logic cells. Transistors are also formed in the intersection regions of the gate structures and the active regions 102 and 104 in the transition region 48. Because the metal paths (and metal lines) in the SRAM cells and the logic cells are aligned with each other, the transition region 48 does not need to have edge cells. Thus, the transistors formed in the transition region 48 (which would otherwise be non-functional transistors) can be functional transistors to improve the circuit area utilization. For example, the transistors formed in the transition region 48 can be implemented as the computational circuit 16 or a portion of the computational circuit 16 as shown in FIG. 2. Figure 1A

[0146] Figure 8 ​FIG. 4 is a schematic diagram of a portion of a CIM circuit 400 configured to multiply an input signal XIN with data from a first SRAM cell 50a and a second SRAM cell 50b, according to some embodiments. The CIM circuit 400 includes the first SRAM cell 50a, the second SRAM cell 50b, a word line driver 402, and a multiplier circuit 404. The word line driver 402 includes NAND gates 406 and 408 electrically coupled to the multiplier circuit 404. The NAND gates 406 and 408 are configured to receive the input signal XIN and one of a plurality of read select signals RSEL[0] and RSEL[1]. Further, the NAND gates 406 and 408 are configured to provide one of a plurality of read word line signals RWLB[0] and RWLB[1] to the multiplier circuit 404 to enable a selected column of the first SRAM cell 50a and the second SRAM cell 50b. The NAND gate 406 receives the input signal XIN and the read select signal RSEL[0] and provides the read word line signal RWLB[0] to the multiplier circuit 404. The NAND gate 408 receives the input signal XIN and the read select signal RSEL[1] and provides the read word line signal RWLB[1] to the multiplier circuit 404.

[0147] The first SRAM cell 50a and the second SRAM cell 50b are electrically coupled to the multiplier circuit 404 to provide stored data bits to the multiplier circuit 404 via a plurality of data signals DB[0] and DB[1]. In some embodiments, the first SRAM cell 50a and the second SRAM cell 50b are configured to store weight data, such as weights of a convolutional neural network (CNN).

[0148] The multiplier circuit 404 includes a plurality of logic gates to multiply the input signal XIN received from the word line driver 402 with the data bits from the first SRAM cell 50a and the second SRAM cell 50b. In this example, the multiplier circuit 404 includes a first OR gate 410, a second OR gate 412, and a NAND gate 414. In other embodiments, the multiplier circuit 404 includes different logic gates. The first OR gate 410 is configured to receive the read word line signal RWLB[0] from the word line driver 402 and the data signal DB[0] from the first SRAM cell 50a. The second OR gate 412 is configured to receive the read word line signal RWLB[1] from the word line driver 402 and the data signal DB[1] from the second SRAM cell 50b. The NAND gate 414 receives output signals from the first OR gate 410 and the second OR gate 412 and provides a result of the multiplication at an output signal OUT.

[0149] During operation, to select one of the first SRAM cell 50a and the second SRAM cell 50b, one of the inverters 406 and 408 in the word line driver 402 receives a read select signal RSEL[0] or RSEL[1] at a logic high level (e.g., logic 1), and the other of the inverters 406 and 408 receives a read select signal RSEL[0] or RSEL[1] at a logic low level (e.g., logic 0). The inverter 406 or 408 that receives the read select signal RSEL[0] or RSEL[1] at the logic low level is not selected and provides a logic high level signal to one of the first OR gate 410 or the second OR gate 412, which in turn passes the logic high level signal to one input of the inverter 414 for output. The inverter 406 or 408 that receives the read select signal RSEL[0] or RSEL[1] at the logic high level is selected to invert the input signal XIN and pass an inverted input signal XINB to the other of the first OR gate 410 or the second OR gate 412. The first OR gate 410 or the second OR gate 412 that receives the inverted input signal XINB also receives one of the data signals DB[0] or DB[1] from the connected first SRAM cell 50a or second SRAM cell 50b and provides an output signal to the other input of the inverter 414 for output. This multiplies the inverted input signal XINB and the data from the connected first SRAM cell 50a or second SRAM cell 50b. The inverter 414 outputs the result of the multiplication at the output signal OUT.

[0150] Figure 9 A schematic diagram of a computing circuit 500 according to some embodiments, in which the computing circuit 500 provides the multiplier circuit 404 Figure 8The computing circuit 500 includes eight transistors, four PMOS transistors P0, P1, P2, and P3, and four NMOS transistors N0, N1, N2, and N3. A first source / drain (S / D) of the PMOS transistor P0 is electrically coupled to a power supply (VDD), and a second S / D of the PMOS transistor P0 is electrically coupled to a first S / D of the PMOS transistor P1. Further, a first S / D of the PMOS transistor P2 is electrically coupled to the power supply (VDD), and a second S / D of the PMOS transistor P2 is electrically coupled to a first S / D of the PMOS transistor P3. A second S / D of the PMOS transistor P1 is electrically coupled to a second S / D of the PMOS transistor P3 and a first S / D of each of the NMOS transistors N0, N1. A second S / D of the NMOS transistor N0 is electrically coupled to a second S / D of the NMOS transistor N1 and a first S / D of each of the NMOS transistors N2, N3. Second S / D of each of the NMOS transistors N2, N3 is electrically coupled to a reference voltage (VSS), such as ground. Gates of the PMOS transistor P0 and the NMOS transistor N0 are electrically coupled together to receive a data signal DB[0], and gates of the PMOS transistor P3 and the NMOS transistor N3 are electrically coupled together to receive a data signal DB[1]. Further, gates of the PMOS transistor P1 and the NMOS transistor N1 are electrically coupled together to receive a read word line signal RWLB[0], and gates of the PMOS transistor P2 and the NMOS transistor N2 are electrically coupled together to receive a read word line signal RWLB[1].

[0151] During operation, if the read word line signal RWLB[1] is at a logic low level (e.g., logic 0), the PMOS transistor P2 is biased on and the NMOS transistor N2 is biased off. Further, if the read word line signal RWLB[0] is at a logic high level (e.g., logic 1), the PMOS transistor P1 is biased off and the NMOS transistor N1 is biased on. Thus, if the data signal DB[1] is at a logic low level, the PMOS transistor P3 is biased on and the NMOS transistor N3 is biased off, causing the output signal OUT to be at a logic high level, and if the data signal DB[1] is at a logic high level, the PMOS transistor P3 is biased off and the NMOS transistor N3 is biased on, causing the output signal OUT to be at a logic low level. Further, if the read word line signal RWLB[0] is at a logic low level, the PMOS transistor P1 is biased on and the NMOS transistor N1 is biased off, and if the read word line signal RWLB[1] is at a logic high level, the PMOS transistor P2 is biased off and the NMOS transistor N2 is biased on. Thus, if the data signal DB[0] is at a logic low level, the PMOS transistor P0 is biased on and the NMOS transistor N0 is biased off, causing the output signal OUT to be at a logic high level, and if the data signal DB[0] is at a logic high level, the PMOS transistor P0 is biased off and the NMOS transistor N0 is biased on, causing the output signal OUT to be at a logic low level. If the read word line signals RWLB[0] and RWLB[1] are at logic high levels, the PMOS transistors P1 and P2 are biased off and the NMOS transistors N2 and N1 are biased on, causing the output signal OUT to be at a logic low level.

[0152] Figure 10 A layout 600 of a circuit region 45 similar to layout 300( Figure 7 ) is described, where layout 600 and layout 300 differ in that layout 600 implements a computing circuit 500( Figure 9 ) in the transition region 48. Figure 10 Simplifications have been made for clarity of understanding of the innovative technology of the present disclosure. For example, only the active regions of the DL tiers are shown, and other features (e.g., gate structures, contacts, vias, and metal lines) are not shown Figure 10The transition region 48 does not need to have edge cells since the metal paths (and respective metal lines) in the SRAM cells and logic cells are aligned, as described above. Therefore, transistors (which would otherwise be non-functional transistors) formed in the transition region 48 can be used as functional transistors to improve circuit utilization. In the described embodiment, PMOS transistors P0 and P2 are formed on a continuous active region 104 that extends from the first SRAM cell 50a and are located in the transition region 48; NMOS transistors N0 and N1 are formed on a continuous active region 102 that extends from the first SRAM cell 50a and are located in the transition region 48; NMOS transistors N2 and N3 are formed on a continuous active region 102 that extends from the second SRAM cell 50b and are located in the transition region 48; and PMOS transistors P1 and P3 are formed on a continuous active region 104 that extends from the second SRAM cell 50b and are located in the transition region 48. The computation circuit 500, which provides the functionality of a multiplier circuit, is merely an example. Computation circuits can be implemented to provide other functions, such as accumulation, absolute difference addition, and other computation functions suitable for CIM applications. Implementing computation circuits in the transition region between SRAM cells and logic cells can simplify circuit complexity, thereby reducing circuit area. This can also minimize data movement distance, ultimately improving device speed and reducing power requirements.

[0153] As described above, the computation circuit can be further divided into computation elements integrated into each SRAM cell. Figure 1B Figure 11 An example of an SRAM cell 50' in which an exclusive-NOR (XNOR) logic can be implemented is described. The SRAM cell 50' is also referred to as an XNOR bitcell. The SRAM cell 50' includes an internal capacitor 56 integrated between the bitcell and a read bitline. The SRAM cell 50' includes a PMOS transistor P0, a PMOS transistor P1, an NMOS transistor N0, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, and a capacitor 56. Figure 2 ​The difference between the two is that the capacitor 56 of the SRAM cell 50' is coupled between the output node of the bit cell and a first read bit line RBL, a read transistor 58 is coupled to the bit cell and a first read word line RWL, and channel gate transistors PG-1 and PG-2 are implemented as transmission gates. Channel gate transistor PG-1 is controlled by multiple control signals WL1P and WL1N, while channel gate transistor PG-2 is controlled by multiple control signals WL2P and WL2N. In this configuration located in a CIM bit cell array, the first read word line RWL on the selected row is turned on to discharge any residual voltage on the internal capacitor 56, and the P-channel transmission gate on channel gate transistor PG-1 or PG-2 is turned on depending on whether the data is 1 or 0, so as to write the desired data state to the bit cell. Figure 11 A truth table is provided to describe the logic function of SRAM cell 50' as an XNOR bit cell.

[0154] Figure 12 A layout 700 is described for circuit region 45, wherein layout 700 is similar to layout 300. Figure 7 ) and layout 500 ( Figure 10 However, layout 700 has one difference: when viewed from above, capacitor 56 is implemented within the cell boundary of each SRAM cell 50'. Figure 12 For clarity, simplification has been implemented to better understand the innovative technology of this utility model. For example, only the active region of the DL layer is shown; other features (such as gate structure, contacts, vias, and metal lines) are not shown. Figure 12 The process is ignored. Capacitor 56 can be implemented as a metal-insulator-metal (MIM) capacitor located on a higher metal layer (e.g., M4 layer or higher) and floating above each SRAM cell 50. Figure 3 The device element 80 is shown. In the described embodiment, the outline of the capacitor 56 from a top-view perspective is represented by a dashed rectangular block with its long side along the Y direction and overlapping the active regions 102, 104. In several other embodiments, the outline of the capacitor 56 from a top-view perspective may have other shapes, such as square or circular, and may overlap only one of the active regions, or may be stacked between the active regions along the Y direction without overlapping with any of the active regions. Furthermore, similar to layout 500 ( Figure 10 The transition region 48 may include functional transistors formed on the active regions 102 and 104, and the functional transistors may be electrically coupled to the capacitor 56 and / or the transistors in the SRAM cell 50'.

[0155] Based on the discussion as described above, it can be seen that the present application provides advantages over conventional semiconductor structures. However, it should be noted that other embodiments can provide additional advantages, and not all embodiments need to exhibit the same advantages. For example, the present application provides a memory macro suitable for implementing a CIM system or other memory system. The memory macro provides integration of memory cells and logic cells, thereby allowing the memory cells and logic cells to be closely packed and have aligned active regions and metal paths (as well as metal lines). Computing circuitry can be implemented in a transition region between the memory cells and logic cells, thereby allowing data to be analyzed on the fly and enabling faster payback and decision making by the CIM application device, with reduced circuit complexity, reduced circuit area, improved circuit speed, and reduced power requirements.

[0156] In one example of an embodiment, the utility model discloses a semiconductor structure. The semiconductor structure includes a memory cell, a signal line connected to the memory cell, a first voltage line for receiving a supply voltage, and a second voltage line for receiving an electrical ground voltage. The semiconductor structure also includes a logic cell configured to provide a logic function to the memory cell, wherein the logic cell is connected to the signal line, the first voltage line, and the second voltage line. The semiconductor structure also includes a transition region extending from a first boundary of the memory cell to a second boundary of the logic cell. The semiconductor structure also includes an interconnect structure over the memory cell and the logic cell. The interconnect structure includes the signal line, the first voltage line, and the second voltage line on a same metal line layer of the interconnect structure. The signal line extends from within the second boundary of the logic cell into the first boundary of the memory cell. The transition region includes one or more functional transistors electrically coupled to the memory cell. In some embodiments, the memory cell is a static random access memory (SRAM) cell. In some embodiments, the one or more functional transistors in the transition region are electrically coupled to the logic cell. In some embodiments, the signal line is a bit line. In some embodiments, the signal line is a reverse bit line. In some embodiments, the first boundary of the memory cell has a first width, the second boundary of the logic cell has a second width, and the first width is equal to the second width. In some embodiments, the memory cell includes an active region that extends continuously along a first direction through the transition region and into the logic cell. In some embodiments, at least one of the one or more functional transistors in the transition region is formed over the active region. In some embodiments, the first voltage line and the second voltage line overlap a first edge and a second edge, respectively, of the first boundary of the memory cell, wherein the first edge and the second edge are opposite each other, and the first voltage line and the second voltage line overlap a third edge and a fourth edge, respectively, of the second boundary of the logic cell, wherein the third edge and the fourth edge are opposite each other. In some embodiments, the metal line layer of the interconnect structure is a lowest metal line layer of the interconnect structure.

[0157] In another example of embodiments, the utility model discloses a semiconductor structure. The semiconductor structure includes a memory cell having a first boundary, a logic cell having a second boundary, and an interconnect structure over the memory cell and the logic cell. The interconnect structure includes a signal line extending continuously from within the second boundary of the logic cell into the first boundary of the memory cell along a first direction, and a computing element. When the semiconductor structure is viewed from above, the computing element is within the first boundary of the memory cell. When the semiconductor structure is viewed from the side, the computing element is suspended over the signal line. In some embodiments, the computing element is a metal-insulator-metal (MIM) capacitor. In some embodiments, the computing element is electrically coupled to an output node of the memory cell. In some embodiments, the memory cell includes a first active region and a second active region extending continuously from within the first boundary of the memory cell into the second boundary of the logic cell along the first direction. In some embodiments, a profile of the computing element overlaps the first active region and the second active region when the semiconductor structure is viewed from above. In some embodiments, a profile of the computing element does not overlap the first active region and the second active region when the semiconductor structure is viewed from above. In some embodiments, the semiconductor structure further includes a transition region stacked between the memory cell and the logic cell along the first direction. The transition region includes a plurality of functional transistors electrically coupled to the memory cell.

[0158] In yet another example of embodiments, the utility model discloses a semiconductor structure. The semiconductor structure includes a static random access memory (6T-SRAM) cell having six transistors, the 6T-SRAM cell having a plurality of first metal paths parallel to each other, and a logic cell having a plurality of second metal paths parallel to each other. The number of the first metal paths is the same as the number of the second metal paths. Each of the first metal paths is aligned with one of the second metal paths. One of the second metal paths includes a signal line extending into the 6T-SRAM cell. In some embodiments, the signal line is a bit line. In some embodiments, the 6T-SRAM cell includes a first active region and a second active region, wherein the first active region and the second active region extend continuously into the logic cell.

[0159] The foregoing summary of the invention provides an overview of the features of many embodiments and can be used to better understand the technology disclosed in the present application. Those skilled in the art will appreciate that the technology described in the present application can be practiced with embodiments other than those described, which are presented for purposes of illustration and not limitation. The present application is therefore considered to include any alterations and further modifications in the technology and its applications to, and the uses of which, would be apparent upon inspection of this application to those skilled in the art. This application should not be limited to the embodiments set forth herein, but should be given the full scope of the appended claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a memory cell connected to a signal line, a first voltage line to receive a power supply voltage, and a second voltage line to receive an electrical ground voltage; a logic cell configured to provide logic functions to the memory cell, wherein the logic cell is connected to the signal line, the first voltage line, and the second voltage line; a transition region extending from a first boundary of the memory cell to a second boundary of the logic cell; and an interconnect structure over the memory cell and the logic cell, wherein the interconnect structure includes the signal line, the first voltage line, and the second voltage line in a same metal line layer of the interconnect structure; wherein the signal line extends from within the second boundary of the logic cell into the first boundary of the memory cell; and wherein the transition region includes one or more functional transistors electrically coupled to the memory cell.

2. The semiconductor structure of claim 1, wherein, The memory cell is a static random access memory cell, and the one or more functional transistors in the transition region are electrically coupled to the logic cell.

3. The semiconductor structure of claim 1, wherein, The signal line is a bit line or a bit line bar.

4. The semiconductor structure of claim 1, wherein, The first boundary of the memory cell has a first width, the second boundary of the logic cell has a second width, and the first width and the second width are equal.

5. The semiconductor structure of claim 1, wherein, The memory cell includes an active region that continuously extends along a first direction through the transition region and into the logic cell, and at least one of the one or more functional transistors in the transition region is formed over the active region.

6. The semiconductor structure of claim 1, wherein, The first voltage line and the second voltage line respectively overlap a first edge and a second edge of the first boundary of the memory cell, and the first edge and the second edge are opposite to each other; and wherein the first voltage line and the second voltage line respectively overlap a third edge and a fourth edge of the second boundary of the logic cell, and the third edge and the fourth edge are opposite to each other.

7. A semiconductor structure, characterized by Comprising: a memory cell having a first boundary; a logic cell having a second boundary; and an interconnect structure over the memory cell and the logic cell, wherein the interconnect structure includes: a signal line continuously extending along a first direction from within the second boundary of the logic cell into the first boundary of the memory cell; and a computing element within the first boundary of the memory cell when viewed from above the semiconductor structure, and suspended over the signal line when viewed from the side of the semiconductor structure. The computing element is a metal-insulation layer-metal capacitor, and the computing element is electrically coupled to an output node of the memory cell.

8. The semiconductor structure of claim 7, wherein, ​ 9. The semiconductor structure of claim 7, wherein, The memory cell includes a first active region and a second active region, the first active region and the second active region extend continuously from within the first boundary of the memory cell along the first direction into the second boundary of the logic cell, and an outline of the computing element overlaps or does not overlap the first active region and the second active region when the semiconductor structure is viewed from above.

10. A semiconductor structure, characterized by Comprises: a six-transistor static random access memory cell having a plurality of first metal paths parallel to each other; and a logic cell having a plurality of second metal paths parallel to each other, wherein: the number of the first metal paths and the second metal paths is the same; each of the first metal paths is aligned with one of the second metal paths; and one of the second metal paths includes a signal line that extends into the six-transistor static random access memory cell. ​

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