Semiconductor device

Abstract

The utility model provides a semiconductor device having an isolation structure, and the semiconductor device comprises a substrate; a first nanostructure channel region disposed on the substrate; a first gate structure surrounding the first nanostructure channel region; a second nanostructure channel region disposed on the substrate; a second gate structure surrounding the second nanostructure channel region; the isolation structure is arranged between the first nano-structure channel region and the second nano-structure channel region; the first protective oxide layer is arranged between the first nano-structure channel region and the isolation structure; and a second protective oxide layer disposed between the second nanostructure channel region and the isolation structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to semiconductor technology, in particular to a semiconductor device. BACKGROUND

[0002] With advances in semiconductor technology, there is an ever-increasing demand for higher storage capacity, faster processing systems, higher performance, and lower cost. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor transistors (MOSFETs), fin field-effect transistors (FinFETs), and gate-all-around (GAA). This miniaturization increases the complexity of semiconductor manufacturing processes. SUMMARY

[0003] The present utility model aims to provide a semiconductor device to solve at least one of the above problems.

[0004] The present utility model provides a semiconductor device, comprising: a substrate; a first nanostructure channel region disposed on the substrate; a first gate structure surrounding the first nanostructure channel region; a second nanostructure channel region disposed on the substrate; a second gate structure surrounding the second nanostructure channel region; an isolation structure disposed between the first nanostructure channel region and the second nanostructure channel region; a first protective oxide layer disposed between the first nanostructure channel region and the isolation structure; and a second protective oxide layer disposed between the second nanostructure channel region and the isolation structure.

[0005] According to one embodiment of the present utility model, the isolation structure includes a T-shaped cross-sectional profile.

[0006] According to one embodiment of the present utility model, the T-shaped cross-sectional profile includes a first portion extending vertically between the first nanostructure channel region and the second nanostructure channel region.

[0007] According to one embodiment of the present utility model, the T-shaped cross-sectional profile includes a second portion extending horizontally above the first nanostructure channel region and the second nanostructure channel region.

[0008] According to one embodiment of the present utility model, the first protective oxide layer is in contact with a high-k gate dielectric layer of the first gate structure.

[0009] According to one embodiment of the present utility model, the first nanostructure channel region and the second nanostructure channel region have a thickness of 3 nm to 15 nm.

[0010] According to one of the embodiments of the present application, the first protective oxide layer and the second protective oxide layer have a thickness of 2 nm to 3 nm.

[0011] According to one of the embodiments of the present application, the semiconductor device further comprises a first fin base and a second fin base, wherein the first fin base is located below the first nanostructure channel region and the second fin base is located below the second nanostructure channel region.

[0012] According to one of the embodiments of the present application, the bottom surface of the isolation structure is substantially coplanar with the top surfaces of the first fin base and the second fin base.

[0013] According to one of the embodiments of the present application, the first protective oxide layer is disposed on the sidewall of the first nanostructure channel region and the second protective oxide layer is disposed on the sidewall of the second nanostructure channel region. BRIEF DESCRIPTION OF DRAWINGS

[0014] The embodiments of the present application can be best understood with reference to the following detailed description and accompanying drawings. It should be noted that the various drawings are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily expanded or reduced for the sake of clarity. In doing so, the principles of the embodiments of the present application can be more readily understood.

[0015] FIG. 1A An isometric view of a semiconductor device having an isolation structure according to some embodiments is illustrated.

[0016] FIG. 1B And FIG. 1C A cross-sectional view of a semiconductor device having an isolation structure according to some embodiments is illustrated.

[0017] FIG. 1D A top view of a semiconductor device having an isolation structure according to some embodiments is illustrated.

[0018] FIG. 2 A flowchart of a method for fabricating a semiconductor device having an isolation structure according to some embodiments is illustrated.

[0019] FIGS. 3-7 And FIGS. 10-15 Cross-sectional views of a semiconductor device having an isolation structure according to some embodiments at various stages of its fabrication process are illustrated.

[0020] FIG. 8 And FIG. 9 Process mechanisms of a fabrication process of a semiconductor device having an isolation structure according to some embodiments are illustrated.

[0021] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally refer to the same, similar, and / or functionally similar elements throughout the various figures.

[0022] Reference signs are as follows:

[0023] 100: semiconductor device

[0024] 102A: FET

[0025] 102B: FET

[0026] 104: substrate

[0027] 106A: fin base

[0028] 106B: fin base

[0029] 110A: source / drain (S / D) region

[0030] 110B: source / drain (S / D) region

[0031] 112: interlayer dielectric (ILD) layer

[0032] 114: gate spacer

[0033] 116: shallow trench isolation (STI) region 118: etch stop layer (ESL)

[0034] 120: gate structure

[0035] 122: nanostructured channel region

[0036] 124: inner spacer

[0037] 126: interfacial oxide (IL) layer

[0038] 127: high-k (HK) gate dielectric layer

[0039] 128: work function metal (WFM) layer

[0040] 130: gate metal fill layer

[0041] 132: poly cut structure

[0042] 132A: first portion

[0043] 132B: second portion

[0044] 134: protective oxide layer

[0045] 200: method

[0046] 205: operation

[0047] 210: operation

[0048] 215: operation

[0049] 220: operation

[0050] 302: nanostructured layer

[0051] 304: protective oxide layer

[0052] 306A: superlattice structure

[0053] 306B: superlattice structure

[0054] 402: polysilicon structure

[0055] 502: hard mask layer

[0056] 504: opening

[0057] 602: metal oxide layer

[0058] 604A: polysilicon cut opening

[0059] 604B: polysilicon cut opening

[0060] 702: dielectric layer

[0061] X: X direction (axis)

[0062] Y: Y direction (axis)

[0063] Z: Z direction (axis)

[0064] A-A: section line

[0065] B-B: section line

[0066] S: spacing

[0067] W: width

[0068] D: thickness DETAILED DESCRIPTION

[0069] The following disclosure provides numerous embodiments or examples for implementing various elements of the subject matter provided. Specific examples of elements and their configurations are described below to exemplify the embodiments of the present disclosure. Of course, the above-described examples are merely illustrative and not intended to limit the present disclosure. For example, if a first element is recited as being formed over a second element, this can include embodiments in which the first and second elements are in direct contact, as well as embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. As used herein, formation of a first component on a second component means that the first component is formed in direct contact with the second component. Furthermore, the present disclosure can also repeat element symbols and / or letters in various examples. Such repetition is for the sake of simplicity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0070] Further, where spatially relative terms are used, such as "beneath", "below", "lower", "above", "upper", and the like, they are used for ease of describing the aspects of one (or more) components to another (or more) components or structural features. The spatially relative terms are used to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. The spatially relative terms are used to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. Where the device is turned over 90 degrees or other orientations, the spatially relative descriptors used will need to be interpreted accordingly.

[0071] It should be noted that references to "one embodiment", "one example", "an example embodiment", "an example", etc., mean that a particular element, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or other like phrases in various places in the description are not necessarily all referring to the same embodiment.

[0072] It should be understood that the words or terminology used herein is for the purpose of description and not of limitation, such that the description of the specification and the terminology used thereby are to be interpreted in accordance with the teachings provided herein to those skilled in the relevant art.

[0073] In some embodiments, the terms "about" and "substantially" can mean that a given value varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% variation from the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" can refer to a percentage of a value as interpreted by one of ordinary skill in the relevant art in light of the teachings herein.

[0074] Gate-all-around (GAA) transistor structures can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the structures, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes can incorporate photolithography and self-alignment processes, allowing for the creation of patterns with smaller pitches than are obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structures.

[0075] The present utility model provides a kind of semiconductor device and example method for solving the challenge of forming poly-cut structures (also known as "isolation structures") in semiconductor device. The semiconductor device can include superlattice structures with nanostructure layers on fin bases. The nanostructure layers can include channel regions. As the pitch between adjacent superlattice structures shrinks with advances in semiconductor technology, defining and forming poly-cut structures between adjacent superlattice structures becomes challenging. Defining and forming poly-cut structures with a pitch less than about 25 nm between adjacent superlattice structures is challenging because extreme ultra-violet (EUV) lithography and etching processes used in the manufacture of semiconductor devices cannot accommodate process variations. Furthermore, when the pitch is less than about 25 nm, the poly-cut openings (also known as "isolation openings") fall on top of the nanostructure layers of the superlattice structures, which causes damage to the nanostructure layers during the formation of the poly-cut structures. The process of forming poly-cut structures can be referred to as a "poly-cut process".

[0076] To address these challenges, the present disclosure provides a method of protecting a nanostmcture layer of a superlattice structure using a protective oxide layer. A protective oxide layer can be formed on the superlattice structure prior to forming a poly cut structure. Because the protective oxide layer is thin, the poly cut process can degrade the protective oxide layer, which can cause damage to the topmost nanostmcture layer of the superlattice structure. This damage can be attributed to the high ion energy of the ions of the poly cut etchant of the poly cut process, which can penetrate the thin protective oxide layer. Because the poly cut etching process is an isotropic etching process, the flat surfaces are more susceptible to ion damage than the sidewall surfaces, primarily because the ions have a higher energy when striking the flat surfaces. This damage can cause the top corners of the topmost nanostmcture layer of the superlattice structure to round. The size difference of the topmost nanostmcture layer compared to the other nanostmcture layers in the superlattice structure can cause the topmost nanostmcture layer to have different current transport characteristics than the other nanostmcture layers in the superlattice structure.

[0077] The present disclosure also provides example methods for protecting the protective oxide layer from damage to the nanostmcture layers (e.g., the topmost nanostmcture layer) of the superlattice structure. In some embodiments, the example methods include selectively depositing a protective metal oxide layer on the surfaces of the protective oxide layer exposed during the poly cut etching process. The protective metal oxide layer can be selectively formed on the surfaces of the protective oxide layer on the sacrificial polysilicon structure. The formation of the protective metal oxide layer can also selectively choose surfaces that are parallel to the horizontal surfaces (e.g., the top and bottom surfaces of the protective oxide layer) instead of the vertical surfaces (e.g., the sidewall surfaces of the protective oxide layer). This protective metal oxide layer can be formed during the poly cut etching process and can be selectively deposited on the horizontal surfaces of the protective oxide layer exposed during the poly cut process.

[0078] FIG. 1A An isometric view of a semiconductor device 100 having field-effect transistors (FETs) FET 102A and FET 102B is illustrated in accordance with some embodiments. Although the semiconductor device 100 is illustrated as having two FETs 102A and 102B, the semiconductor device 100 can have any number of FETs. In some embodiments, the FETs 102A and 102B can represent n-type FETs 102A and 102B (NFETs 102A and 102B) or p-type FETs 102A and 102B (PFETs 102A and 102B). The discussion of the FETs 102A and 102B applies to the NFETs 102A and 102B and the PFETs 102A and 102B unless otherwise noted. FIG. 1B and FIG. 1C are shown along the FIG. 1Aa cross-sectional view of the semiconductor device 100 along line A-A and line B-B. FIG. 1D a top view of the semiconductor device 100 is illustrated. FIG. 1A a cross-sectional view of the semiconductor device 100 is illustrated. FIG. 1B and FIG. 1C a cross-sectional view of the semiconductor device 100 is illustrated, which has additional structures, which are not illustrated in FIG. 1A for simplicity. Unless otherwise noted, the discussion of elements having the same reference numbers in FIGS. 1A-1D apply to each other.

[0079] Referring to FIGS. 1A-1D , the semiconductor device 100 can include (i) a substrate 104, (ii) fin bases 106A and 106B (also referred to as “sheet bases” 106A and 106B or “fin structures” 106A and 106B) disposed on the substrate 104, (iii) a nanostructure channel region 122, (iv) gate structures 120 disposed on the fin bases 106A and 106B, (v) gate spacers 114 disposed along sidewalls of the gate structures 120, (vi) a poly cut structure 132 (also referred to as “isolation structure 132”) disposed between the gate structures 120 on the fin bases 106A and 106B, (vi) source / drain (S / D) regions 110A and 110B disposed on portions of the fin fin bases 106A and 106B not covered by the gate structures 120, (vii) a shallow trench isolation (STI) region 116, (viii) an etch stop layer (ESL) 118 disposed directly on the S / D regions 110A and 110B, (ix) an interlayer dielectric (ILD) layer 112 disposed directly on the ESL 118, (x) a protective oxide layer 134 along sidewalls of the nanostructure channel region 122, and (xi) an inner spacer 124. The term “nanostructure” refers to a structure, layer, and / or region having a horizontal dimension (e.g., along an X-axis and / or a Y-axis) and / or a vertical dimension (e.g., along a Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values less than about 100 nm are within the scope of the present disclosure. Depending on the context, the S / D regions 110A and 110B can individually or collectively refer to a source or a drain.

[0080] The semiconductor device 100 can be formed on a substrate 104. Other FETs and / or structures (e.g., isolation structures) can be formed on the substrate 104. The substrate 104 can be a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, other suitable semiconductor materials, and combinations thereof. In addition, the substrate 104 can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, the fin bases 106A and 106B can include a material similar to the substrate 104 and can have elongated sides extending along the X-axis. In some embodiments, the STI regions 116, the ESL 118, and the ILD layers 112 can include insulating materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbinitride (SiOCN), silicon germanium oxide (SiGeOx), and other suitable insulating materials.

[0081] Referring to FIGS. 1B-1D FET 102A can include (i) a stack of nanowire channel regions 122 disposed on the fin base 106A and surrounded by the gate structure 120, (ii) a protective oxide layer 134 disposed on sidewalls of the nanowire channel regions 122 disposed on the fin base 106A, and (iii) an epitaxial S / D region 110A disposed adjacent to the stack of nanowire channel regions 122 disposed on the fin base 106A. Similarly, FET 102B can include (i) a stack of nanowire channel regions 122 disposed on the fin base 106B and surrounded by the gate structure 120, (ii) a protective oxide layer 134 disposed on sidewalls of the nanowire channel regions 122 disposed on the fin base 106B, and (iii) an epitaxial S / D region 110B disposed adjacent to the stack of nanowire channel regions 122 disposed on the fin base 106B. For simplicity, FIG. 1D The ILD layers 112 and the ESL 118 are not shown.

[0082] Referring to FIG. 1B and FIG. 1CThe nanostructure channel regions 122 can include a semiconductor material similar to or different from the substrate 104 and can include a semiconductor material similar to or different from each other. In some embodiments, the nanostructure channel regions 122 can include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), SiGe, silicon germanium boron (SiGeB), boron silicon germanium (GeB), silicon germanium tin boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor material. Although three nanostructure channel regions are illustrated in each stack, the FETs 102A and 102B can include any number of nanostructure channel regions in each stack. Although a rectangular cross-section of the nanostructure channel regions 122 is illustrated, the nanostructure channel regions 122 can have a cross-section of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). In some embodiments, the nanostructure channel regions 122 can be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanoscale structure shapes.

[0083] For the NFETs 102A and 102B, the S / D regions 110A and 110B can include an epitaxially grown semiconductor material (e.g., Si) and n-type dopants (e.g., phosphorus and other suitable n-type dopants). For the PFETs 102A and 102B, the S / D regions 110A and 110B can include an epitaxially grown semiconductor material (e.g., Si and SiGe) and p-type dopants (e.g., boron and other suitable p-type dopants).

[0084] The gate structure 120 can be a multi-layer structure and can surround the nanostructure channel regions 122, for which the gate structure 120 can be referred to as a “gate-all-around (GAA)” or a “Horizontal Gate All Around (HGAA).” The FET 102A can be referred to as a “GAA FET 102A.” The gate portions of the gate structure 120 surrounding the nanostructure channel regions 122 can be electrically isolated from the adjacent S / D regions 110A by the inner spacers 124, as shown in FIG. 1C The gate portions of the gate structure 120 disposed on the stacks of the nanostructure channel regions 122 can be electrically isolated from the adjacent S / D regions 110A by the gate spacers 114, as shown in FIG. 1C The inner spacers 124 and the gate spacers 114 can include an insulating material, such as SiO2, SiN, SiCN, SiOCN, and other suitable insulating materials.

[0085] The gate structure 120 can include an interfacial oxide (IL) layer 126, a high-k (HK) gate dielectric layer 127 disposed on the IL layer 126, a work function metal (WFM) layer 128 disposed on the HK gate dielectric layer 127, and a gate metal fill layer 130 disposed on the WFM layer 128. As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, HK refers to a dielectric constant greater than that of SiO2(e.g., greater than 3.9).

[0086] The IL layer 126 can include silicon oxide SiO2, silicon germanium oxide (SiGeOx), or germanium oxide (GeOx). The HK gate dielectric layer 127 can include a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the WFM layer 128 can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-based materials, or combinations thereof for the NFETs 102A and 102B. In some embodiments, the WFM layer 128 can include Ti-based or Ta-based nitrides or alloys that are substantially free of Al (e.g., no Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloys, titanium-copper (Ti-Cu) alloys, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloys, tantalum-copper (Ta-Cu), and combinations thereof for the PFETs 102A and 102B. In some embodiments, the gate metal fill layer 130 can include a suitable conductive material such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0087] Referring to FIG. 1A , FIG. 1B and FIG. 1DIn some embodiments, the poly-cut structure 132 can be disposed between the FETs 102A and 102B. In some embodiments, the poly-cut structure 132 can electrically isolate the gate structures 120 disposed on the fin bases 106A and 106B from each other. In some embodiments, the poly-cut structure 132 can include a dielectric material, such as SiN, Si02, SiOCN, SiOC, SiON, and other suitable dielectric materials. In some embodiments, the dielectric material of the poly-cut structure 132 can be different from the dielectric material of the ILD layer 112.

[0088] In some embodiments, the poly-cut structure 132 can be disposed directly on the STI region 116 between the fin bases 106A and 106B. In some embodiments, the poly-cut structure 132 can be in direct contact with the HK gate dielectric layer 127 of the gate structures 120. In some embodiments, a bottom surface of the poly-cut structure 132 can be substantially coplanar with a top surface of the fin bases 106A and 106B underneath the nanostructure channel regions 122. In some embodiments, the poly-cut structure 132 can have a T-shaped cross-sectional profile. In some embodiments, the poly-cut structure 132 can include a first portion 132A extending vertically between the nanostructure channel regions on the fin bases 106A and 106B and a second portion 132B extending horizontally above the nanostructure channel regions on the fin bases 106A and 106B. In some embodiments, the second portion 132B extends perpendicularly to the first portion 132A and parallel to the fin bases 106A and 106B.

[0089] Reference is made to FIG. 1B In some embodiments, a protective oxide layer 134 can be disposed between the nanostructure channel regions 122 and the poly-cut structure 132. In some embodiments, the protective oxide layer 134 can be disposed directly on sidewalls of the nanostructure channel regions 122 and the poly-cut structure 132 facing each other. In some embodiments, a thickness of the protective oxide layer 134 along the Z-axis can be greater than a thickness of the nanostructure channel regions 122 along the Z-axis. In some embodiments, a top surface and a bottom surface of the protective oxide layer 134 can be in direct contact with the HK gate dielectric layer 127. In some embodiments, sidewalls of the protective oxide layer 134 can be in direct contact with the IL layer 126. The oxide layer 134 can include an oxide dielectric material, such as Si02, SiON, SiOCN, SiOC, and other suitable oxide dielectric materials. In some embodiments, the protective oxide layer 134 can be deposited using atomic layer deposition.

[0090] FIG. 2 is a flowchart of an example method 200 for fabricating a semiconductor device 100 as described above with reference to FIGS. 1A-1D For illustrative purposes, reference will be made to the fabrication of a semiconductor device 100 as described above with reference toFIGS. 3-14 The example manufacturing process of the semiconductor device 100 shown is described below. FIG. 2 The operation shown. FIG. 3 and FIG. 2 The semiconductor device 100 is illustrated along various stages of manufacturing according to some embodiments. FIG. 3 A cross-sectional view of line AA. FIG. 4 and FIG. 4 The process mechanism of a manufacturing flow for a semiconductor device 100 according to some embodiments is illustrated. The operation of method 200 may be performed in a different order or not at all, depending on the specific application. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only a few other processes may be briefly described herein. Unless otherwise stated, FIG. 2 and FIGS. 5-11 The discussion of elements with the same designation applies to each other.

[0091] refer to FIGS. 5-9 In operation 205, a superlattice structure is formed on the first fin substrate and the second fin substrate. For example, as shown in reference... FIG. 10 As described, superlattice structures 306A and 306B (also referred to as “nanosheet stacks 306A and 306B”) are formed on fin substrates 106A and 106B, respectively. Superlattice structure 306A may include nanostructure layers 122 and 302 arranged in an alternating configuration. Similarly, superlattice structure 306B may include nanostructure layers 122 and 302 arranged in an alternating configuration. Nanostructure layer 302 is also referred to as “sacrificial layer 302”. In some embodiments, nanostructure layer 122 may include Si and nanostructure layer 302 may include SiGe. In some embodiments, each of nanostructure layers 122 and 302 may have a thickness of about 3 nm to about 15 nm along the Z-axis.

[0092] refer to FIG. 11 In operation 210, a protective oxide layer is formed on the superlattice structure, and a polycrystalline silicon structure is formed on the protective oxide layer. For example, as referenced... FIG. 11 and FIG. 12As described, a protective oxide layer 304 can be formed on the superlattice structures 306A and 306B, and a polysilicon structure 402 can be formed on the superlattice structures 306A and 306B. In some embodiments, the step of forming the protective oxide layer 304 can include depositing a dielectric layer of SiO2, SiON, SiOCN, SiOC, or other suitable oxide dielectric material substantially conformally on the superlattice structures 306A and 306B and the STI regions 116. The protective oxide layer 304 can be deposited to protect the nanostructure layer 122 during a subsequent poly-cut process. In some embodiments, the protective oxide layer 304 can be about 2 nm to about 3 nm thick. The protective oxide layer 304 and the polysilicon layer 402 can encase the superlattice structures 306A and 306B. In some embodiments, the step of forming the polysilicon structure 402 can include depositing a polysilicon layer on the protective oxide layer 304, as shown in FIG. 4B. In some embodiments, during a subsequent process, the polysilicon structure 402 and the sacrificial layer 302 can be replaced with the gate structure 120 in a gate replacement process. FIG. 6

[0093] Referring to FIG. 6 , in operation 215, a poly-cut structure is formed in the polysilicon structure and between the first and second fin bases. For example, as described with reference to FIG. 7 , the poly-cut structure 132 can be formed in the polysilicon structure 402 and between the fin bases 106A and 106B. In some embodiments, the step of forming the poly-cut structure 132 can include (i) forming poly-cut openings 604A and 604B (also referred to as “isolation openings 604A and 604B” or “isolation trenches 604A and 604B”), as described with reference to FIG. 6 , (ii) depositing a dielectric layer 702 in the poly-cut openings 604A and 604B, as shown in FIG. 6C, (iii) performing a chemical mechanical polishing (CMP) process to planarize a top surface of the dielectric layer 702 with a top surface of the polysilicon structure 402, as shown in FIG. 6D, (iv) performing a trimming process on the dielectric layer 702 to form the poly-cut structure 132, as shown in FIG. 6E, and (v) removing the dielectric layer 702 and the polysilicon structure 402 to form the gate structure 120, as shown in FIG. 6F. FIG. 7 FIG. 8 FIG. 9 FIG. 6

[0094] ​​​​​In some embodiments, the step of forming the poly-cut opening 604A can include depositing and patterning a hard mask 502 on the polysilicon structure 402 to define an opening 504 for a subsequent poly-cut process. Since the spacing S between the fin bases 106A and 106B along the Y-axis is less than 25 nm, the width of the opening 504 along the Y-axis is formed to be greater than the spacing S, such that, in the subsequent poly-cut process, the poly-cut opening 604A over the superlattice structures 306A and 306B is formed to have a width W that is greater than the spacing S.

[0095] In some embodiments, the step of forming the poly-cut opening 604A can further include performing a poly-cut process through the opening 504. The poly-cut process can include an etching process to remove portions of the polysilicon structure 402 exposed through the opening 504. Since the opening 504 is greater than the spacing S, portions of the top surface of the protective oxide layer 304 can be exposed during the poly-cut process, as shown in FIG. 6B. If the exposed portions of the protective oxide layer 304 are not protected during the poly-cut process, the topmost nanostmcture layer 122 can be damaged during the poly-cut process. To prevent such damage, in addition to etching portions of the polysilicon structure 402 through the opening 504, the poly-cut process can further include forming a protective metal oxide layer 602. FIG. 7

[0096] Since the poly-cut process is an isotropic etching process, horizontal surfaces are more susceptible to ion damage than sidewall surfaces, primarily because the energy of the ions impacting the horizontal surfaces is higher. For example, during the poly-cut process, the horizontal surfaces of the protective oxide layer 304 under the opening 504 can be more susceptible to ion damage than the sidewall surfaces of the protective oxide layer 304 under the opening 504. Accordingly, during the poly-cut process, the horizontal surfaces of the protective oxide layer 304 under the opening 504 can be protected by the protective metal oxide layer 602. In some embodiments, the protective metal oxide layer 602 can be formed on the horizontal surfaces of the protective oxide layer 304 over the superlattice structures 306A and 306B, the protective oxide layer 304 being formed on exposed surfaces of the polysilicon structure 402 that are exposed during the poly-cut process to form the poly-cut opening 604A, as shown in FIG. 6B. In some embodiments, the protective metal oxide layer 602 can be formed on the horizontal surfaces of the protective oxide layer 304 over the STI region 116 that is exposed during the poly-cut process to form the poly-cut opening 604B, as shown in FIG. 6C. FIG. 11 FIG. 11

[0097] ​​​In some embodiments, a polycrystalline silicon structure 402 can be etched through opening 504 using a polycrystalline dicing etching process, wherein the polycrystalline dicing etching process is (i) selective on the polycrystalline silicon structure 402 above the protective oxide layer 304 and (ii) capable of protecting the protective oxide layer 304 and the topmost nanostructured layer 122 below the protective oxide layer 304. To achieve the combination of requirements (i) and (ii), the polycrystalline dicing etching process can be a dry etching process using polycrystalline silicon etchants having the following properties: (i) fluorine, chlorine, or bromine to etch the polycrystalline silicon structure 402, and (ii) dimethylaluminum chloride (DMAC) and hydrogen fluoride (HF) to form a protective metal oxide layer 602. An ion-enhanced deposition process is used to deposit the protective metal oxide layer 602, wherein energy is provided to the reactant ions (HF ions and DMAC ions) to facilitate the directional deposition process. Reference FIG. 12 and FIG. 11 During the deposition of the protective metal oxide layer 602, vertically oriented DMAC and HF ions are provided to facilitate the deposition of the protective metal oxide layer 602 on horizontal surfaces, such as (a) the top surface of the hard mask layer 502, (b) the top surface of the exposed oxide layer 304, and (c) the surface of the protective oxide layer 304 at the bottom of the polycrystalline dicing opening 604B. The vertical orientation of the DMAC and HF ions is detrimental to the formation of the protective metal oxide layer 602 on the sidewalls of the polysilicon layer 402 and the sidewalls of the polycrystalline dicing openings 604A and 604B. FIG. 12 and FIG. 12 As shown, HF reacts with DMAC to generate trimethylaluminum fluoride (Al(CH3)F2). Due to the presence of -OH dangling bonds, trimethylaluminum fluoride (Al(CH3)F2) can selectively adhere to the surface of the protective oxide layer 304. The methyl group can be removed as a non-volatile byproduct, leaving aluminum fluoride (AlF3) on the surface of the protective oxide layer 304. AlF3 can selectively react with oxygen from the protective oxide layer 304 to form an aluminum oxide (Al2O3)-based protective metal oxide layer 602. In some embodiments, the Al2O3-based protective metal oxide layer 602 may include trace amounts of AlF3. The surface of the polycrystalline silicon structure 402 has -H dangling bonds, which do not contribute to the incubation of Al(CH3)F2 on the polycrystalline silicon surface. Therefore, the protective metal oxide layer 602 does not form on the surface of the polycrystalline silicon structure 402. FIG. 13 and FIG. 2The protective metal oxide layer 602 is formed on the exposed sidewalls of the polycrystalline silicon structure 402. Furthermore, non-volatile byproducts containing methyl groups can adhere to the sidewalls of the protective oxide layer 304, thereby delaying the formation of the protective metal oxide layer 602 on the sidewalls. In some embodiments, the protective metal oxide layer 602 may have a thickness of about 1 nm to about 3 nm. In some embodiments, instead of DMAC and HF, dimethyltitanium chloride and HF can be used to form a titanium oxide (TiO2)-based protective metal oxide layer 602 with trace amounts of titanium fluoride (TiF).

[0098] Polycrystalline silicon dicing can be performed in inductively coupled plasma (ICP), capacitively coupled plasma (CCP), or electron cyclotron resonance (ECR) etching equipment. To form an AlO-based protective metal oxide layer 602, aluminum-containing gases such as DMAC or aluminum chloride (AlCl3) and HF can be introduced into the etching equipment along with the polycrystalline silicon etchant gas. Co-reacting gases, such as H2 and CO, can also be used. x or CH x It can flow into the etching equipment simultaneously. The polysilicon dicing process can be performed at temperatures from approximately 50°C to approximately 350°C and process pressures from approximately 1 mtorr to approximately 1 torr. The polysilicon dicing process can use source power from approximately 50 W to approximately 1200 W and source power frequencies equal to or greater than approximately 13.56 MHz. To ensure isotropic etching, the polysilicon dicing process can use bias power from approximately 1 V to approximately 1200 V and bias power frequencies lower than approximately 13.56 MHz.

[0099] In some embodiments, the protective metal oxide layer 602 can be removed after the openings 604A and 604B are formed. The protective oxide layer 602, which contains the aluminum polymer, can be removed using a standard cleaning solution (SC-1). The SC-1 solution may contain a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water. The SC-1 solution can selectively remove the protective metal oxide layer 602 above the protective oxide 304.

[0100] In some embodiments, such as FIGS. 14-15 As shown, after removing the protective oxide layer 602, a dielectric layer 702 can be deposited, followed by a CMP process to form... FIG. 14The dielectric layer 702 is shown. In some embodiments, the step of depositing the dielectric layer 702 in the polysilicon dicing openings 604A and 604B may include depositing the dielectric layer 702 using a chemical vapor deposition process. In some embodiments, after the CMP process, the remaining portion of the polysilicon structure 402 surrounding the protective oxide layer 304 and the polysilicon dicing structure 132 may be removed, such as FIG. 14 As shown.

[0101] In some embodiments, after removing the polysilicon structure 402, trimming can be performed. FIG. 15 The top and side portions of dielectric layer 702 are used to form FIG. 15 The polycrystalline cut structure 132 is shown. (Example) FIG. 15 As shown, the top and sides of dielectric layer 702 can be trimmed to a thickness D to form a polycrystalline diced structure 132. The trimming process can involve an isotropic etching process, where an etchant selectively removes dielectric layer 702 above protective oxide layer 304. The trimming operation can expose a larger area of ​​protective oxide layer 304, which can lead to easier removal of protective oxide layer 304 in subsequent steps. This can further facilitate the uniform deposition of HK dielectric layer 127, WFM layer 128, and gate metal fill layer 130 in the groove between polycrystalline diced structure 132 and the topmost nanostructure layer 122. After the trimming process, portions of protective oxide layer 304 from the top surfaces of superlattice structures 306A and 306B, as well as portions from the non-polycrystalline diced structure sidewalls of superlattice structures 306A and 306B, can be removed to expose superlattice structures 306A and 306B, as... FIG. 15 As shown.

[0102] refer to ​ In operation 220, the sacrificial layer of the superlattice structure is replaced by a gate structure. For example, as referenced... ​ As described, the sacrificial layer 302 is replaced by the gate structure 120. The formation of the gate structure 120 may include the following sequential operations: (i) etching the sacrificial layer 302 of the superlattice structures 306A and 306B, as... ​ As shown, (ii) the portion of the etched protective oxide layer 304 on the sidewall of the polycrystalline diced structure 132 exposed after etching the sacrificial layer 302, as... ​ As shown, (iii) an IL layer 126 is formed on the exposed surface of the nanostructured layer 122, such as ​ As shown, (iv) an HK dielectric layer 127 is deposited on the IL layer 126, as... ​ As shown, (v) a WFM layer 128 is deposited on the HK dielectric layer 127, as... ​ As shown, (vi) a gate metal fill layer 130 is deposited on the WFM layer 128, as follows: ​As shown, (vii) performing a CMP process to planarize top surfaces of the HK gate dielectric layer 127, the WFM layer 128, the gate metal fill layer 130, and the poly cut structure 132 to each other.

[0103] The present utility model provides a kind of semiconductor device (for example, semiconductor device 100) and example method (for example, method 200) for solving the challenge of forming poly cut structure (for example, poly cut structure 132) in semiconductor device).Semiconductor device can include superlattice structure (for example, superlattice structure 306A and 306B), it has nanostructure layer (for example, nanostructure layer 122 and 302) on fin base (for example, fin base 106A and 106B).Nanostructure layer can include channel region.As the spacing between adjacent superlattice structures decreases with the advancement of semiconductor technology, it becomes challenging to define and form poly cut structure between adjacent superlattice structures.It is challenging to define and form poly cut structure with a spacing of less than about 25 nm between adjacent superlattice structures, as extreme ultraviolet (EUV) lithography and etching processes used in the manufacture of semiconductor devices cannot accommodate process variations.In addition, when the spacing is less than about 25 nm, the poly cut opening (also referred to as "isolation opening") falls on top of the nanostructure layer of the superlattice structure, which can cause damage to the nanostructure layer during the formation of the poly cut structure.The process of forming the poly cut structure can be referred to as "poly cut process".

[0104] To address these challenges, the present utility model provides a method of using a protective oxide layer (for example, protective oxide layer 134) to protect the nanostructure layer of the superlattice structure.The protective oxide layer can be formed on the superlattice structure before the formation of the poly cut structure.As the protective oxide layer is thin, the poly cut process can degrade the protective oxide layer, which can cause damage to the topmost nanostructure layer of the superlattice structure.This damage can be attributed to the high ion energy of the ions of the poly cut etchant of the poly cut process, which can penetrate the thin protective oxide layer.As the poly cut etching process is an isotropic etching process, the flat surface is more susceptible to ion damage than the sidewall surface, mainly because the energy of the ions hitting the flat surface is higher.This damage can cause the top corner of the topmost nanostructure layer of the superlattice structure to round off.The size difference of the topmost nanostructure layer compared to other nanostructure layers in the superlattice structure can cause the topmost nanostructure layer to have different current transport characteristics than the current transport characteristics of other nanostructure layers in the superlattice structure.

[0105] The utility model also provides an example method for protecting the protective oxide layer from damaging the nanostructure layer (for example, the topmost nanostructure layer) of the superlattice structure. In some embodiments, the example method includes selectively depositing a protective metal oxide layer on a surface of the protective oxide layer exposed during a poly cut etch process. The protective metal oxide layer can be selectively formed on the surface of the protective oxide layer on the sacrificial polysilicon structure. The formation of the protective metal oxide layer can also selectively choose a surface parallel to a horizontal surface (for example, the top and bottom surfaces of the protective oxide layer) instead of a vertical surface (for example, the sidewall surface of the protective oxide layer). This protective metal oxide layer can be formed during the poly cut etch process and can be selectively deposited on the horizontal surface of the protective oxide layer exposed during the poly cut process.

[0106] In some embodiments, a method includes forming a first superlattice structure and a second superlattice structure on a substrate, forming a dielectric oxide layer on the first superlattice structure and the second superlattice structure, forming a polysilicon layer on the dielectric oxide layer, forming a first isolation opening above the first superlattice structure and the second superlattice structure, forming a second isolation opening between the first superlattice structure and the second superlattice structure, and depositing a dielectric layer in the first isolation opening and the second isolation opening to form an isolation structure. The step of forming the first isolation opening includes forming a first metal oxide layer on a first portion of the dielectric oxide layer exposed during formation of the first isolation opening. The step of forming the second isolation opening includes forming a second metal oxide layer on a second portion of the dielectric oxide layer exposed during formation of the second isolation opening.

[0107] In some embodiments, a method includes forming a first superlattice structure and a second superlattice structure on a substrate, forming a first protective layer around the first superlattice structure and the second superlattice structure, forming a polysilicon structure on the first protective layer, forming a poly cut opening between the first superlattice structure and the second superlattice structure, depositing a dielectric layer in the poly cut opening, forming a gate opening in the first superlattice structure and the second superlattice structure, removing a portion of the first protective layer in the gate opening, and forming a gate structure in the gate opening. The step of forming the poly cut opening includes forming a second protective layer on a portion of the first protective layer exposed during formation of the poly cut opening.

[0108] In some embodiments, a semiconductor device includes a substrate, a first nanostructure channel region disposed on the substrate, a first gate structure surrounding the first nanostructure channel region, a second nanostructure channel region disposed on the substrate, a second gate structure surrounding the second nanostructure channel region, an isolation structure disposed between the first nanostructure channel region and the second nanostructure channel region, a first protective oxide layer disposed between the first nanostructure channel region and the isolation structure, and a second protective oxide layer disposed between the second nanostructure channel region and the isolation structure.

[0109] The components of the above-described embodiments are summarized in order that those skilled in the art can better understand the present embodiments. Those skilled in the art should understand that they can design or modify other processes and structures according to the present embodiments, in order to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present embodiments, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present embodiments.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; a first nanostructure channel region disposed on the substrate; a first gate structure surrounding the first nanostructure channel region; a second nanostructure channel region disposed on the substrate; a second gate structure surrounding the second nanostructure channel region; an isolation structure disposed between the first nanostructure channel region and the second nanostructure channel region; a first protective oxide layer disposed between the first nanostructure channel region and the isolation structure; and a second protective oxide layer disposed between the second nanostructure channel region and the isolation structure. The isolation structure comprises a T-shaped cross-sectional profile.

2. The semiconductor device according to claim 1, wherein The T-shaped cross-sectional profile comprises a first portion extending vertically between the first nanostructure channel region and the second nanostructure channel region.

3. The semiconductor device according to claim 2, wherein The T-shaped cross-sectional profile comprises a second portion extending horizontally above the first nanostructure channel region and the second nanostructure channel region.

4. The semiconductor device according to claim 3, wherein The first protective oxide layer is in contact with a high-k gate dielectric layer of the first gate structure.

5. The semiconductor device according to claim 1, wherein The first nanostructure channel region and the second nanostructure channel region have a thickness of 3 nm to 15 nm.

6. The semiconductor device according to claim 1 or 2, wherein The first protective oxide layer and the second protective oxide layer have a thickness of 2 nm to 3 nm.

7. The semiconductor device according to claim 1, wherein Further comprising a first fin base and a second fin base, wherein the first fin base is located below the first nanostructure channel region and the second fin base is located below the second nanostructure channel region.

8. The semiconductor device according to claim 1, wherein A bottom surface of the isolation structure is coplanar with top surfaces of the first fin base and the second fin base.

9. The semiconductor device according to claim 8, wherein The first protective oxide layer is disposed on sidewalls of the first nanostructure channel region and the second protective oxide layer is disposed on sidewalls of the second nanostructure channel region.

10. The semiconductor device according to claim 1, wherein ​

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