Packaging module
By incorporating reinforcing components and conductive pillars into a monolithic architecture within the packaging module, the warping problem of fan-out packaging structures is resolved, achieving stable connection to external devices and meeting the demands for multifunctionality and lightweight compactness.
Patent Information
- Application Number
- CN202520204166.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-03
- Filing Date
- 2025-02-10
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-02-10
AI Technical Summary
Existing fan-out packaging structures are difficult to manufacture and have a high risk of warpage when used in ultra-thin and ultra-large packaging, making it difficult to meet the development needs of multi-functionality and lightweight and compact designs.
The packaging module adopts a monolithic architecture. By setting reinforcement components on multiple packaging units and forming circuit structures and conductive pillars on the carrier board, combined with bridging chips and encapsulation layers, a fan-out embedded bridging or multi-chip structure is formed, and independent packaging units are obtained through a single-chip dicing process.
It enhances the overall strength of the packaging structure, mitigates warping issues, ensures stable mounting of the packaging unit on external devices, and eliminates the need for additional materials or processes, thus avoiding extra costs.
Smart Images
Figure CN223885642U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor packaging technology, in particular to a packaging module comprising a plurality of packaging units. BACKGROUND
[0002] High performance computing (HPC) technology is increasingly important and widely used in today's world, such as medical technology development, such as the development of cancer drugs, or automatic sensing detection operations of autonomous vehicles. The packaging structure used in devices applied to these fields is mostly a fan-out package (FOPKG) structure. For example, fan-out multi-chip (FOMCM) structure and fan-out embedded bridge die (FOEB) structure, which has the needs of multi-chip, high line count, large fan-out size, and high heat dissipation design.
[0003] Please refer to Figure 1 , which is a conventional fan-out package (FOPKG) structure. The chip 11 is embedded in the encapsulation layer 15, and then the redistribution layer (RDL) 10 is formed on the top, and then the functional chip 16 is placed on the redistribution layer 10. In this way, the functional chip 16 and the chip 11 embedded in the encapsulation layer 15 can be vertically communicated to meet the high-speed transmission requirement.
[0004] However, to meet the development trend of multi-functional and thin and small electronic products, when the ultra-thin packaging structure (such as the packaging structure thickness is less than 300um) and the ultra-large packaging structure (the packaging structure size is greater than 70x70mm-100x100mm), it is easy to cause the difficulty of wafer mode manufacturing process to increase and the high risk of warping deformation when the packaging structure is placed on the circuit board.
[0005] Therefore, how to overcome the shortcomings of the prior art is a technical problem that the current community is eager to solve. CONTENT OF THE INVENTION
[0006] In view of the shortcomings of the prior art described above, the present application provides a packaging module in a whole piece architecture, comprising a plurality of packaging units arranged on a temporary carrier. Each packaging unit comprises a reinforcement arranged on the temporary carrier, a plurality of electronic elements arranged on the reinforcement, and a circuit structure formed on the plurality of electronic elements and electrically connected to the circuit structure.
[0007] The application also provides a method for manufacturing a packaging module. The packaging module has a monolithic architecture and includes a plurality of packaging regions. The method includes forming a circuit structure on a carrier plate; disposing a plurality of electronic components on the circuit structure and electrically connecting the plurality of electronic components to the circuit structure; disposing a reinforcement on the plurality of electronic components; removing the carrier plate; disposing the reinforcement on a temporary carrier; and singulating along each of the packaging regions to form a plurality of packaging units.
[0008] The packaging module and the method for manufacturing the packaging module further include a plurality of conductive pillars disposed on the circuit structure and electrically connected to the circuit structure.
[0009] The packaging module and the method for manufacturing the packaging module further include a bridge chip disposed on the circuit structure and electrically connected to the circuit structure.
[0010] The packaging module and the method for manufacturing the packaging module further include a coating layer disposed on the circuit structure and covering the bridge chip and the plurality of conductive pillars.
[0011] The packaging module and the method for manufacturing the packaging module further include a circuit portion disposed on the coating layer and electrically connected to the plurality of conductive pillars.
[0012] The packaging module and the method for manufacturing the packaging module further include a plurality of conductive elements disposed on the circuit portion and electrically connected to the circuit portion.
[0013] The packaging module and the method for manufacturing the packaging module further include a plurality of conductive elements disposed on the circuit structure and electrically connected to the circuit structure.
[0014] The packaging module and the method for manufacturing the packaging module further include a packaging layer formed on the circuit structure and covering the plurality of electronic components.
[0015] The packaging module and the method for manufacturing the packaging module have a fan-out embedded bridge structure or a fan-out multi-chip structure.
[0016] As can be seen from the above, the packaging module of the application has a reinforcement disposed on the plurality of electronic components of the plurality of packaging units of the monolithic architecture to strengthen the overall structural strength and slow down the warping problem. The reinforcement can be used to control the warping phenomenon when the packaging units are subsequently disposed in an external device. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 FIG. 4 is a cross-sectional view of a conventional fan-out packaging structure.
[0018] Figures 2A to 2G FIG. 5 is a cross-sectional view of a first embodiment of the packaging module and the method for manufacturing the packaging module of the application.
[0019] Figure 3 Application profile of the first embodiment of the packaging module of the present application.
[0020] Figures 4A to 4D Application profile of the second embodiment of the packaging module and the manufacturing method thereof of the present application.
[0021] Figure 5 Application profile of the second embodiment of the packaging module of the present application.
[0022] Explanation of reference numerals
[0023] 10 circuit redistribution layer
[0024] 11 chip
[0025] 15 encapsulation layer
[0026] 16 functional chip
[0027] 2, 4 packaging module
[0028] 2a, 4a packaging unit
[0029] 20, 40 circuit structure
[0030] 200 dielectric layer
[0031] 201 circuit redistribution layer
[0032] 21 bridge chip
[0033] 21a active surface
[0034] 21b non-active surface
[0035] 210 conductive body
[0036] 212 bonding layer
[0037] 23 conductive pillar
[0038] 24 circuit portion
[0039] 25 encapsulation layer
[0040] 25a first surface
[0041] 25b second surface
[0042] 26, 46 electronic element
[0043] 260 underfill
[0044] 27, 47 reinforcement
[0045] 28, 48 encapsulation layer
[0046] 29,49 Conductive elements
[0047] 30, 50 External devices
[0048] 31,51 Heat sink
[0049] 8 Temporary carrier
[0050] 9. Support plate
[0051] 91. Insulation layer. Detailed Implementation
[0052] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0053] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0054] Please see Figures 2A to 2G This is a cross-sectional schematic diagram of the first embodiment of the packaging module and its manufacturing method of this application. The packaging module of this application is implemented in a monolithic architecture such as wafer form or panel form, and includes multiple packaging areas.
[0055] like Figure 2A As shown, a carrier plate 9 is provided, and a plurality of conductive pillars 23 and a plurality of bridging chips 21 are formed on the carrier plate 9.
[0056] In this embodiment, the carrier plate 9 can sequentially form a release layer, an insulating layer 91 such as a dielectric material or a solder mask material, and a seed layer such as titanium / copper, so that the seed layer is disposed on the insulating layer 91, and a patterned resist layer is formed on the seed layer, so as to form a plurality of conductive pillars 23, wherein the material of the conductive pillars 23 is a metal material such as copper or a solder material. After the plurality of conductive pillars 23 are made, the patterned resist layer and the seed layer thereunder are removed, and a plurality of bridge chips 21 are disposed on the carrier plate 9, and the plurality of conductive pillars 23 surround the bridge chips 21, wherein the bridge chips 21 are combined and electrically connected with a plurality of conductive bodies 210, and the plurality of conductive bodies 210 are spherical such as solder balls, or columnar such as copper columns, solder bumps, or stud conductive members made by a solder wire machine, but are not limited thereto.
[0057] In addition, the bridge chip 21 has opposite active surfaces 21a and non-active surfaces 21b, the bridge chip 21 is fixed to the insulating layer 91 by a bonding layer 212 with the non-active surfaces 21b, the active surfaces 21a have a plurality of electrode pads and a protective film such as a passivation material, and the conductive bodies 210 are disposed on the electrode pads and embedded in the protective film.
[0058] As shown in Figure 2B , an encapsulation layer 25 is formed on the insulating layer 91 of the carrier plate 9, so that the encapsulation layer 25 encapsulates the bridge chip 21, the plurality of conductive bodies 210, and the plurality of conductive pillars 23, wherein the encapsulation layer 25 has opposite first and second surfaces 25a and 25b, and the encapsulation layer 25 is combined to the insulating layer 91 of the carrier plate 9 with the second surface 25b. In this embodiment, the encapsulation layer 25 is an insulating material such as polyimide (PI), a dry film, a packaging adhesive such as epoxy, or a molding compound.
[0059] Further, through a planarization process, the first surface 25a of the encapsulation layer 25 is flush with the end surfaces of the plurality of conductive pillars 23 and the end surfaces of the plurality of conductive bodies 210, so that the end surfaces of the plurality of conductive pillars 23 and the end surfaces of the plurality of conductive bodies 210 are exposed to the first surface 25a of the encapsulation layer 25.
[0060] As shown in Figure 2C , a wiring structure 20 is formed on the first surface 25a of the encapsulation layer 25, and the wiring structure 20 is electrically connected with the plurality of conductive pillars 23 and the plurality of conductive bodies 210.
[0061] In this embodiment, the circuit structure 20 includes multiple dielectric layers 200 and multiple redistribution layers (RDLs) 201 disposed on the dielectric layers 200. Alternatively, the circuit structure 20 may include only a single dielectric layer 200 and a single redistribution layer 201.
[0062] Furthermore, the material forming the circuit redistribution layer 201 is copper, and the material forming the dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0063] like Figure 2D As shown, multiple electronic components 26 are disposed on the circuit structure 20, and then the multiple electronic components 26 are covered by an encapsulation layer 28.
[0064] In this embodiment, the electronic component 26 may be an active component, a passive component, or a combination of both. In one embodiment, the electronic component 26 may be, for example, a graphics processing unit (GPU) or a high-bandwidth memory (HBM) semiconductor chip.
[0065] Furthermore, the electronic component 26 is electrically connected to the circuit structure 20 through multiple conductive bumps such as solder bumps, copper bumps, or others, and at least two other electronic components 26 can be electrically connected to each other through the bridging chip 21.
[0066] Furthermore, the encapsulation layer 28 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin, which can be formed on the circuit structure 20 by lamination or molding. It should be understood that the material forming the encapsulation layer 28 may be the same as or different from the material of the covering layer 25.
[0067] Alternatively, an adhesive base 260 can be formed first between the electronic component 26 and the circuit structure 20 to cover the plurality of conductive bumps, and then the encapsulation layer 28 can be formed to cover the adhesive base 260 and the plurality of electronic components 26. The aforementioned adhesive base 260 may be selectively formed or not formed between the electronic component 26 and the circuit structure 20.
[0068] Furthermore, by thinning the process, some material of the encapsulation layer 28 and some material of the plurality of electronic components 26 are removed, so that the upper surface of the encapsulation layer 28 is flush with the upper surface of the plurality of electronic components 26, thereby exposing the plurality of electronic components 26 to the encapsulation layer 28.
[0069] like Figure 2E As shown, a reinforcing member 27 is provided on the plurality of electronic components 26. The reinforcing member 27 is, for example, a plate made of semiconductor material (such as silicon or glass).
[0070] like Figure 2F As shown, the carrier plate 9 and its release layer and metal layer are then removed, and a circuit portion 24 is formed on the cover layer 25 to electrically connect the plurality of conductive posts 23. The circuit portion 24 may also include an insulating layer 91 and a bump under metal layer (UBM) to bond conductive elements 29 such as a plurality of solder bumps or solder balls (of type C4); or, the circuit portion 24 may be formed on the cover layer 25 through an RDL process to bond the conductive elements 29.
[0071] like Figure 2G As shown, after the reinforcing member 27 is placed on a temporary carrier 8, a cutting process is performed along each packaging area to obtain a packaging module 2 containing multiple packaging units 2a. The temporary carrier 8 is an adhesive carrier, such as tape.
[0072] Through the aforementioned manufacturing method, this application provides a packaging module 2, which has a monolithic architecture and includes a plurality of packaging units 2a disposed on a temporary carrier 8. Each packaging unit 2a includes: a reinforcing member 27 disposed on the temporary carrier 8; a plurality of electronic components 26 disposed on the reinforcing member 27; and a circuit structure 20 formed on the plurality of electronic components 26, and the plurality of electronic components 26 are electrically connected to the circuit structure 20.
[0073] In this embodiment, each of the packaging units 2a is, for example, a fan-out embedded bridge (FOEB) structure, which further includes a cover layer 25 disposed on the circuit structure 20, a plurality of conductive pillars 23 embedded in the cover layer 25 and a bridge chip 21, a circuit portion 24 disposed on the cover layer 25 and a plurality of conductive elements 29 disposed on the circuit portion 24.
[0074] The bridging chip 21 and the plurality of conductive posts 23 are electrically connected to the circuit structure 20. The plurality of conductive posts 23 are embedded in the cladding layer 25 and surround the bridging chip 21. The circuit section 24 is electrically connected to the plurality of conductive posts 23 and the plurality of conductive elements 29.
[0075] In one embodiment, each of the packaging units 2a further includes a packaging layer 28 formed on the circuit structure 20 and covering the plurality of electronic components 26.
[0076] Referring to Figure 3 , the packaging units 2a can be subsequently placed on an external device 30 (e.g., a circuit board) through the plurality of conductive elements 29, and then the reinforcement 27 is removed and a heat dissipation element 31 is disposed on the external device 30.
[0077] Referring to Figures 4A to 4D , a cross-sectional view of a second embodiment of a packaging module and a method of manufacturing the same is shown. The packaging module of the present application is in a whole piece architecture, such as a wafer form or a panel form, and includes a plurality of packaging regions.
[0078] As shown in Figure 4A , a carrier plate 9 is provided, and a circuit structure 40 is formed on the carrier plate 9, and then a plurality of electronic elements 46 are disposed on the circuit structure 40. The circuit structure 40 includes a plurality of dielectric layers and a plurality of circuit redistribution layers, and the electronic elements 46 are active elements, passive elements, or a combination of both.
[0079] As shown in Figure 4B , a packaging layer 48 covering the plurality of electronic elements 46 is formed on the circuit structure 40, and a thinning process is performed to remove part of the material of the packaging layer 48 and part of the material of the plurality of electronic elements 46, so that the upper surface of the packaging layer 48 is flush with the upper surface of the plurality of electronic elements 46, so that the plurality of electronic elements 46 are exposed to the packaging layer 48.
[0080] As shown in Figure 4C , a reinforcement 47 is disposed on the plurality of electronic elements 46. The reinforcement 47 is, for example, a plate body of a semiconductor material (such as silicon or glass), and the carrier plate 9 is removed to expose the circuit structure 40, and then a plurality of conductive elements 49 are disposed on the circuit structure 40.
[0081] As shown in Figure 4D , after the reinforcement 47 is placed on a temporary carrier 8, a singulation process is performed along each packaging region, and a packaging module 4 including a plurality of packaging units 4a is obtained.
[0082] Through the foregoing method, the present application provides a packaging module 4 in a whole piece architecture and including a plurality of packaging units 4a disposed on a temporary carrier 8, wherein each packaging unit 4a includes: a reinforcement 47 disposed on the temporary carrier 8; a plurality of electronic elements 46 disposed on the reinforcement 47; and a circuit structure 40 formed on the plurality of electronic elements 46 and electrically connecting the plurality of electronic elements 46.
[0083] In this embodiment, the packaging units 4a are, for example, fan-out multi-chip (FOMCM) structures, which further include a plurality of conductive elements 49 disposed on the circuit structure 40, and a packaging layer 48 covering the plurality of electronic elements 46, and the plurality of conductive elements 49 are electrically connected to the circuit structure 40.
[0084] Referring to Figure 5 Subsequently, the packaging units 4a can be mounted on an external device 50 (for example, a circuit board) through the plurality of conductive elements 49, and then the reinforcing member 47 is removed and a heat dissipation member 51 is disposed on the external device 50.
[0085] In summary, the packaging module of the present application is provided with a reinforcing member on the plurality of electronic elements of the plurality of packaging units in the whole piece structure, so as to reinforce the overall structural strength and slow down the warping problem. At the same time, when the packaging units are subsequently mounted on the external device, the warping phenomenon can be controlled through the setting of the reinforcing member. In addition, the above-mentioned structure does not need to increase the development process and materials or purchase equipment, and the existing materials and old process and equipment can solve the existing technical problems in the industry, so there will be no large additional cost.
[0086] The above embodiments are only used to illustrate the principles and effects of the present application, and are not used to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be as listed in the claims.
Claims
1. A package module comprising a plurality of package units disposed on a temporary carrier, wherein, Each of the packaging units comprises: a reinforcement disposed on the temporary carrier; a plurality of electronic elements disposed on the reinforcement; and a circuit structure formed on the plurality of electronic elements and electrically connecting the plurality of electronic elements.
2. The package module of claim 1, wherein The packaging module further comprises a plurality of conductive pillars disposed on the circuit structure and electrically connecting the circuit structure.
3. The package module of claim 2, wherein The packaging module further comprises a bridge chip disposed on the circuit structure and electrically connecting the circuit structure.
4. The package module of claim 3, wherein The packaging module further comprises a covering layer disposed on the circuit structure and covering the bridge chip and the plurality of conductive pillars.
5. The package module of claim 4, wherein the first and second package modules are connected to each other by a plurality of conductive bumps. The packaging module further comprises a circuit portion disposed on the covering layer and electrically connecting the plurality of conductive pillars.
6. The package module of claim 5, wherein the first and second package modules are connected to each other by a flexible printed circuit board. The packaging module further comprises a plurality of conductive elements disposed on the circuit portion and electrically connecting the circuit portion.
7. The package module of claim 1, wherein The packaging module further comprises a plurality of conductive elements disposed on the circuit structure and electrically connecting the circuit structure.
8. The package module of claim 1, wherein The packaging module further comprises a packaging layer formed on the circuit structure and covering the plurality of electronic elements.
9. The package module of claim 1, wherein The packaging units are fan-out embedded bridge structures or fan-out multi-chip structures.