VPX AI chassis architecture

Abstract

The utility model discloses a VPX AI case framework, and relates to the technical field of case design. Comprising a 6U VPX connector, a first computing board, a second computing board, a first switching board, a second switching board, a first power board, a second power board, a first AI board group and a second AI board group, the 6U VPX connector is connected with the first computing board, the second computing board, the first switching board, the second switching board, the first power board, the second power board, the first AI board group and the second AI board group; the first computing board is provided with a first CPU module and a first data exchange chip; the second computing board is provided with a second CPU module and a second data exchange chip; the first exchange board is provided with a third data exchange chip; and the second exchange board is provided with a fourth data exchange chip. The beneficial effects of the utility model are that the parallel computing capability of the server can be optimized, and the user experience can be improved.

Description

Technical Field

[0001] This utility model relates to the field of chassis design technology, and more specifically, to a VPX AI chassis architecture. Background Technology

[0002] VPX is a new generation of high-speed serial bus standard proposed by VITA (VME International Trade Association) in 2007 based on its VME bus. It is mainly used in military, aerospace, embedded systems and other fields.

[0003] To adapt to the design of VPX and chassis architecture, this utility model provides a VPX AI chassis architecture that can optimize the parallel computing capabilities of the server and improve the user experience. Utility Model Content

[0004] To overcome the shortcomings of existing technologies, this invention provides a VPX AI chassis architecture that can optimize the parallel computing capabilities of servers and improve user experience.

[0005] The technical solution adopted by this utility model to solve its technical problem is: a VPX AI chassis architecture, the improvement of which is that the VPX AI chassis architecture includes a 6U VPX connector, a first computing board, a second computing board, a first switching board, a second switching board, a first power board, a second power board, a first AI board group, and a second AI board group; the 6U VPX connector is connected to the first computing board, the second computing board, the first switching board, the second switching board, the first power board, the second power board, the first AI board group, and the second AI board group;

[0006] The first computing board is provided with a first CPU module and a first data exchange chip; the second computing board is provided with a second CPU module and a second data exchange chip; the first exchange board is provided with a third data exchange chip; the second exchange board is provided with a fourth data exchange chip; the first data exchange chip is connected to the first CPU module, the second CPU module, the second data exchange chip, and the third data exchange chip; the second data exchange chip is connected to the first CPU module, the second CPU module, and the fourth data exchange chip; the third data exchange chip is connected to the first AI board group; and the fourth data exchange chip is connected to the second AI board group.

[0007] In the above structure, the VPX AI chassis architecture also includes a network communication module; the network communication module is connected to the third data exchange board, the fourth data exchange board, and the 6U VPX connector.

[0008] In the above structure, the 6U VPX connector includes a P0 interface, a P1 interface, a P2 interface, a P3 interface, a P4 interface, a P5 interface, and a P6 interface; the P0 interface is connected to the first power board and the second power board; the P1 interface is connected to the first CPU module and the second CPU module; the P2 interface is connected to the network communication module; and the P3, P4, P5, and P6 interfaces are connected to the first AI board group, the second AI board group, the third data exchange chip, and the fourth data exchange chip.

[0009] In the above structure, the first AI board group and the second AI board group are each equipped with 4 AI blades; the AI ​​blades are respectively connected to the P3 interface, P4 interface, P5 interface and P6 interface.

[0010] In the above structure, both the first computing board and the second computing board are provided with a BMC module and a CPLD module; the BMC module is connected to the P0 interface and the CPLD module; the CPLD module is connected to the first CPU module / second CPU module.

[0011] In the above structure, the VPX AI chassis architecture also includes a reset button, a USB interface, a debug interface, and an indicator light circuit; the reset button, USB interface, debug interface, and indicator light circuit are all connected to the CPLD module.

[0012] In the above structure, the first computing board and the second computing board are further provided with an X100 module, an mSATA module, an onboard SSD module and a video interface converter. The X100 module is connected to the mSATA module, the onboard SSD module, the video interface converter and the first CPU module / second CPU module.

[0013] In the above structure, the VPX AI chassis architecture also includes a VGA interface, which is connected to a video interface converter.

[0014] In the above structure, the model of the first data exchange chip and the model of the second data exchange chip are both PEX88064.

[0015] In the above structure, the model of the third data exchange chip and the model of the fourth data exchange chip are both PEX88096.

[0016] The beneficial effects of this utility model are as follows: The VPX AI chassis architecture of this utility model integrates two computing boards, two switching boards, two AI board groups, and two power supply boards, which are connected through a 6U VPX connector. The second computing board and the two switching boards are equipped with data exchange chips, so that the first CPU module / second CPU module can exchange data with the first AI board group through the first data exchange chip and the third data exchange chip; and can exchange data with the second AI board group through the second data exchange chip and the fourth data exchange chip. This can optimize the parallel computing capability of the server and improve the user experience. Attached Figure Description

[0017] Figure 1 This utility model provides a connection frame for a VPX AI chassis architecture. Figure 1 ;

[0018] Figure 2 This utility model provides a connection frame for a VPX AI chassis architecture. Figure 2 ;

[0019] Figure 3 This is a diagram showing the connection of the computing board in a VPX AI chassis architecture according to this utility model;

[0020] Figure 4 This is a connection diagram of the switching board of a VPX AI chassis architecture according to this utility model. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] The following will clearly and completely describe the concept, specific structure, and technical effects of this utility model in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are all within the scope of protection of this utility model. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this utility model can be combined interactively without contradicting each other.

[0023] Reference Figure 1 and Figure 2As shown, this utility model discloses a VPX AI chassis architecture, which includes a 6U VPX connector, a first computing board, a second computing board, a first switching board, a second switching board, a first power board, a second power board, a first AI board group, and a second AI board group; the 6U The VPX connector connects to a first computing board, a second computing board, a first switching board, a second switching board, a first power board, a second power board, a first AI board group, and a second AI board group. The first computing board is equipped with a first CPU module and a first data exchange chip. The second computing board is equipped with a second CPU module and a second data exchange chip. The first switching board is equipped with a third data exchange chip. The second switching board is equipped with a fourth data exchange chip. The first data exchange chip is connected to the first CPU module, the second CPU module, the second data exchange chip, and the third data exchange chip. The second data exchange chip is connected to the first CPU module, the second CPU module, and the fourth data exchange chip. The third data exchange chip is connected to the first AI board group. The fourth data exchange chip is connected to the second AI board group. The model of the first data exchange chip and the model of the second data exchange chip are both PEX88064. The model of the third data exchange chip and the model of the fourth data exchange chip are both PEX88096.

[0024] It should be noted that, in this embodiment, the 6U VPX connector is a physical interface standard used to provide electrical connections between the first computing board, the second computing board, the first switching board, the second switching board, the first power board, the second power board, the first AI board group, and the second AI board group. 6U indicates the size, typically 160mm × 233mm, suitable for high-density, high-performance systems. The first and second computing boards are used to perform computing tasks and exchange data within the computer system. Specifically, the first computing board includes a first CPU module and a first data exchange chip; the second computing board includes a second CPU module and a second data exchange chip. The first and second CPU modules serve as high-performance processing units for AI computing within the AI ​​chassis. The first and second data exchange chips are responsible for high-speed data transmission between the boards, ensuring... Data flows smoothly during the calculation process; the first and second switching boards act as bridges for data flow between various components in the computer system, enabling high-speed data exchange between different boards; specifically, the first switching board is equipped with a third data exchange chip; the second switching board is equipped with a fourth data exchange chip. The third data exchange chip is used to transmit data from the first and second computing boards to the first AI board group; the fourth data exchange chip is used to transmit data from the first and second computing boards to the second AI board group; the first and second power boards provide the required voltage and current to the system, ensuring stable operation of the entire system; the first and second AI board groups serve as dedicated hardware for AI computing, used to perform efficient AI calculations; in the specific implementation of this utility model, the VPX of this embodiment... The AI ​​chassis architecture integrates two computing boards, two switching boards, two AI board groups, and two power boards, connected via a 6U VPX connector. Each of the second computing board and the two switching boards is equipped with a data exchange chip. The first, second, third, and fourth data exchange chips utilize a high-bandwidth, low-latency data transmission mechanism to enable efficient data exchange between different computing boards, AI board groups, and other components. The design of the first and second computing boards allows the computer system to process multiple tasks in parallel, and each computing board is equipped with an independent CPU (first CPU module / second CPU module) to execute different computing tasks simultaneously, thereby accelerating the overall computing process. Therefore, the VPX AI chassis architecture of this embodiment optimizes the server's parallel computing capabilities and enhances the user experience.

[0025] It should also be noted that the 6U VPX connector ensures that the load is evenly distributed between the first and second computing boards through the switching board and data switching chip, thereby avoiding overload of any one computing board. Furthermore, the 6U VPX connector employs low-latency switching technology to ensure that data can be quickly transmitted to the required computing board or AI board group, thus preventing data transmission from becoming a performance bottleneck and optimizing overall parallel computing performance. In addition, the 6U VPX connector has high reliability and redundancy mechanisms to ensure that the computing process is not interrupted by hardware failures, thereby reducing downtime caused by hardware problems and improving computing efficiency.

[0026] Reference Figure 1 As shown, the VPX AI chassis architecture also includes a network communication module; the network communication module is connected to the third data exchange board, the fourth data exchange board, and the 6U VPX connector.

[0027] It should be noted that, in this embodiment, the network communication module is used to process and manage data streams and transmit data to other parts of the computer system through a high-speed network. Specifically, the network communication module provides a high-speed data exchange interface between various boards, and can manage data streams, route data packets, and ensure that data can flow smoothly to the correct destination. The network communication module can support high-speed communication protocols such as Ethernet, Fibre Channel, and InfiniBand, ensuring that data can be transmitted quickly and efficiently in the system.

[0028] Reference Figure 3 and Figure 4 As shown, the 6U VPX connector includes a P0 interface, a P1 interface, a P2 interface, a P3 interface, a P4 interface, a P5 interface, and a P6 interface; the P0 interface is connected to the first power board and the second power board; the P1 interface is connected to the first CPU module and the second CPU module; the P2 interface is connected to the network communication module; and the P3, P4, P5, and P6 interfaces are connected to the first AI board group, the second AI board group, the third data exchange chip, and the fourth data exchange chip.

[0029] It should be noted that, in this embodiment, the 6U VPX connector is designed with P0, P1, P2, P3, P4, P5, and P6 interfaces. The P0 interface consists of 8 pieces, primarily used for providing power and signal transmission, including 3 power contact pieces (providing +12V and +3.3V), 3 single-ended signal contact pieces (for low-speed control signals), and 2 differential signal contact pieces (for high-speed data transmission). The P1 to P6 interfaces consist of 16 pieces, primarily used for differential signal transmission. Each interface has 16 sets of differential signal pairs. These interfaces provide high-speed data exchange capabilities between boards, suitable for high-bandwidth, high-speed applications such as AI computing, network communication, and data exchange.

[0030] Reference Figure 1 and Figure 2 As shown, both the first AI board group and the second AI board group are equipped with 4 AI blades; the AI ​​blades are connected to the P3 interface, P4 interface, P5 interface and P6 interface respectively.

[0031] It should be noted that, in this embodiment, the AI ​​blade is a hardware module used to perform artificial intelligence computing tasks, which is usually composed of specially designed acceleration chips. Each AI blade in this embodiment can be used as an independent computing unit to perform high-speed parallel computing in AI inference, training and other tasks, and realize high-speed data transmission between the AI ​​blade and the first CPU module / second CPU module through high-speed data transmission channels such as P3 interface, P4 interface, P5 interface and P6 interface.

[0032] Reference Figure 3 and Figure 4 As shown, both the first and second computing boards are equipped with a BMC module and a CPLD module; the BMC module is connected to the P0 interface and the CPLD module; the CPLD module is connected to the first CPU module / second CPU module.

[0033] It should be noted that, in this embodiment, the BMC module is a controller specifically designed for hardware management. It is used to obtain real-time hardware status through the CPLD and CPU modules and handle abnormal situations in a timely manner. For example, when the BMC detects that the temperature is too high, it may notify the CPU module through the CPLD module to make corresponding adjustments or issue an alarm. The CPLD module is a programmable logic device used to execute customized logic tasks. It can support functions such as timing management, protocol conversion, and signal synchronization, and assist the BMC module and CPU module in coordinating their work.

[0034] Reference Figure 3 and Figure 4As shown, the VPX AI chassis architecture also includes a reset button, a USB interface, a debugging interface, and an indicator light circuit; the reset button, USB interface, debugging interface, and indicator light circuit are all connected to the CPLD module.

[0035] It should be noted that, in this embodiment, the reset button is a common hardware interface in computer systems, used to manually restart the system or device. When the computer system malfunctions or needs to be reinitialized, the user can press the reset button to force the system to restart. The USB interface is used for data transmission and external device connection, typically for connecting external storage devices, mice, keyboards, and other peripherals. The debug interface is used for system development and fault diagnosis, allowing developers or maintenance personnel to access internal data, read logs, or troubleshoot through this interface. The indicator light circuit is used to display the system's operating status, such as power status, hardware faults, and operating mode.

[0036] Reference Figure 3 and Figure 4 As shown, the first computing board and the second computing board are also provided with an X100 module, an mSATA module, an onboard SSD module and a video interface converter. The X100 module is connected to the mSATA module, the onboard SSD module, the video interface converter and the first CPU module / second CPU module.

[0037] It should be noted that, in this embodiment, the X100 module is used to provide an expansion interface, including a high-speed storage interface and a USB expansion interface; the mSATA module is a miniaturized solid-state drive (SSD) used to provide high-speed data read and write storage, such as in embedded devices, servers, and other computer systems; the onboard SSD module is a solid-state drive (SSD) directly integrated onto the computing board, used to provide the main storage for the computer system; and the video interface converter is used to convert video signals from one format to another, typically to support compatibility between different display devices or video output standards.

[0038] Reference Figure 3 and Figure 4 As shown, the VPX AI chassis architecture also includes a VGA interface, which is connected to a video interface converter.

[0039] It should be noted that, in this embodiment, the VGA interface is a traditional video output standard used to transmit image signals from a computer or other device to a display device (such as a monitor, projector, etc.).

[0040] The above is a detailed description of the preferred embodiments of the present utility model. However, the present utility model is not limited to the described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present utility model. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A VPX AI chassis architecture, characterized in that, The VPX AI chassis architecture includes a 6U VPX connector, a first computing board, a second computing board, a first switching board, a second switching board, a first power board, a second power board, a first AI board group, and a second AI board group; the 6U VPX connector is connected to the first computing board, the second computing board, the first switching board, the second switching board, the first power board, the second power board, the first AI board group, and the second AI board group. The first computing board is provided with a first CPU module and a first data exchange chip; the second computing board is provided with a second CPU module and a second data exchange chip; the first exchange board is provided with a third data exchange chip; the second exchange board is provided with a fourth data exchange chip; the first data exchange chip is connected to the first CPU module, the second CPU module, the second data exchange chip, and the third data exchange chip; the second data exchange chip is connected to the first CPU module, the second CPU module, and the fourth data exchange chip; the third data exchange chip is connected to the first AI board group; and the fourth data exchange chip is connected to the second AI board group.

2. The VPX AI chassis architecture according to claim 1, characterized in that, The VPX AI chassis architecture also includes a network communication module; the network communication module is connected to the third data exchange board, the fourth data exchange board, and the 6U VPX connector.

3. The VPX AI chassis architecture according to claim 2, characterized in that, The 6U VPX connector includes a P0 interface, a P1 interface, a P2 interface, a P3 interface, a P4 interface, a P5 interface, and a P6 interface; the P0 interface is connected to the first power board and the second power board; the P1 interface is connected to the first CPU module and the second CPU module; the P2 interface is connected to the network communication module; and the P3, P4, P5, and P6 interfaces are connected to the first AI board group, the second AI board group, the third data exchange chip, and the fourth data exchange chip.

4. The VPX AI chassis architecture according to claim 3, characterized in that, The first AI board group and the second AI board group are each equipped with 4 AI blades; the AI ​​blades are respectively connected to the P3 interface, P4 interface, P5 interface and P6 interface.

5. The VPX AI chassis architecture according to claim 4, characterized in that, Both the first and second computing boards are equipped with a BMC module and a CPLD module; the BMC module is connected to the P0 interface and the CPLD module; the CPLD module is connected to the first CPU module / second CPU module.

6. The VPX AI chassis architecture according to claim 5, characterized in that, The VPX AI chassis architecture also includes a reset button, a USB interface, a debug interface, and an indicator light circuit; the reset button, USB interface, debug interface, and indicator light circuit are all connected to the CPLD module.

7. The VPX AI chassis architecture according to claim 1, characterized in that, The first and second computing boards are also equipped with an X100 module, an mSATA module, an onboard SSD module, and a video interface converter. The X100 module is connected to the mSATA module, the onboard SSD module, the video interface converter, and the first CPU module / second CPU module.

8. The VPX AI chassis architecture according to claim 7, characterized in that, The VPX AI chassis architecture also includes a VGA interface, which is connected to a video interface converter.

9. The VPX AI chassis architecture according to claim 1, characterized in that, The model of the first data exchange chip and the model of the second data exchange chip are both PEX88064.

10. The VPX AI chassis architecture according to claim 1, characterized in that, The model numbers of the third and fourth data exchange chips are both PEX88096.

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