Memory allocator for in-chip memory multi-interface access of SOC (system on chip)
By designing a memory allocator for SOC systems, employing multiplexer groups and interface matrices, the problem of multiprocessor access management to on-chip memory in SOC systems is solved, achieving optimized allocation of memory resources and enhanced system flexibility and scalability.
Patent Information
- Application Number
- CN202423240110.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2034-12-26
AI Technical Summary
Existing technologies struggle to effectively manage the flexible access and dynamic allocation of on-chip memory by multiple processors in a System-on-a-Chip (SoC) system, impacting system reliability and scalability.
A memory allocator is designed, comprising on-chip memory, a first interface group, a second interface, and a multiplexer group. By combining the multiplexer group and the interface matrix, flexible access to multiple processors and optimized allocation of memory resources are achieved. A two-to-one multiplexer and a switch matrix are used to manage memory access.
It enables flexible memory access to multiple processors, optimizes the allocation and use of memory resources, enhances the system's flexibility, compatibility and scalability, and supports dynamic memory access for various hardware devices.
Smart Images
Figure CN223897872U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of on-chip memory technology, and in particular to a memory allocator for multi-interface access to on-chip memory in a SOC system. Background Technology
[0002] A System-on-Chip (SoC) is a system-level microprocessor that typically integrates multiple processing devices, including a CPU, DSP, network interface card (NIC), and sound card. Each processing device requires access to the SoC's on-chip memory. To meet these access requirements, the SoC's on-chip memory must be allocated, and access interfaces must be provided for each processing device. Furthermore, dynamic memory allocation has become an industry requirement to ensure the reliability and scalability of SoC operations. Utility Model Content
[0003] Based on the above analysis, the present invention aims to provide a memory allocator for multi-interface access to on-chip memory in a SOC system, thereby solving the problem of on-chip memory allocation in a SOC system.
[0004] The objective of this utility model is mainly achieved through the following technical solutions:
[0005] This utility model discloses a memory allocator for multi-interface access to on-chip memory in a SOC system, comprising: on-chip memory, a first interface group, a second interface, and a multiplexer group;
[0006] The on-chip memory is divided into N banks; each bank is further subdivided into 4 SRAM blocks; the size of the SRAM block is the smallest unit of the memory region;
[0007] The first interface group includes N interfaces, and the multiplexer group includes N 2-to-1 multiplexers;
[0008] The first multiplexing interface of each 2-to-1 multiplexer in the multiplexer group is connected to one interface of the first group of interfaces; the second multiplexing interface of each 2-to-1 multiplexer in the multiplexer group is connected to the second interface; the common interface of the N 2-to-1 multiplexers in the multiplexer group is connected to the N banks of the on-chip memory respectively.
[0009] Furthermore, each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the first multiplexed interface and the common interface, and disconnects the connection path between the second multiplexed interface and the common interface; each interface in the first interface group is connected to a bank of on-chip memory through the first multiplexed interface and the common interface of the 2-to-1 multiplexer connected to it.
[0010] Furthermore, each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the second multiplexing interface and the common interface, and disconnects the connection path between the first multiplexing interface and the common interface; the second interface is connected to all banks of on-chip memory through the second multiplexing interface and the common interface of the 2-to-1 multiplexer connected to it.
[0011] Furthermore, the number N of interfaces in the first interface group is not less than the number of processors accessing memory.
[0012] Furthermore, each interface of the first interface group is connected to a bus and connected to a processor that accesses memory via the bus;
[0013] The processors connected to each interface in the first interface group include: ARM, GPU, network card, sound card and PPU; each processor accessing memory is connected to one interface in the first interface group.
[0014] Furthermore, the processor connected to the second interface for accessing memory is a DSP.
[0015] Furthermore, it also includes an interface matrix;
[0016] The interface matrix includes a third interface group, a fourth interface group, and a multi-way connection mechanism;
[0017] Both the third interface group and the fourth interface group include N interfaces;
[0018] The multiplex connection mechanism is located between the third interface group and the fourth interface group, and is used to provide connection paths between the corresponding interfaces of the N interfaces in the two groups of the third interface group and the fourth interface group.
[0019] The N interfaces of the third interface group are respectively connected to the N interfaces of the first interface group; the fourth interface group is connected to the processor accessing memory; according to the address of the processor accessing memory, the multiplexing mechanism provides the corresponding connection path, so that the interface of the fourth interface group is connected to the interface of the third interface group, and then connected to the on-chip memory at the corresponding address through the interface of the first interface group and the two-to-one multiplexer in the multiplexer group.
[0020] Furthermore, the multi-way connection mechanism is a switch matrix; the switch array in the switch matrix consists of a series of switches including relays, transistors or electronic switches, and the switches in the switch array are controlled to establish or disconnect a set connection, and establish a corresponding connection path between the interfaces of the third interface group and the fourth interface group.
[0021] Furthermore, after the switch matrix provides a connection path between the interfaces of the fourth interface group and the third interface group,
[0022] Each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the first multiplexed interface and the common interface, and disconnects the connection path between the second multiplexed interface and the common interface; each interface of the fourth interface group is connected to the interface of the third interface group through the connection path provided by the switch matrix, and then establishes the connection relationship between each interface of the fourth interface group and the corresponding bank of the on-chip memory through the connection between the third interface group and the first interface group, the connection between the first interface group and the multiplexer group, and the connection between the multiplexer group and the on-chip memory.
[0023] Furthermore, each interface of the fourth interface group is connected to a bus and connected to a processor that accesses memory via the bus;
[0024] The processors connected to each interface in the first interface group include: ARM, GPU, network card, sound card and PPU; each processor accessing memory is connected to one interface in the first interface group.
[0025] The beneficial effects of this utility model are as follows:
[0026] This utility model discloses a memory allocator for multi-interface access to on-chip memory in a SOC system. Through the design of multiplexer groups and interface groups, it can flexibly manage access to on-chip memory by multiple processors, optimize the allocation and use of memory resources, and support dynamic memory access of various hardware devices including ARM, network card, sound card, GPU, PPU (Physics Processing Unit) and DSP, thereby enhancing the system's flexibility, compatibility and scalability. Attached Figure Description
[0027] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0028] Figure 1 This is a schematic diagram of the connection of a memory allocator for multi-interface access to on-chip memory in a SOC system in this embodiment;
[0029] Figure 2 This is a schematic diagram showing the connection of another memory allocator for multi-interface access to on-chip memory in a SOC system, as described in this embodiment.
[0030] Reference numerals: 1. First interface group, 2. Second interface, 3. Multiplexer group, 4. On-chip memory, 5. Interface matrix. Detailed Implementation
[0031] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.
[0032] A specific embodiment of this utility model discloses a memory allocator for multi-interface access to on-chip memory in a SOC system, such as... Figure 1 As shown, it includes: on-chip memory, a first interface group, a second interface, and a multiplexer group;
[0033] The on-chip memory is divided into N banks; each bank is further subdivided into 4 SRAM blocks; the size of the SRAM block is the smallest unit of the memory region;
[0034] The first interface group includes N interfaces, and the multiplexer group includes N 2-to-1 multiplexers;
[0035] The first multiplexing interface of each 2-to-1 multiplexer in the multiplexer group is connected to one interface of the first group of interfaces; the second multiplexing interface of each 2-to-1 multiplexer in the multiplexer group is connected to the second interface; the common interface of the N 2-to-1 multiplexers in the multiplexer group is connected to the N banks of the on-chip memory respectively.
[0036] Specifically, when the input of the selection control terminal of the two-to-one multiplexer is low, the first multiplexing interface and the common interface form a connection path; when the input of the selection control terminal is high, the second multiplexing interface and the common interface form a connection path.
[0037] When there is no memory access request for the second interface, the input of the selection control terminal of each 2-to-1 multiplexer in the multiplexer group is low; each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the first multiplexed interface and the common interface, and disconnects the connection path between the second multiplexed interface and the common interface; each interface in the first interface group is connected to a bank of on-chip memory through the first multiplexed interface and the common interface of the 2-to-1 multiplexer connected to it.
[0038] When the second interface has a memory access request, the input of the selection control terminal of each 2-to-1 multiplexer in the multiplexer group is high; each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the second multiplexed interface and the common interface, and disconnects the connection path between the first multiplexed interface and the common interface; the second interface is connected to all banks of the on-chip memory through the second multiplexed interface and the common interface of the 2-to-1 multiplexer connected to it.
[0039] Specifically, the number N of interfaces in the first interface group is not less than the number of processors accessing memory.
[0040] Specifically, each interface of the first interface group is connected to a bus and connected to a processor that accesses memory via the bus;
[0041] The processors connected to each interface in the first interface group include: ARM, GPU, network card, sound card, and PPU (Physics Processing Unit); each processor accessing memory is connected to one interface in the first interface group.
[0042] Specifically, the processor connected to the second interface for accessing memory is a DSP;
[0043] In this embodiment, an interface and memory allocation scheme are provided for the processor accessing the on-chip memory. In particular, the DSP is given priority in memory access. When the DSP accesses memory, other processors' access to memory is disconnected, so that the DSP can access the entire on-chip memory and realize the storage and retrieval of algorithm operation results with large memory usage.
[0044] In another preferred embodiment, such as Figure 2 As shown, the memory allocator also includes an interface matrix;
[0045] The interface matrix includes a third interface group, a fourth interface group, and a multi-way connection mechanism;
[0046] Both the third interface group and the fourth interface group include N interfaces;
[0047] The multiplexing mechanism is located between the third interface group and the fourth interface group, providing connection paths between the corresponding interfaces of the N interfaces in the two groups. The N interfaces of the third interface group are respectively connected to the N interfaces of the first interface group. The fourth interface group is connected to the processor accessing memory. According to the address of the processor accessing memory, the multiplexing mechanism provides corresponding connection paths, so that the interfaces of the fourth interface group are connected to the interfaces of the third interface group, and then connected to the on-chip memory at the corresponding address through the interfaces of the first interface group and the two-to-one multiplexer in the multiplexer group.
[0048] Specifically, the multi-way connection mechanism is a switch matrix; the switch array in the switch matrix consists of a series of switches including relays, transistors or electronic switches, and the switches in the switch array are controlled to establish or disconnect a set connection, and a corresponding connection is established between the interfaces of the third interface group and the fourth interface group.
[0049] In this embodiment, the switch matrix can be an existing switch matrix with the number of input and output interfaces meeting the interface connection requirements.
[0050] After the switch matrix provides a connection path between the interfaces of the fourth interface group and the third interface group...
[0051] When there is no memory access request for the second interface, the input of the selection control terminal of each 2-to-1 multiplexer in the multiplexer group is low; each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the first multiplexed interface and the common interface, and disconnects the connection path between the second multiplexed interface and the common interface; each interface of the fourth interface group is connected to the interface of the third interface group through the connection path provided by the switch matrix, and through the connection between the third interface group and the first interface group, the connection between the first interface group and the multiplexer group, and the connection between the multiplexer group and the on-chip memory, the connection relationship between each interface of the fourth interface group and the corresponding bank of the on-chip memory is established.
[0052] Specifically, each interface of the fourth interface group is connected to a bus and connected to a processor that accesses memory via the bus;
[0053] The processors connected to each interface in the first interface group include: ARM, GPU, network card, sound card and PPU; each processor accessing memory is connected to one interface in the first interface group.
[0054] By dynamically adjusting the connection relationships of the connection paths of the switch matrix, dynamic allocation of each processor is achieved. By combining the dynamic adjustment of the switch matrix and the dynamic control of the multiplexer group selection control terminal, data exchange between the processors and DSPs on the bus through on-chip memory cache can be realized.
[0055] In summary, the memory allocator for multi-interface access to on-chip memory in this embodiment, through the design of multiplexer groups and interface groups, can flexibly manage access to on-chip memory by multiple processors, optimizing the allocation and use of memory resources. The solution supports dynamic memory access from various hardware devices, including ARM, network cards, sound cards, GPUs, PPUs, and DSPs, enhancing the system's flexibility, compatibility, and scalability.
[0056] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model should be included within the protection scope of the present utility model.
Claims
1. A memory allocator for multi-interface access to on-chip memory in a SOC system, characterized in that, include: On-chip memory, first interface group, second interface and multiplexer group; The on-chip memory is divided into N banks; Each bank is further subdivided into 4 SRAM blocks; The size of an SRAM block is the smallest unit of a memory region; The first interface group includes N interfaces, and the multiplexer group includes N 2-to-1 multiplexers; The first multiplexing interface of each 2-to-1 multiplexer in the multiplexer group is connected to one interface of the first group of interfaces; the second multiplexing interface of each 2-to-1 multiplexer in the multiplexer group is connected to the second interface; the common interface of the N 2-to-1 multiplexers in the multiplexer group is connected to the N banks of the on-chip memory respectively.
2. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 1, characterized in that, Each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the first multiplexed interface and the common interface, and disconnects the connection path between the second multiplexed interface and the common interface; each interface in the first interface group is connected to a bank of on-chip memory through the first multiplexed interface and the common interface of the 2-to-1 multiplexer connected to it.
3. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 1, characterized in that, Each 2-to-1 multiplexer in the multiplexer group establishes a connection path between the second multiplexed interface and the common interface, and disconnects the connection path between the first multiplexed interface and the common interface; the second interface is connected to all banks of on-chip memory through the second multiplexed interface and the common interface of the 2-to-1 multiplexer connected to it.
4. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 3, characterized in that, The number of interfaces N in the first interface group is not less than the number of processors accessing memory.
5. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 4, characterized in that, Each interface in the first interface group is connected to a bus and is connected to a processor that accesses memory via the bus. The processors connected to each interface in the first interface group include: ARM, GPU, network card, sound card, and PPU; Each processor accessing memory connects to one interface in the first interface group.
6. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 4, characterized in that, The processor connected to the second interface for accessing memory is a DSP.
7. The memory allocator for multi-interface access to on-chip memory in a SOC system according to any one of claims 1-6, characterized in that, It also includes the interface matrix; The interface matrix includes a third interface group, a fourth interface group, and a multi-way connection mechanism; Both the third interface group and the fourth interface group include N interfaces; The multiplex connection mechanism is located between the third interface group and the fourth interface group, and is used to provide connection paths between the corresponding interfaces of the N interfaces in the two groups of the third interface group and the fourth interface group. The N interfaces of the third interface group are respectively connected to the N interfaces of the first interface group; the fourth interface group is connected to the processor that accesses memory; Based on the address of the memory accessed by the processor, the multiplexing mechanism provides a corresponding connection path, so that the interface of the fourth interface group is connected to the interface of the third interface group, and then connected to the on-chip memory at the corresponding address through the interface of the first interface group and the two-to-one multiplexer in the multiplexer group.
8. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 7, characterized in that, The multi-way connection mechanism is a switch matrix; the switch array in the switch matrix consists of a series of switches including relays, transistors or electronic switches, and the switches in the switch array are controlled to establish or disconnect a set connection, and establish a corresponding connection path between the interfaces of the third interface group and the fourth interface group.
9. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 8, characterized in that, After the switch matrix provides a connection path between the interfaces of the fourth interface group and the third interface group... Each interface of the fourth interface group is connected to the interface of the third interface group through the connection path provided by the switch matrix. Furthermore, the connection relationship between each interface of the fourth interface group and the corresponding bank of the on-chip memory is established through the connection between the third interface group and the first interface group, the connection between the first interface group and the multiplexer group, and the connection between the multiplexer group and the on-chip memory.
10. The memory allocator for multi-interface access to on-chip memory in a SOC system according to claim 9, characterized in that, Each interface of the fourth interface group is connected to a bus and is connected to the processor that accesses memory via the bus.