Differential signal processing circuit, differential operational amplifier and operational amplifier chip
By using a high-voltage cross-coupled switching circuit and a level transfer circuit, and controlling it with a low-voltage domain clock signal, the problem of processing high-voltage DC common-mode signals and small-signal differential signals in integrated circuits is solved. This achieves high-precision signal conversion and isolation, and is suitable for differential signal processing circuits and operational amplifier chips.
Patent Information
- Application Number
- CN202520310512.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2035-02-25
AI Technical Summary
Existing technologies struggle to effectively process differential signals between high-voltage DC common-mode signals and small signals in integrated circuits, especially in high-side current sensing. Traditional methods such as magnetic coupling and optical coupling suffer from integration difficulties or low accuracy.
A high-voltage cross-coupled switching circuit and a level transfer circuit are adopted. The high-voltage DC common-mode signal is isolated by the low-voltage domain clock signal control, and the high-voltage differential signal is transferred to the low-voltage differential signal output. The sampling and isolation are performed using capacitors.
With a small integration area and high precision, effective isolation and conversion of high-voltage differential signals are achieved, improving the accuracy and precision of signal measurement and avoiding the shortcomings of traditional methods.
Smart Images
Figure CN223899197U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuits, and in particular to a differential signal processing circuit, a differential operational amplifier, and an operational amplifier chip. Background Technology
[0002] In many measurement scenarios, the signal of interest is very small, possibly in the range of tens of microvolts, and superimposed on a larger DC common-mode (CM) signal, potentially in the range of several volts or even hundreds of volts. Processing such a large DC common-mode signal while accurately measuring such a small signal presents a significant challenge for differential signal processing circuits. For example, in high-side current sensing, such as... Figure 1 As shown, the battery load current is monitored by inserting a small sensing resistor Rsense in series with the battery. Therefore, the current can be determined by the DC voltage drop Vsense across the resistor. To minimize power consumption, the sensing resistor Rsense is typically very small, and consequently, the DC voltage drop Vsense is also small, typically between tens of microvolts and hundreds of millivolts. In this case, the DC voltage drop Vsense is accompanied by a large DC common-mode voltage, which can typically be as high as 30V, far exceeding the supply voltage of normal CMOS circuits.
[0003] In existing technologies, magnetic coupling and optical coupling are commonly used to address the DC common-mode voltage problem. Magnetic coupling consists of input and output modulators, a transformer, and a sense amplifier. In this case, the modulator is implemented as a chopper, a switch whose polarity is reversed and driven by a fixed-frequency digital clock signal. The input chopper converts the DC differential voltage into a square wave, and the output chopper converts the amplified square wave back to DC. In this way, the high-voltage differential signal is first modulated to a high frequency by the input chopper, and thus can be coupled to the input of the sense differential operational amplifier through the transformer. However, the DC common-mode voltage is not modulated and therefore does not couple to the sense differential operational amplifier. Furthermore, the bias and 1 / f noise of the sense differential operational amplifier are up-modulated by the output chopper and can therefore be filtered out. However, a major drawback of this method is that the transformer is difficult to integrate onto the chip. Although micro-transformers can be integrated in some processes, they often occupy a large amount of chip area.
[0004] Optical coupling involves optically isolating DC common-mode voltage, for example, using an optical isolator. While there are many types of optical isolators, the most common type consists only of an LED and a photodiode. The LED is connected to the input signal and converts it into a light signal, which is then picked up by the photodiode and a sense amplifier and converted back to an electrical signal. In this way, the input DC common-mode voltage is completely isolated from the differential operational amplifier. However, a major drawback of this method is its lack of accuracy. The signal transfer function between the LED and the photodiode depends on several parameters, such as the voltage-to-light transfer function of the LED, the intensity of the light picked up by the photodiode, and the light-to-voltage transfer function of the photodiode. These parameters are difficult to control and accurately reproduce in mass production. Therefore, the accuracy of measurements, especially the total gain of the system, is not well defined. Furthermore, the linearity of the signal is typically low, requiring an additional feedback circuit. Utility Model Content
[0005] Therefore, it is necessary to provide a differential signal processing circuit and operational amplifier chip to address the above-mentioned technical problems, so as to isolate high-voltage DC common-mode signals and convert high-voltage differential signals into low-voltage differential signal outputs.
[0006] In a first aspect, embodiments of this application propose a differential signal processing circuit, comprising:
[0007] A high-voltage cross-coupled switch circuit has two first input terminals and two first output terminals. The high-voltage cross-coupled switch circuit is configured to receive high-voltage differential signals through the two first input terminals respectively, and select and output high-voltage differential signals through the two first output terminals according to a low-voltage domain clock signal.
[0008] The level shifting circuit has two second input terminals and two second output terminals, and is configured to receive the high-voltage differential signal through the two second input terminals, and shift the high-voltage differential signal into a low-voltage differential signal according to the low-voltage domain clock signal, and output it through the two second output terminals.
[0009] In some embodiments, the high-voltage cross-coupled switching circuit includes: a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit. One end of the first switching unit is connected to a first input terminal, and the other end is connected to a first output terminal. One end of the second switching unit is connected to a first input terminal, and the other end is connected to another first output terminal. One end of the third switching unit is connected to another first input terminal, and the other end is connected to the first output terminal. One end of the fourth switching unit is connected to another first input terminal, and the other end is connected to another first output terminal.
[0010] In some embodiments, the high-voltage cross-coupled switching circuit further includes: a first clock signal control circuit and a second clock signal control circuit, wherein the first clock signal control circuit receives the low-voltage domain clock signal and controls the first switching unit and the fourth switching unit, and the second clock signal control circuit receives the low-voltage domain clock signal and controls the second switching unit and the third switching unit.
[0011] In some embodiments, the first switching unit includes PMOS transistor MP3 and NMOS transistor MN5, the second switching unit includes PMOS transistor MP1 and NMOS transistor MN1, the third switching unit includes PMOS transistor MP2 and NMOS transistor MN2, and the fourth switching unit includes PMOS transistor MP4 and NMOS transistor MN6.
[0012] The gate of the PMOS transistor MP3 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN5, and its drain is connected to the first output terminal; the gate of the NMOS transistor MN5 is connected to the first clock signal control circuit, and its source is connected to the first high-voltage differential signal.
[0013] The gate of the NMOS transistor MN1 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal, and its drain is connected to the source of the PMOS transistor MP1; the gate of the PMOS transistor MP1 is connected to the second clock signal control circuit, and its drain is connected to the first output terminal.
[0014] The gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal, and its drain is connected to the source of the PMOS transistor MP2; the gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and its drain is connected to another of the first output terminals.
[0015] The gate of the PMOS transistor MP4 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN6, and its drain is connected to another of the first output terminals; the gate of the NMOS transistor MN6 is connected to the second clock signal control circuit, and its source is connected to the first high-voltage differential signal.
[0016] In some embodiments, the first clock signal control circuit includes NMOS transistors MN7 and MN8, PMOS transistors MP7 and MP8, and capacitors Cp3, Cp4, Cp7, and Cp8; the second clock signal control circuit includes NMOS transistors MN3 and MN4, PMOS transistors MP5 and MP6, and capacitors Cp1, Cp2, Cp5, and Cp6.
[0017] The source of NMOS transistor MN7 is connected to the first high-voltage differential signal, its gate is connected to the drain of NMOS transistor MN8, its drain is connected to one end of capacitor Cp3 and the gate of NMOS transistor MN8, and the other end of capacitor Cp3 is connected to the second low-voltage domain clock signal; the source of NMOS transistor MN8 is connected to the first high-voltage differential signal, its drain is connected to one end of capacitor Cp4, and the other end of capacitor Cp4 is connected to the first low-voltage domain clock signal;
[0018] The source of PMOS transistor MP7 is connected to the first high-voltage differential signal, its gate is connected to the drain of PMOS transistor MP8, its drain is connected to one end of capacitor Cp7 and the gate of PMOS transistor MP8, and the other end of capacitor Cp7 is connected to the fourth low-voltage domain clock signal; the source of PMOS transistor MP8 is connected to the first high-voltage differential signal, its drain is connected to one end of capacitor Cp8, and the other end of capacitor Cp8 is connected to the third low-voltage domain clock signal.
[0019] The source of NMOS transistor MN3 is connected to the second high-voltage differential signal, its gate is connected to the drain of NMOS transistor MN4, its drain is connected to one end of capacitor Cp1 and the gate of NMOS transistor MN4, and the other end of capacitor Cp1 is connected to the first low-voltage domain clock signal; the source of NMOS transistor MN4 is connected to the second high-voltage differential signal, its drain is connected to one end of capacitor Cp2, and the other end of capacitor Cp2 is connected to the second low-voltage domain clock signal;
[0020] The source of PMOS transistor MP5 is connected to the second high-voltage differential signal, and its gate is connected to the drain of PMOS transistor MP6. The drain of MP5 is connected to one end of capacitor Cp5 and the gate of PMOS transistor MP6. The other end of capacitor Cp5 is connected to the third low-voltage domain clock signal. The source of PMOS transistor MP6 is connected to the second high-voltage differential signal, and its drain is connected to one end of capacitor Cp6. The other end of capacitor Cp6 is connected to the fourth low-voltage domain clock signal.
[0021] In some embodiments, the third low-voltage domain clock signal is a delayed signal of the first low-voltage domain clock signal; and the fourth low-voltage domain clock signal is a delayed signal of the second low-voltage domain clock signal.
[0022] In some embodiments, the first high-voltage differential signal is greater than, equal to, or less than the second high-voltage differential signal.
[0023] In some embodiments, the level shifting circuit includes a fifth switching unit, a sixth switching unit, a seventh switching unit, an eighth switching unit, a ninth switching unit, a tenth switching unit, capacitors C1, C2, C3, and C4.
[0024] One end of the fifth switching unit is connected to one end of the capacitor C3, and the other end is connected to the common ground. The other end of the capacitor C3 is connected to a second output terminal.
[0025] One end of the sixth switching unit is connected to one end of the capacitor C3, and the other end is connected to the reference voltage signal;
[0026] One end of the seventh switching unit is connected to one end of the capacitor C4, and the other end is connected to the reference voltage signal. The other end of the capacitor C4 is connected to another second output terminal.
[0027] One end of the eighth switching unit is connected to one end of the capacitor C4, and the other end is connected to the common ground;
[0028] One end of the ninth switch unit is connected to a second output terminal, and the other end is connected to one end of the tenth switch unit. The other end of the tenth switch unit is connected to another second output terminal.
[0029] One end of capacitor C1 is connected to a second input terminal, and the other end is connected to a second output terminal; one end of capacitor C2 is connected to another second input terminal, and the other end is connected to another second output terminal.
[0030] Secondly, embodiments of this application provide a differential operational amplifier, including the differential signal processing circuit described in the first aspect.
[0031] Thirdly, embodiments of this application provide an operational amplifier chip, including the differential operational amplifier as described in the second aspect.
[0032] The aforementioned differential signal processing circuit, differential operational amplifier, and operational amplifier chip possess the following technical advantages: The high-voltage cross-coupled switching circuit receives high-voltage differential signals through its two first input terminals, and selects and outputs high-voltage differential signals through its two first output terminals based on the low-voltage domain clock signal. The level shifting circuit receives the high-voltage differential signals through its two second input terminals, and, based on the low-voltage domain clock signal, converts the high-voltage differential signals into low-voltage differential signals, which are then output through the two second output terminals. This technical solution, with a relatively small integration area and high precision, can isolate high-voltage DC common-mode signals and convert high-voltage differential signals into low-voltage differential signals for output. Attached Figure Description
[0033] Figure 1A schematic diagram of the differential signal processing circuit in one embodiment provided in this application;
[0034] Figure 2 A schematic diagram of the specific structure of the differential signal processing circuit in one embodiment provided in this application;
[0035] Figure 3 An equivalent circuit diagram of a differential signal processing circuit in one embodiment provided in this application;
[0036] Figure 4 A schematic diagram of a high-voltage cross-coupled switch circuit in one embodiment provided in this application. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.
[0038] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.
[0039] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.
[0040] Figure 1 This is a schematic diagram of the differential signal processing circuit in one embodiment provided in this application. Figure 1 As shown, the differential signal processing circuit includes: a high-voltage cross-coupled switch circuit 10, having two first input terminals and two first output terminals, configured to receive high-voltage differential signals through the two first input terminals respectively, and select and output high-voltage differential signals through the two first output terminals according to a low-voltage domain clock signal; and a level shifting circuit 20, having two second input terminals and two second output terminals, configured to receive the high-voltage differential signals through the two second input terminals, and shift the high-voltage differential signals into low-voltage differential signals according to the low-voltage domain clock signal and output them through the two second output terminals.
[0041] The high-voltage differential signal refers to a differential signal above 70V, but this embodiment does not limit its specific voltage range.
[0042] In this embodiment, the high-voltage cross-coupled switch circuit 10 receives high-voltage differential signals through the two first input terminals, and selects and outputs high-voltage differential signals through the two first output terminals according to the low-voltage domain clock signal. The level shifting circuit 20 receives the high-voltage differential signals through the two second input terminals, and shifts the high-voltage differential signals into low-voltage differential signals according to the low-voltage domain clock signal, which are then output through the two second output terminals. This technical solution can isolate high-voltage DC common-mode signals and shift high-voltage differential signals into low-voltage differential signals for output, while maintaining a small integration area and high precision.
[0043] Figure 2 This is a schematic diagram of the differential signal processing circuit in one embodiment provided in this application. Figure 2 As shown, the high-voltage cross-coupled switching circuit 10 includes: a first switching unit S1, a second switching unit S2, a third switching unit S3, and a fourth switching unit S4. One end of the first switching unit S1 is connected to a first input terminal, and the other end is connected to a first output terminal. One end of the second switching unit S2 is connected to a first input terminal, and the other end is connected to another first output terminal. One end of the third switching unit S3 is connected to another first input terminal, and the other end is connected to the first output terminal. One end of the fourth switching unit S4 is connected to another first input terminal, and the other end is connected to another first output terminal.
[0044] Among them, a first input terminal is connected to a first high-voltage differential signal V. H The other first input terminal is connected to the second high-voltage differential signal V. L .
[0045] In some embodiments, the level shifting circuit 20 includes a fifth switching unit S5, a sixth switching unit S6, a seventh switching unit S7, an eighth switching unit S8, a ninth switching unit S9, a tenth switching unit S10, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4.
[0046] One end of the fifth switching unit S5 is connected to one end of the capacitor C3, and the other end is connected to a common ground. The other end of the capacitor C3 is connected to a second output terminal. One end of the sixth switching unit S6 is connected to one end of the capacitor C3, and the other end is connected to a reference voltage signal V. REF One end of the seventh switching unit S7 is connected to one end of the capacitor C4, and the other end is connected to the reference voltage signal V. REFThe other end of capacitor C4 is connected to another second output terminal; one end of the eighth switch unit S8 is connected to one end of capacitor C4, and the other end is connected to a common ground; one end of the ninth switch unit S9 is connected to one second output terminal, and the other end is connected to one end of the tenth switch unit S10, the other end of the tenth switch unit S10 is connected to another second output terminal; one end of capacitor C1 is connected to one second input terminal, and the other end is connected to one second output terminal; one end of capacitor C2 is connected to another second input terminal, and the other end is connected to another second output terminal.
[0047] Among them, the second output terminal outputs the first low-voltage differential signal V. ON The other second output terminal outputs a second low-voltage differential signal V. OP .
[0048] In the above embodiments, capacitors C1, C2, C3, and C4 have the same capacitance.
[0049] In the above embodiments, the first switching unit S1, the fourth switching unit S4, the fifth switching unit S5, the seventh switching unit S7, the ninth switching unit S9, and the tenth switching unit S10 are powered by the first low-voltage domain clock signal. Controlled by the second low-voltage domain clock signal, the second switching unit S2, the third switching unit S3, the sixth switching unit S6, and the eighth switching unit S8 are controlled by the second low-voltage domain clock signal. Control. First low-voltage domain clock signal Second low-voltage domain clock signal It is a two-phase non-overlapping clock signal.
[0050] In the above embodiments, a capacitor is used to sample the high-voltage differential signal, and the high-voltage DC common-mode signal is completely isolated by the capacitor.
[0051] When the first high-voltage differential signal V H Higher than the second high-voltage differential signal V L At that time, the equivalent circuit of the differential signal processing circuit is as follows: Figure 3 As shown. When the first low-voltage domain clock signal High level, second low-voltage domain clock signal When the signal is low, capacitors C1 and C3 are connected, and one end of capacitor C1 is connected to the first high-voltage differential signal V. H The other end is connected to the midpoint signal V. CM One end of capacitor C3 is connected to the common ground, and the other end is connected to the midpoint signal V. CM Second low-voltage domain clock signal High level, first low-voltage domain clock signal When the signal is low, capacitors C1 and C3 are connected, and one end of capacitor C1 is connected to the second high-voltage differential signal V.L The other end is connected to the midpoint signal V. CM One end of capacitor C3 is connected to the reference voltage signal V. REF The other end is connected to the midpoint signal V. CM .
[0052] The capacitances of capacitors C1, C2, C3, and C4 are all, for example, C. Based on the above equivalent circuit, and using the definition of charge conservation, we obtain:
[0053] (V CM -V H )C+(V CM -0)C=(V xp -V L )C+(V xp -V REF C
[0054] Among them, V xp This represents an output voltage of the level shifting circuit.
[0055] Simplifying, we get:
[0056]
[0057] Similarly, we can conclude that:
[0058]
[0059] Among them, V xn This represents another output voltage of the level shifting circuit.
[0060] In conclusion:
[0061] V xp -V xn =V REF -(V H -V L )
[0062] Reference voltage signal V REF For example, if the voltage is 3.3V, the signal V can be obtained from the above formula. xp and, V xn The voltage is shifted to signal V CM Up, and when V H -V L When the range is 0 to 6.6V, V xp -V xn The voltage range is ±3.3V, which meets the quantization range of adc±3.3V, thus isolating the influence of DC common-mode voltage.
[0063] When the first high-voltage differential signal VH is lower than the second high-voltage differential signal VL, the first low-voltage domain clock signal in the level shifting circuit will be... Second low-voltage domain clock signal Reverse polarity, similarly based on the law of conservation of charge:
[0064]
[0065] The reference voltage signal VREF is, for example, 3.3V, when V L =0~6.6V, V H When V = 0, if L =0V, then V xp -V xn =3.3V, if V L =6.6V, then V xp -V xn = -3.3V.
[0066] Figure 4 This is a schematic diagram of the high-voltage cross-coupled switch circuit 10 in one embodiment provided in this application. Figure 4 As shown, the high-voltage cross-coupled switching circuit 10 further includes: a first clock signal control circuit 101 and a second clock signal control circuit 102. The first clock signal control circuit 101 receives the low-voltage domain clock signal and controls the first switching unit S1 and the fourth switching unit S4. The second clock signal control circuit 102 receives the low-voltage domain clock signal and controls the second switching unit S2 and the third switching unit S3.
[0067] In some embodiments, the first switching unit S1 includes a PMOS transistor MP3 and an NMOS transistor MN5, the second switching unit S2 includes a PMOS transistor MP1 and an NMOS transistor MN1, the third switching unit S3 includes a PMOS transistor MP2 and an NMOS transistor MN2, and the fourth switching unit S4 includes a PMOS transistor MP4 and an NMOS transistor MN6.
[0068] The gate of the PMOS transistor MP3 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN5, and its drain is connected to the first output terminal V. OUT1 The gate of the NMOS transistor MN5 is connected to the first clock signal control circuit, and its source is connected to the first high-voltage differential signal V. H The gate of the NMOS transistor MN1 is connected to the second clock signal control circuit, and its source is connected to the second high-voltage differential signal V. L Its drain is connected to the source of the PMOS transistor MP1; the gate of the PMOS transistor MP1 is connected to the second clock signal control circuit, and its drain is connected to the first output terminal V.OUT1 The gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and its source is connected to the second high-voltage differential signal V. L Its drain is connected to the source of the PMOS transistor MP2; the gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and its drain is connected to another of the first output terminals V. OUT2 The gate of the PMOS transistor MP4 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN6, and its drain is connected to another first output terminal V. OUT2 The gate of the NMOS transistor MN6 is connected to the second clock signal control circuit, and its source is connected to the first high-voltage differential signal V. H .
[0069] In some embodiments, the first clock signal control circuit 101 includes NMOS transistors MN7 and MN8, PMOS transistors MP7 and MP8, and capacitors Cp3, Cp4, Cp7, and Cp8; the second clock signal control circuit includes NMOS transistors MN3 and MN4, PMOS transistors MP5 and MP6, and capacitors Cp1, Cp2, Cp5, and Cp6.
[0070] The source of the NMOS transistor MN7 is connected to the first high-voltage differential signal V. H Its gate is connected to the drain of the NMOS transistor MN8, and its drain is connected to one end of the capacitor Cp3 and the gate of the NMOS transistor MN8. The other end of the capacitor Cp3 is connected to the second low-voltage domain clock signal. The source of the NMOS transistor MN8 is connected to the first high-voltage differential signal V. H Its drain is connected to one end of the capacitor Cp4, and the other end of the capacitor Cp4 is connected to the first low-voltage domain clock signal.
[0071] The source of the PMOS transistor MP7 is connected to the first high-voltage differential signal V. H Its gate is connected to the drain of the PMOS transistor MP8, and its drain is connected to one end of the capacitor Cp7 and the gate of the PMOS transistor MP8. The other end of the capacitor Cp7 is connected to the fourth low-voltage domain clock signal. The source of the PMOS transistor MP8 is connected to the first high-voltage differential signal V. H Its drain is connected to one end of the capacitor Cp8, and the other end of the capacitor Cp8 is connected to the third low-voltage domain clock signal.
[0072] The source of the NMOS transistor MN3 is connected to the second high-voltage differential signal V.L Its gate is connected to the drain of the NMOS transistor MN4, and its drain is connected to one end of the capacitor Cp1 and the gate of the NMOS transistor MN4. The other end of the capacitor Cp1 is connected to the first low-voltage domain clock signal. The source of the NMOS transistor MN4 is connected to the second high-voltage differential signal V. L Its drain is connected to one end of the capacitor Cp2, and the other end of the capacitor Cp2 is connected to the second low-voltage domain clock signal.
[0073] The source of the PMOS transistor MP5 is connected to the second high-voltage differential signal V. L Its gate is connected to the drain of the PMOS transistor MP6, and its drain is connected to one end of the capacitor Cp5 and the gate of the PMOS transistor MP6. The other end of the capacitor Cp5 is connected to the third low-voltage domain clock signal. The source of the PMOS transistor MP6 is connected to the second high-voltage differential signal V. L Its drain is connected to one end of the capacitor Cp6, and the other end of the capacitor Cp6 is connected to the fourth low-voltage domain clock signal.
[0074] To avoid using LDMOS, the above embodiments employ a charge pump-based switching structure, similar to the boost section in a boost switch.
[0075] The gate-source voltage of a high-voltage device in the on-state is determined by the charge distribution ratio between the coupling capacitor (Cpi) and the MOS parasitic capacitor. Taking NMOS transistor MN3 as an example, the clock signal in the first low-voltage domain of the capacitor base station node... The pulse signal will cause charge redistribution.
[0076] It should be noted that the third low-voltage domain clock signal The first low-voltage domain clock signal The delayed signal, the fourth low-voltage domain clock signal The second low-voltage domain clock signal The delayed signal.
[0077] By setting the delay signal, NMOS transistors MN1, MN2, MN5, and MN6 can be allowed to pass through first, preventing the Vgs voltage of PMOS transistors MP1, MP2, MP3, and MP4 from exceeding 5V.
[0078] In this embodiment, by configuring PMOS transistors MP1, MP2, MP3, and MP4, the first high-voltage differential signal V can be avoided. HIt must be greater than the second high-voltage differential signal V. L Due to the limitations of the conditions, the first high-voltage differential signal V H It can be greater than, equal to, or less than the second high-voltage differential signal V. L .
[0079] The control process of the high-voltage cross-coupled switch is described below using the first switching unit S1 and the first clock signal control circuit as an example.
[0080] First low-voltage domain clock signal Second low-voltage domain clock signal It is a two-phase non-overlapping clock signal, the first low-voltage domain clock signal. When the voltage level is high, NMOS transistor MN7 is turned on, NMOS transistor MN5 is turned on, and the third low-voltage domain clock signal is activated. The first low-voltage domain clock signal The opposite signal is low, so PMOS transistor MP7 is turned on and PMOS transistor MP3 is turned on. At this time, the first switching unit S1 is turned on.
[0081] The control process for other switching units and clock signal control circuits follows the same control principle, so it will not be described in detail here.
[0082] This application also proposes a differential operational amplifier, including the differential signal processing circuit described in the above embodiments.
[0083] It should be noted that the working principle and beneficial effects of the differential signal processing circuit have been described in detail in the above embodiments, so they will not be repeated in this embodiment.
[0084] This application also proposes an operational amplifier chip, including the differential operational amplifier as described in the above embodiments.
[0085] It should be noted that the working principle and beneficial effects of the differential signal processing circuit have been described in detail in the above embodiments, so they will not be repeated in this embodiment.
[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0087] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A differential signal processing circuit, characterized in that, include: A high-voltage cross-coupled switch circuit has two first input terminals and two first output terminals. The high-voltage cross-coupled switch circuit is configured to receive high-voltage differential signals through the two first input terminals respectively, and select and output high-voltage differential signals through the two first output terminals according to a low-voltage domain clock signal. The level shifting circuit has two second input terminals and two second output terminals, and is configured to receive the high-voltage differential signal through the two second input terminals, and shift the high-voltage differential signal into a low-voltage differential signal according to the low-voltage domain clock signal, and output it through the two second output terminals.
2. The differential signal processing circuit according to claim 1, characterized in that, The high-voltage cross-coupled switching circuit includes: a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit. One end of the first switching unit is connected to a first input terminal, and the other end is connected to a first output terminal. One end of the second switching unit is connected to a first input terminal, and the other end is connected to another first output terminal. One end of the third switching unit is connected to another first input terminal, and the other end is connected to the first output terminal. One end of the fourth switching unit is connected to another first input terminal, and the other end is connected to another first output terminal.
3. The differential signal processing circuit according to claim 2, characterized in that, The high-voltage cross-coupled switching circuit further includes: a first clock signal control circuit and a second clock signal control circuit. The first clock signal control circuit receives the low-voltage domain clock signal and controls the first switching unit and the fourth switching unit. The second clock signal control circuit receives the low-voltage domain clock signal and controls the second switching unit and the third switching unit.
4. The differential signal processing circuit according to claim 3, characterized in that, The first switching unit includes PMOS transistor MP3 and NMOS transistor MN5; the second switching unit includes PMOS transistor MP1 and NMOS transistor MN1; the third switching unit includes PMOS transistor MP2 and NMOS transistor MN2; and the fourth switching unit includes PMOS transistor MP4 and NMOS transistor MN6. The gate of the PMOS transistor MP3 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN5, and its drain is connected to the first output terminal; the gate of the NMOS transistor MN5 is connected to the first clock signal control circuit, and its source is connected to the first high-voltage differential signal. The gate of the NMOS transistor MN1 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal, and its drain is connected to the source of the PMOS transistor MP1; the gate of the PMOS transistor MP1 is connected to the second clock signal control circuit, and its drain is connected to the first output terminal. The gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal, and its drain is connected to the source of the PMOS transistor MP2; the gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and its drain is connected to another of the first output terminals. The gate of the PMOS transistor MP4 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN6, and its drain is connected to another of the first output terminals; the gate of the NMOS transistor MN6 is connected to the second clock signal control circuit, and its source is connected to the first high-voltage differential signal.
5. The differential signal processing circuit according to claim 4, characterized in that, The first clock signal control circuit includes NMOS transistors MN7 and MN8, PMOS transistors MP7 and MP8, and capacitors Cp3, Cp4, Cp7, and Cp8; the second clock signal control circuit includes NMOS transistors MN3 and MN4, PMOS transistors MP5 and MP6, and capacitors Cp1, Cp2, Cp5, and Cp6. The source of NMOS transistor MN7 is connected to the first high-voltage differential signal, its gate is connected to the drain of NMOS transistor MN8, its drain is connected to one end of capacitor Cp3 and the gate of NMOS transistor MN8, and the other end of capacitor Cp3 is connected to the second low-voltage domain clock signal; the source of NMOS transistor MN8 is connected to the first high-voltage differential signal, its drain is connected to one end of capacitor Cp4, and the other end of capacitor Cp4 is connected to the first low-voltage domain clock signal; The source of PMOS transistor MP7 is connected to the first high-voltage differential signal, its gate is connected to the drain of PMOS transistor MP8, its drain is connected to one end of capacitor Cp7 and the gate of PMOS transistor MP8, and the other end of capacitor Cp7 is connected to the fourth low-voltage domain clock signal; the source of PMOS transistor MP8 is connected to the first high-voltage differential signal, its drain is connected to one end of capacitor Cp8, and the other end of capacitor Cp8 is connected to the third low-voltage domain clock signal. The source of NMOS transistor MN3 is connected to the second high-voltage differential signal, its gate is connected to the drain of NMOS transistor MN4, its drain is connected to one end of capacitor Cp1 and the gate of NMOS transistor MN4, and the other end of capacitor Cp1 is connected to the first low-voltage domain clock signal; the source of NMOS transistor MN4 is connected to the second high-voltage differential signal, its drain is connected to one end of capacitor Cp2, and the other end of capacitor Cp2 is connected to the second low-voltage domain clock signal; The source of PMOS transistor MP5 is connected to the second high-voltage differential signal, and its gate is connected to the drain of PMOS transistor MP6. The drain of MP5 is connected to one end of capacitor Cp5 and the gate of PMOS transistor MP6. The other end of capacitor Cp5 is connected to the third low-voltage domain clock signal. The source of PMOS transistor MP6 is connected to the second high-voltage differential signal, and its drain is connected to one end of capacitor Cp6. The other end of capacitor Cp6 is connected to the fourth low-voltage domain clock signal.
6. The differential signal processing circuit according to claim 5, characterized in that, The third low-voltage domain clock signal is a delayed signal of the first low-voltage domain clock signal; the fourth low-voltage domain clock signal is a delayed signal of the second low-voltage domain clock signal.
7. The differential signal processing circuit according to any one of claims 4-6, characterized in that, The first high-voltage differential signal is greater than, equal to, or less than the second high-voltage differential signal.
8. The differential signal processing circuit according to claim 1, characterized in that, The level shifting circuit includes a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a ninth switch unit, a tenth switch unit, capacitors C1, C2, C3, and C4. One end of the fifth switching unit is connected to one end of the capacitor C3, and the other end is connected to the common ground. The other end of the capacitor C3 is connected to a second output terminal. One end of the sixth switching unit is connected to one end of the capacitor C3, and the other end is connected to the reference voltage signal; One end of the seventh switching unit is connected to one end of the capacitor C4, and the other end is connected to the reference voltage signal. The other end of the capacitor C4 is connected to another second output terminal. One end of the eighth switching unit is connected to one end of the capacitor C4, and the other end is connected to the common ground; One end of the ninth switch unit is connected to a second output terminal, and the other end is connected to one end of the tenth switch unit. The other end of the tenth switch unit is connected to another second output terminal. One end of capacitor C1 is connected to a second input terminal, and the other end is connected to a second output terminal; one end of capacitor C2 is connected to another second input terminal, and the other end is connected to another second output terminal.
9. A differential operational amplifier, characterized in that, Includes the differential signal processing circuit as described in any one of claims 1-8.
10. An operational amplifier chip, characterized in that, Includes the differential operational amplifier as described in claim 9.