Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a substrate and a gate drive circuit and an anode layer which are arranged on the substrate, the gate drive circuit is located in a non-display area and comprises a plurality of first thin film transistors, the anode layer comprises a transmission bus located in the non-display area, the transmission bus and the gate drive circuit are arranged in an overlapped mode, and the first thin film transistors are arranged on the transmission bus. The second thin film transistor is electrically connected with the first thin film transistor; the transmission bus located in the non-display area is prepared through the material of the anode layer, an original metal film layer for preparing the transmission bus is removed, the wiring structure of the non-display area is simplified, meanwhile, the transmission bus and the gate drive circuit are arranged in an overlapped mode, the frame width occupied by the transmission bus in the non-display area is reduced, and the display effect is improved. And the narrow frame design of the product is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a new type of current-driven semiconductor light-emitting device that displays light by controlling the charge carriers in the device and exciting organic materials.

[0003] In current OLED display panels, the transmission bus in the non-display area is usually located on one side of the gate driving circuit, which increases the bezel width of the display panel and contradicts the narrow bezel design of current products. At the same time, the transmission bus is usually made of a second layer of source and drain metal, which makes the structure of the display panel more complex and increases the manufacturing cost of the product. Utility Model Content

[0004] This application provides a display panel and display device to solve the technical problem of the complex structure of existing OLED display panels.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] This application discloses a display panel including a display area and a non-display area located on at least one side of the display area, the display panel comprising:

[0007] Substrate;

[0008] A gate driving circuit is disposed on one side of the substrate and located within the non-display area; the gate driving circuit includes a plurality of first thin-film transistors; and

[0009] An anode layer is disposed on the side of the gate drive circuit away from the substrate.

[0010] The anode layer includes a transmission bus located within the non-display area, the transmission bus at least partially overlapping the gate drive circuit and being electrically connected to the first thin-film transistor.

[0011] In the display panel of this application, the display panel further includes:

[0012] A light-shielding layer is disposed on one side of the substrate, and the light-shielding layer includes a first electrode plate;

[0013] A semiconductor layer is disposed on the side of the light-shielding layer away from the substrate.

[0014] A gate layer is disposed on the side of the semiconductor layer away from the substrate.

[0015] A source-drain layer is disposed on the side of the gate layer away from the substrate, and the source-drain layer includes a second electrode plate disposed opposite to the first electrode plate;

[0016] The anode layer is disposed on the side of the source / drain layer away from the substrate, and the anode layer includes a third electrode plate;

[0017] The semiconductor layer or the gate layer further includes a fourth electrode plate, which is disposed between the first electrode plate and the second electrode plate. The first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate are all located within the display area and constitute the storage capacitor of the display panel.

[0018] In the display panel of this application, the display panel further includes a conductive element disposed between the third electrode plate and the fourth electrode plate, one end of the conductive element being electrically connected to the third electrode plate and the other end of the conductive element being electrically connected to the fourth electrode plate;

[0019] The conductive component includes a first conductive part and a second conductive part connected to each other. The first conductive part is disposed near the third electrode plate, and the second conductive part is disposed near the fourth electrode plate. The material of the first conductive part is the same as the material of the anode layer, and the material of the second conductive part is the same as the material of the source and drain electrode layers.

[0020] In the display panel of this application, the distance between the interface of the first conductive portion and the second conductive portion and the substrate is less than or equal to the distance between the surface of the source / drain layer on the side away from the substrate and the substrate.

[0021] In the display panel of this application, the display panel further includes a pixel driving circuit disposed in the display area, the pixel driving circuit including a second thin film transistor;

[0022] The semiconductor layer includes a first active portion of the second thin-film transistor and a second active portion of the first thin-film transistor, wherein the mobility of the first active portion is less than or equal to the mobility of the second active portion.

[0023] In the display panel of this application, the display panel further includes:

[0024] A buffer layer is disposed between the semiconductor layer and the light-shielding layer;

[0025] The protective layer includes a first portion located in the display area and a second portion located in the non-display area. The first portion is disposed on the surface of the first active portion away from the substrate, and the second portion is disposed between the second active portion and the buffer layer.

[0026] The mobility of the first active part is less than that of the second active part.

[0027] In the display panel of this application, the semiconductor layer includes the fourth electrode plate, and the fourth electrode plate is in contact with the surface of the buffer layer away from the substrate.

[0028] Alternatively, the protective layer may further include a third portion disposed between the buffer layer and the fourth electrode plate, wherein the gate layer includes the fourth electrode plate and the fourth electrode plate is disposed on the side of the third portion away from the substrate.

[0029] In the display panel of this application, the semiconductor layer further includes a third active portion disposed between the buffer layers in the third portion, and the mobility of the third active portion is the same as that of the first active portion;

[0030] One side of the third active part is in contact with the buffer layer, and the other side of the third active part is in contact with the third portion.

[0031] In the display panel of this application, the display panel further includes:

[0032] A passivation layer is disposed between the source / drain layer and the anode layer, and the passivation layer covers the source / drain layer;

[0033] A first planarization layer is disposed on the side of the passivation layer away from the substrate, and a portion of the anode layer is in contact with the surface of the first planarization layer away from the substrate.

[0034] The first flat layer has a first opening, and the third electrode plate is disposed in the first opening.

[0035] This application also proposes a display device, which includes the above-described display panel.

[0036] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0039] Figure 1 A simplified structural diagram of the display panel provided in the embodiments of this application;

[0040] Figure 2 for Figure 1 The first structural diagram of the mid-section MM;

[0041] Figure 3 for Figure 1 A magnified view of region NN within the Central African display area;

[0042] Figure 4 for Figure 1 The second structural diagram of the mid-section MM;

[0043] Figure 5 for Figure 1 The third structural diagram of the mid-section MM;

[0044] Figure 6 for Figure 1 The fourth structural diagram of the mid-section MM;

[0045] Figure 7 for Figure 2 A magnified view of the storage capacitor. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0047] Please see Figures 1 to 7 This application proposes a display panel 100, which includes a display area AA and a non-display area NA located on at least one side of the display area AA. The display panel 100 includes a substrate 10, a gate driving circuit GC disposed on one side of the substrate 10, and an anode layer 401 disposed on the side of the gate driving circuit GC away from the substrate 10.

[0048] In this embodiment, the gate driving circuit GC is located within the non-display area NA, and the gate driving circuit GC includes a plurality of first thin-film transistors T2; the anode layer 401 includes a transmission bus BS located within the non-display area NA, the transmission bus BS at least partially overlaps with the gate driving circuit GC, and is electrically connected to the first thin-film transistors T2.

[0049] This application utilizes the material of the anode layer 401 to fabricate the transmission bus BS located in the non-display area NA, eliminating the need for the original metal film layer used to fabricate the transmission bus BS and simplifying the wiring structure of the non-display area NA. Secondly, the transmission bus BS overlaps with the gate drive circuit GC, reducing the bezel width occupied by the transmission bus BS in the non-display area NA and achieving a narrow bezel design for the product.

[0050] The technical solution of this application will now be described in conjunction with specific embodiments.

[0051] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains a plurality of sub-pixels PX that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the sub-pixels PX within the display area AA in displaying information.

[0052] Please see Figure 1 A bonding terminal PD can be provided on the lower side of the display area AA. The bonding terminal PD can be connected to an external circuit and transmit the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal PD can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0053] Please see Figures 2 to 6 The display panel 100 may include a substrate 10, an array layer 20 disposed on the substrate 10, a pixel layer 30 disposed on the array layer 20, a light-emitting functional layer 40, and an encapsulation layer 50.

[0054] In this embodiment, the substrate 10 can be made of materials such as glass, quartz, or polyimide; for example, when the display panel 100 is a flexible panel, the substrate 10 can be made of flexible materials such as polyimide, or can be composed of a laminate of flexible materials and inorganic materials; when the display panel 100 is a rigid panel, the substrate 10 can be made of rigid materials such as glass or quartz.

[0055] Please see Figures 2 to 6 The array layer 20 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., depending on the position of the gate and the semiconductor layer AS. There are no specific restrictions.

[0056] In this embodiment, at least one second thin-film transistor T1 is disposed in the display area AA, and at least one first thin-film transistor T2 is disposed in the non-display area NA; at the same time, a pixel driving circuit and a storage capacitor Cst are disposed in the display area AA, the pixel driving circuit including the second thin-film transistor T1, and a gate driving circuit GC is disposed in the non-display area NA, the gate driving circuit GC including the first thin-film transistor T2.

[0057] It should be noted that, in order to simplify the manufacturing process, the second thin-film transistor T1 and the first thin-film transistor T2 in the display area AA and the non-display area NA can be fabricated simultaneously.

[0058] For example, please see Figures 2 to 6 The thin-film transistor shown can be a top-gate thin-film transistor. The array layer 20 can include a light-shielding layer LS disposed on the substrate 10, a buffer layer 201 disposed on the light-shielding layer LS, a semiconductor layer AS disposed on the buffer layer 201, a gate insulating layer 202 disposed on the semiconductor layer AS, a gate layer GE disposed on the gate insulating layer 202, an inter-insulating layer 203 disposed on the gate layer GE, a source-drain layer SD disposed on the inter-insulating layer 203, a passivation layer 204 disposed on the source-drain layer SD, a first planarization layer 205 disposed on the passivation layer 204, and a second planarization layer 206 disposed on the first planarization layer 205.

[0059] It should be noted that the number of source and drain layers can be set according to the wiring space requirements. For example, the source and drain layers in this application can be one layer. At the same time, the number of gate layers GE can be set according to the wiring space and capacitance requirements. For example, the gate layer GE in this application is one layer.

[0060] It should be noted that the buffer layer 201, the gate insulating layer 202, the interlayer insulating layer 203 and the passivation layer 204 can all be inorganic materials composed of elements such as nitrogen, silicon, oxygen and aluminum, such as single or multiple stacked inorganic film layers composed of silicon nitride, silicon oxide and aluminum oxide.

[0061] It should be noted that the planarization layer in this application is set to ensure the flatness of the film layer. The number of planarization layers is set according to the flatness requirements of the film layer. For example, the planarization layer in this application can be two layers.

[0062] Please see Figures 2 to 6 The pixel layer 30 may include a first pixel definition layer 310 and a second pixel definition layer 320. The first pixel definition layer 310 is disposed on the side of the second planarization layer 206 away from the substrate 10, and the second pixel definition layer 320 is disposed on the surface of the first pixel definition layer 310 away from the substrate 10.

[0063] It should be noted that, since the light-emitting layer 402 of this application is prepared using inkjet printing technology, in order to reduce the precision of inkjet printing, the first pixel definition layer 310 of this application may include a plurality of horizontally and vertically intersecting first masking strips. The horizontally and vertically intersecting first masking strips enclose a plurality of pixel openings corresponding to sub-pixels. The second pixel definition layer 320 includes a plurality of horizontally or vertically intersecting second masking strips. The plurality of sub-pixels between two adjacent second masking strips have the same color, so that in the inkjet printing process, multiple sub-pixels between two adjacent second masking strips can be printed simultaneously along the arrangement direction of the second masking strips, thereby reducing the precision of inkjet printing and improving process efficiency.

[0064] It should be noted that the first pixel definition layer 310 and the second pixel definition layer 320 of this application can be formed in one process, that is, the film layers of the first pixel definition layer 310 and the second pixel definition layer 320 are formed simultaneously, and the first pixel definition layer 310 and the second pixel definition layer 320 are patterned in the same photomask so that the first pixel definition layer 310 forms a plurality of first occlusion strips, and the second pixel definition layer 320 forms a plurality of second occlusion strips. For example, this application may include a plurality of first occlusion strips extending along the second direction and arranged along the first direction, and a plurality of second occlusion strips extending along the first direction and arranged along the second direction.

[0065] In this embodiment, since the second masking strip mainly serves to isolate sub-pixels of different colors, the thickness of the second masking strip in this application can be greater than the thickness of the first masking strip.

[0066] It should be noted that the display panel 100 also includes a support layer (not shown) integrally disposed with the pixel layer 30. The support layer is disposed on the surface of the second pixel definition layer 320 away from the first pixel definition layer 310, and the support layer and the pixel layer 30 can be formed in the same photomask process. The support layer can be used to support the photomask.

[0067] It should be noted that the materials of pixel layer 30 and support layer can be organic positive photoresist.

[0068] Please see Figures 2 to 6 The light-emitting functional layer 40 may include an anode layer 401 disposed on the first planarization layer 205, a light-emitting layer 402 disposed on the anode layer 401, and a cathode layer 403 disposed on the light-emitting layer 402. The anode layer 401 includes a plurality of anodes AN corresponding one-to-one with the pixel openings, and the light-emitting layer 402 may include a plurality of light-emitting pixels corresponding one-to-one with the plurality of anodes AN.

[0069] It should be noted that the pixel opening of this application can penetrate the second flattening layer 206, the first pixel definition layer 310 and the second pixel definition layer 320, or / and the pixel opening of this application can penetrate the second flattening layer 206 and the first pixel definition layer 310.

[0070] Please see Figures 2 to 6 The encapsulation layer 50 covers the pixel layer 30 and continuously covers multiple pixel openings and multiple light-emitting pixels; the encapsulation layer 50 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are stacked sequentially.

[0071] In this embodiment, the display panel may further include a color filter layer (not shown) disposed on the encapsulation layer 50 and a cover plate layer (not shown) disposed on the color filter layer. The color filter layer includes a plurality of color resists and light-shielding units disposed on both sides of the color resists, with one color resist corresponding to one light-emitting pixel. The cover plate layer is disposed on the side of the color filter layer away from the substrate 10. The cover plate layer may be a glass cover or formed directly on the color filter layer.

[0072] The following is a summary of this application. Figures 2 to 6 The structure of the middle array layer 20 is described in detail.

[0073] Please see Figure 2 The material of the light-shielding layer LS may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the light-shielding layer LS may be a stacked structure composed of a MoTi layer and a Cu layer.

[0074] In this embodiment, since the device effect of the transistor drifts under the action of light, the light-shielding layer LS can be provided between the transistor and the substrate 10 to block the active part in the transistor; and since a light-shielding structure is provided in the non-display area NA, external light cannot enter the area where the gate drive circuit GC is located, so the light-shielding layer LS can be located in the display area AA, and there is no need to provide a light-shielding layer LS in the non-display area NA.

[0075] Please see Figure 2 When the light-shielding layer LS is patterned, the light-shielding layer LS can be formed into a light-shielding part LS1 corresponding to the second thin film transistor T1 and the first plate C1 of the storage capacitor Cst.

[0076] Please see Figure 2 The buffer layer 201 covers the light-shielding layer LS. The material of the buffer layer 201 can be silicon nitride or silicon oxide, or a stacked structure of the two.

[0077] Please see Figure 2The semiconductor layer AS is disposed on the side of the buffer layer 201 away from the substrate 10. The material of the semiconductor layer AS can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, or other metal oxides; for example Figure 2 The semiconductor layer AS in the process can be made of IGZO.

[0078] In this embodiment, the semiconductor layer AS includes a first active portion AS1 of the second thin-film transistor T1 and a second active portion AS2 of the first thin-film transistor T2. The materials of the first active portion AS1 and the second active portion AS2 can be the same, that is, the mobility of the first active portion AS1 can be equal to the mobility of the second active portion AS2.

[0079] In this embodiment, the surfaces of the first active portion AS1 and the second active portion AS2 on the side away from the gate layer GE are both in contact with the buffer layer 201.

[0080] In this embodiment, the semiconductor layer AS may further include a fourth electrode C4 corresponding to the first electrode C1. The fourth electrode C4 is in contact with the surface of the buffer layer 201 away from the light-shielding layer LS, and the fourth electrode C4 is disposed opposite to the first electrode C1. The second electrode C2 is the capacitor electrode of the storage capacitor Cst.

[0081] Please see Figure 2 The gate insulating layer 202 includes a first sub-part 202a and a second sub-part 202b. The first sub-part 202a is disposed on the side of the first active part AS1 away from the substrate 10, and the second sub-part 202b is disposed on the side of the second active part AS2 away from the substrate 10. The gate insulating layer 202 is used to isolate the semiconductor layer AS from the upper conductive layer.

[0082] Please see Figure 2 The gate layer GE includes a first gate GE1 of the second thin film transistor T1 and a second gate GE2 of the first thin film transistor T2. The first gate GE1 is disposed on the side of the first sub-part 202a away from the substrate 10, and the second gate GE2 is disposed on the side of the second sub-part 202b away from the substrate 10.

[0083] In this embodiment, the material of the gate layer GE may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the first electrode layer 120 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0084] In this embodiment, the thickness of the gate layer GE can be from 100nm to 200nm.

[0085] Please see Figure 2 The inter-insulating layer 203 is disposed on the side of the gate layer GE away from the substrate 10. The inter-insulating layer 203 is laid out in its entirety, and the inter-insulating layer 203 covers the gate insulating layer and is in contact with the buffer layer 201.

[0086] Please see Figure 2 The source-drain layer SD includes a first source T1S and a first drain T1D of the second thin film transistor T1, and a second source T2S and a second drain T2D of the first thin film transistor T2. The first source T1S is connected to one end of the first active part AS1 through the first via HL1, the first drain T1D is connected to the other end of the first active part AS1 through the second via HL2, the second source T2S is connected to one end of the second active part AS2 through the third via HL3, and the second drain T2D is connected to the other end of the second active part AS2 through the fourth via HL4.

[0087] In this embodiment, the first source T1S is also electrically connected to the light-shielding part LS1 through the fifth via HL5, so that the light-shielding part LS1 is multiplexed as the bottom gate of the second thin film transistor T1, thereby improving the conduction rate of the second thin film transistor T1.

[0088] In this embodiment, the source-drain layer SD further includes a second electrode C2 of the storage capacitor Cst. The second electrode C2 is connected to the first electrode C1 through a sixth via HL6, and the second electrode C2 is disposed opposite to the fourth electrode C4.

[0089] In this embodiment, the material of the source / drain layer SD may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the source / drain layer SD may be a stacked structure composed of a MoTi layer and a Cu layer, the thickness of the MoTi layer may be 10 nm to 30 nm, and the thickness of the Cu layer may be 400 nm to 600 nm.

[0090] Please see Figure 2 The passivation layer 204 is disposed on the side of the source-drain layer SD away from the substrate 10. The passivation layer 204 is laid out in its entirety, and the passivation layer 204 covers the source-drain layer SD and is in contact with the interlayer insulating layer 203.

[0091] Please see Figure 2 The first planarization layer 205 is disposed on the side of the passivation layer 204 away from the substrate 10. The first planarization layer 205 covers a portion of the passivation layer 204, and a first opening 205a is formed on the first planarization layer 205.

[0092] In this embodiment, since the source / drain layer SD is relatively thick, there is a large step difference between the areas where the source / drain layer SD is provided and the areas where the source / drain layer SD is not provided. Since the passivation layer 204 is an inorganic material with poor leveling properties, the flatness of the surface of the passivation layer 204 away from the substrate 10 is poor. The material of the first leveling layer 205 can be an organic material with good leveling properties, such as polyimide, which improves the flatness of the film surface.

[0093] Please see Figure 2 The anode layer 401 includes an anode AN located in the display area AA and a transmission bus BS located in the non-display area NA. The anode AN is connected to the first source T1S through the seventh via HL7. The transmission bus BS can be connected to the second gate GE2, the second source T2S, or the second drain T2D in the first thin film transistor T2 through the eighth via HL8.

[0094] Please see Figure 3 The transmission bus BS may include multiple signal transmission lines, such as high potential lines, low potential lines, data lines, clock signal lines, etc. The multiple signal lines are overlapped with the gate drive circuit GC, and the multiple signal lines are electrically connected to the corresponding first thin film transistors to transmit the corresponding signals to the first thin film transistors.

[0095] This application reduces the bezel space occupied by the transmission bus BS on the side of the first thin-film transistor T2 away from the substrate 10, thus achieving a narrow bezel design. Simultaneously, the transmission bus BS is made of the material of the anode layer 401, eliminating the need for the original metal film layer used to fabricate the transmission bus BS. Furthermore, the transmission bus BS and the anode AN in the display area AA are fabricated in the same process, without adding an additional photomask process. This simplifies the wiring structure of the non-display area NA and also simplifies the manufacturing process of the display panel 100. Finally, since the anode layer 401 in this application is typically made of a material with a certain reflectivity, using the anode layer 401 material to fabricate the transmission bus BS in the non-display area NA can reflect ambient light entering the non-display area NA, preventing ambient light from affecting the device performance of the first thin-film transistor T2 in the non-display area NA.

[0096] Please see Figure 3 The display panel also includes multiple scan lines, and the gate driving circuit GC is connected to the scan lines to transmit the control signal output by the gate driving circuit GC to the pixel driving circuit in the display area AA.

[0097] It should be noted that a gate driving circuit GC can also correspond to multiple scan lines to transmit corresponding control signals to different transistors in the pixel driving circuit in order to control the conduction and cutoff of the transistors.

[0098] In this embodiment, the anode layer 401 may further include a third electrode plate C3 of the storage capacitor Cst. The third electrode plate C3 may be located within the first opening 205a, that is, part of the material of the anode layer 401 is in contact with the surface of the first planarization layer 205 away from the substrate 10. The third electrode plate C3 may pass through the ninth via HL9 and be connected to the fourth electrode plate C4. The third electrode plate C3 is disposed opposite to the second electrode plate C2.

[0099] In this embodiment, the depth of the first opening 205a can be less than or equal to the thickness of the first planarization layer 205. For example, in this application, the depth of the first opening 205a is equal to the thickness of the first planarization layer 205. The third electrode C3 contacts the passivation layer 204 in the first opening 205a. The arrangement of the first opening 205a reduces the distance between the second electrode C2 and the third electrode C3, thereby increasing the capacitance of the storage capacitor Cst.

[0100] In this embodiment, the material of the anode layer 401 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0101] Please see Figure 2 The bonding terminal PD may include a first terminal PD1 and a second terminal PD2. The first terminal PD1 may be fabricated in the patterning process of the source-drain layer SD, and the second terminal PD2 may be fabricated in the patterning process of the anode layer 401. The second terminal PD2 is electrically connected to the first terminal PD1 through the tenth via HL10.

[0102] exist Figure 2 In this application, the materials of the light-shielding layer LS, semiconductor layer AS, source-drain layer SD, and anode layer 401 in the display panel 100 are used to prepare four layers of capacitor plates. There is no need to set an additional conductive layer to prepare the capacitor plates, which simplifies the structure of the storage capacitor Cst and reduces the manufacturing cost of the display panel 100. At the same time, the parallel capacitor formed by the four layers of capacitor plates increases the capacitance of the storage capacitor Cst, which effectively compensates the threshold voltage of the driving transistor and improves the display screen of the display panel 100.

[0103] Please see Figure 2 The second planarization layer 206 is disposed on the side of the anode layer 401 away from the substrate 10. The material of the second planarization layer 206 can be the same as the material of the first planarization layer 205. For example, both the second planarization layer 206 and the first planarization layer 205 can be materials with good leveling properties, such as polyimide.

[0104] In this embodiment, the material of the second planarization layer 206 may be different from that of the first planarization layer 205. For example, the photosensitivity of the second planarization layer 206 may be greater than that of the first planarization layer 205, that is, the photosensitivity of the second planarization layer 206 is stronger. When exposing the second planarization layer 206, the exposure process time can be reduced and the efficiency of the exposure process can be improved.

[0105] Please see Figure 4 , Figure 4 For this application Figure 1 The second structural diagram of the mid-section MM. Figure 4 medium structure and Figure 2 The structures in the two are the same or similar, but the differences are:

[0106] Please see Figure 4 The material of the first active part AS1 is different from the material of the second active part AS2, and the mobility of the first active part AS1 is less than the mobility of the second active part AS2.

[0107] In this embodiment, the trend of narrow bezel design for the display panel 100 reduces the bezel size of the display panel 100. This requires increasing the driving current capability of the gate driving circuit GC to reduce the size of the driving circuit. This application increases the mobility of the second active part AS2 in the first thin film transistor T2, thereby increasing the driving current capability of the transistor in the gate driving circuit GC and reducing the bezel size of the non-display area NA. This achieves a narrow bezel design while ensuring the driving stability of the non-display area NA.

[0108] In this embodiment, the material of the first active part AS1 can be IGZO, and the material of the second active part AS2 can be IGZTO, IZO (InZnO), or InIZO.

[0109] In this embodiment, in order to differentiate the mobility of the first active part AS1 and the second active part AS2, the first active part AS1 and the second active part AS2 need to be fabricated in two photomask processes. In order to prevent the influence of the later process on the active part in the earlier process, this application can provide a protective layer 207 between the two processes.

[0110] Please see Figure 4 The protective layer 207 may include a first portion 207a located in the display area AA and a second portion 207b located in the non-display area. The first portion 207a is disposed on the surface of the first active part AS1 away from the light-shielding layer LS, and the second portion 207b is disposed between the second active part AS2 and the buffer layer 201.

[0111] In this embodiment, the protective layer 207 can be laid as a whole layer, or it can be only provided as an attachment. Figure 4 In the structure shown; meanwhile, the material of the protective layer 207 can be the same as the material of the gate insulating layer 202.

[0112] This application improves the driving current capability of the transistor in the gate drive circuit GC by making the mobility of the second active part AS2 greater than that of the first active part AS1, thereby reducing the bezel size of the non-display area NA and achieving a narrow bezel design. At the same time, the protective layer 207 can protect the first active part AS1 and prevent the process of the second active part AS2 from affecting the first active part AS1.

[0113] Please see Figure 5 , Figure 5 For this application Figure 1 The third structural diagram of the mid-section MM. Figure 5 medium structure and Figure 4 The structures in the two are the same or similar, but the differences are:

[0114] Please see Figure 5The gate layer GE includes the fourth electrode C4, and the fourth electrode C4 is disposed on the side of the third portion 207c away from the light-shielding layer LS.

[0115] Meanwhile, the protective layer 207 may also include a third portion 207c disposed between the buffer layer 201 and the fourth electrode plate C4, and the gate insulating layer 202 includes a third sub-part 202c disposed between the third portion 207c and the fourth electrode plate C4, that is, the buffer layer 201, the third portion 207c and the third sub-part 202c are spaced apart between the first electrode plate C1 and the fourth electrode plate C4.

[0116] and Figure 2 and Figure 4 compared to, Figure 5 The fourth electrode C4 is fabricated in the patterning process of the gate layer GE; at the same time, the third part 207c, the third sub-part 202c and the fourth electrode C4 can all be formed in one process, which simplifies the structure of the storage capacitor Cst, reduces the number of photomasks and lowers the process cost.

[0117] Please see Figure 6 , Figure 6 For this application Figure 1 The fourth structural diagram of the mid-section MM. Figure 6 medium structure and Figure 5 The structures in the two are the same or similar, but the differences are:

[0118] Please see Figure 6 The semiconductor layer AS further includes a third active portion AS3 disposed between the buffer layer 201 in the third portion 207c. One side of the third active portion AS3 is in contact with the buffer layer 201, and the other side of the third active portion AS3 is in contact with the third portion 207c. That is, the buffer layer 201, the third active portion AS3, the third portion 207c and the third sub-part 202c are disposed between the first electrode C1 and the fourth electrode C4.

[0119] In this embodiment, due to the obstruction of the fourth electrode plate C4, the third active part AS3 is not subjected to conductor treatment, that is, the mobility of the third active part AS3 is the same as the mobility of the first active part AS1.

[0120] Please see Figure 7 The display panel 100 further includes a conductive element CT disposed between the third electrode plate C3 and the fourth electrode plate C4. The conductive element CT is located in the ninth through hole HL9. One end of the conductive element CT is electrically connected to the third electrode plate C3, and the other end of the conductive element CT is electrically connected to the fourth electrode plate C4.

[0121] In this embodiment, the conductive component CT includes a first conductive part CT1 and a second conductive part CT2 connected to each other. The first conductive part CT1 is disposed near the third electrode plate C3, and the second conductive part CT2 is disposed near the fourth electrode plate C4. The material of the first conductive part CT1 is the same as the material of the anode layer 401, and the material of the second conductive part CT2 is the same as the material of the source and drain electrode layers SD.

[0122] In this embodiment, since the impedance of the material of the anode layer 401 is greater than that of the source-drain layer SD, this application can first form the second conductive part CT2 of the conductive element CT in the patterning process of the source-drain layer SD, and then form the first conductive part CT1 of the conductive element CT in the process of the anode layer 401, so as to reduce the impedance of the conductive element CT, thereby reducing the connection impedance of the third electrode C3 and the fourth electrode C4.

[0123] In this embodiment, since the second conductive portion CT2 is formed in the patterning process of the source-drain layer SD, the surface of the second conductive portion CT2 away from the substrate 10 cannot exceed the surface of the source-drain layer SD away from the substrate 10. That is, the distance between the interface of the first conductive portion CT1 and the second conductive portion CT2 and the substrate 10 is less than or equal to the distance between the surface of the source-drain layer SD away from the substrate 10 and the substrate 10.

[0124] It should be noted that, Figures 4 to 6 The structure of the CT with the central conductive component is also the same as Figure 7 The structure of the conductive component CT is the same.

[0125] This application also discloses a display device including the aforementioned display panel. It should be noted that the display device of this application can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0126] This application provides a display panel and a display device. The display panel includes a substrate and a gate driving circuit and an anode layer disposed on the substrate. The gate driving circuit is located in a non-display area and includes a plurality of first thin-film transistors. The anode layer includes a transmission bus located in the non-display area. The transmission bus overlaps with the gate driving circuit and is electrically connected to the first thin-film transistors. This application utilizes the material of the anode layer to prepare the transmission bus in the non-display area, eliminating the metal film layer used in the original preparation of the transmission bus and simplifying the wiring structure in the non-display area. At the same time, the overlap between the transmission bus and the gate driving circuit reduces the bezel width occupied by the transmission bus in the non-display area, achieving a narrow bezel design for the product.

[0127] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0128] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0129] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0130] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area. Substrate; A gate driving circuit is disposed on one side of the substrate and located within the non-display area; the gate driving circuit includes a plurality of first thin-film transistors; and An anode layer is disposed on the side of the gate drive circuit away from the substrate. The anode layer includes a transmission bus located within the non-display area, the transmission bus at least partially overlapping the gate drive circuit and being electrically connected to the first thin-film transistor.

2. The display panel according to claim 1, characterized in that, The display panel also includes: A light-shielding layer is disposed on one side of the substrate, and the light-shielding layer includes a first electrode plate; A semiconductor layer is disposed on the side of the light-shielding layer away from the substrate. A gate layer is disposed on the side of the semiconductor layer away from the substrate. A source-drain layer is disposed on the side of the gate layer away from the substrate, and the source-drain layer includes a second electrode plate disposed opposite to the first electrode plate; The anode layer is disposed on the side of the source / drain layer away from the substrate, and the anode layer includes a third electrode plate; The semiconductor layer or the gate layer further includes a fourth electrode plate, which is disposed between the first electrode plate and the second electrode plate. The first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate are all located within the display area and constitute the storage capacitor of the display panel.

3. The display panel according to claim 2, characterized in that, The display panel further includes a conductive element disposed between the third electrode plate and the fourth electrode plate, one end of the conductive element being electrically connected to the third electrode plate and the other end of the conductive element being electrically connected to the fourth electrode plate; The conductive component includes a first conductive part and a second conductive part connected to each other. The first conductive part is disposed near the third electrode plate, and the second conductive part is disposed near the fourth electrode plate. The material of the first conductive part is the same as the material of the anode layer, and the material of the second conductive part is the same as the material of the source and drain electrode layers.

4. The display panel according to claim 3, characterized in that, The distance between the interface between the first conductive portion and the second conductive portion and the substrate is less than or equal to the distance between the surface of the source / drain layer on the side away from the substrate and the substrate.

5. The display panel according to any one of claims 2 to 4, characterized in that, The display panel further includes a pixel driving circuit disposed within the display area, the pixel driving circuit including a second thin-film transistor; The semiconductor layer includes a first active portion of the second thin-film transistor and a second active portion of the first thin-film transistor, wherein the mobility of the first active portion is less than or equal to the mobility of the second active portion.

6. The display panel according to claim 4, characterized in that, The display panel also includes: A buffer layer is disposed between the semiconductor layer and the light-shielding layer; The protective layer includes a first portion located in the display area and a second portion located in the non-display area. The first portion is disposed on the surface of the first active portion away from the substrate, and the second portion is disposed between the second active portion and the buffer layer. The mobility of the first active part is less than that of the second active part.

7. The display panel according to claim 6, characterized in that, The semiconductor layer includes the fourth electrode plate, and the fourth electrode plate is in contact with the surface of the buffer layer on the side away from the substrate. Alternatively, the protective layer may further include a third portion disposed between the buffer layer and the fourth electrode plate, wherein the gate layer includes the fourth electrode plate and the fourth electrode plate is disposed on the side of the third portion away from the substrate.

8. The display panel according to claim 7, characterized in that, The semiconductor layer further includes a third active portion disposed between the third portion and the buffer layer, wherein the mobility of the third active portion is the same as that of the first active portion; One side of the third active part is in contact with the buffer layer, and the other side of the third active part is in contact with the third portion.

9. The display panel according to any one of claims 2 to 4, 6 to 8, characterized in that, The display panel also includes: A passivation layer is disposed between the source / drain layer and the anode layer, and the passivation layer covers the source / drain layer; A first planarization layer is disposed on the side of the passivation layer away from the substrate, and a portion of the anode layer is in contact with the surface of the first planarization layer away from the substrate. The first flat layer has a first opening, and the third electrode plate is disposed in the first opening.

10. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 9.

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