Display substrate and display device

Abstract

The utility model provides a display substrate and a display device. The display substrate comprises a substrate body and a plurality of signal lines which are arranged on the substrate body and extend in the first direction. The plurality of signal lines comprise light-emitting control lines; the ratio of the overlapping area between the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the signal lines except the light-emitting control line included in the multiple signal lines on the substrate to the area of the orthographic projection of the light-emitting control line on the substrate is larger than or equal to 0 and smaller than or equal to 0.8. According to the utility model, stray capacitance of the light-emitting control line can be reduced, and power consumption is reduced.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] With the continuous development of smartphones, phone functions are becoming increasingly powerful, and the computing power of mobile phone chips and the brightness and clarity of screen displays are also increasing. Consequently, the power consumption of the entire device is also increasing. Without significant breakthroughs in battery technology, power consumption will be the primary issue restricting the battery life of mobile devices. Therefore, reducing power consumption has become an urgent problem to be solved to ensure the battery life of mobile devices. Summary of the Invention

[0003] The main objective of this invention is to provide a display substrate and a display device that solves the problem in the prior art that the parasitic capacitance of the light-emitting control lines cannot be reduced, which is not conducive to reducing power consumption.

[0004] In one aspect, this utility model provides a display substrate, including a substrate and a plurality of signal lines extending along a first direction disposed on the substrate; the plurality of signal lines include light-emitting control lines;

[0005] The ratio between the overlapping area of ​​the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the signal lines (excluding the light-emitting control line) on the substrate, and the area of ​​the orthographic projection of the light-emitting control line on the substrate, is greater than or equal to 0 and less than or equal to 0.8.

[0006] Optionally, the plurality of signal lines includes a first signal line;

[0007] The orthogonal projection of the light-emitting control line on the substrate covers the orthogonal projection of the first signal line on the substrate;

[0008] The line width of the first signal line is smaller than the line width of the light emission control line.

[0009] Optionally, the plurality of signal lines includes a first signal line;

[0010] The orthographic projection of the light-emitting control line on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

[0011] Optionally, the light emission control line includes a first light emission control signal line portion and a second light emission control signal line portion; both the first light emission control signal line portion and the second light emission control signal line portion extend along a first direction;

[0012] The orthographic projection of the first light-emitting control signal line on the substrate does not overlap with the orthographic projection of the first signal line on the substrate, while the orthographic projection of the second light-emitting control signal line on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

[0013] Optionally, the plurality of signal lines includes a first signal line; the first signal line includes a plurality of first signal line portions and connecting line portions; the first signal line portions and the connecting line portions are arranged alternately along a first direction; adjacent first signal line portions and connecting line portions are electrically connected; the first signal line portions extend along the first direction.

[0014] The orthographic projection of the light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the first signal line portion on the substrate; the orthographic projection of the connecting line portion on the substrate does not overlap with the orthographic projection of the first signal line portion on the substrate.

[0015] Optionally, the length of the light-emitting control line is greater than the sum of the lengths of the plurality of first signal lines.

[0016] Optionally, the ratio of the sum of the lengths of the plurality of first signal lines to the length of the light-emitting control line is greater than 0 and less than or equal to 0.8.

[0017] Optionally, the display substrate described in at least one embodiment of the present invention further includes a multi-row, multi-column pixel circuit disposed on the substrate; the first signal line portion is electrically connected to the active pattern of at least one transistor included in the pixel circuit through the connecting line portion;

[0018] The first signal line portion and the connecting line portion are disposed in different layers.

[0019] Optionally, the plurality of signal lines includes a first signal line;

[0020] The orthographic projection of the light-emitting control line on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

[0021] Optionally, the plurality of signal lines includes a first reset control line;

[0022] The orthographic projection of the first reset control line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate.

[0023] Optionally, the light emission control line is disposed on the same layer as the first reset control line; the first reset control line is disposed on a different layer from the first signal line.

[0024] Optionally, the plurality of signal lines further includes a second signal line, a third signal line, and a second reset control line; the second signal line, the third signal line, and the second reset control line all extend along a first direction;

[0025] The orthographic projection of the second reset control line on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate;

[0026] The second reset control line, the second signal line, and the third signal line are arranged in different layers.

[0027] Optionally, the light emission control line, the first reset control line, and the second reset control line are all formed on the first metal layer, the third signal line is formed on the second metal layer, and the first signal line and the second signal line are both formed on the third metal layer.

[0028] The orthographic projection of the third signal line on the substrate does not overlap with the orthographic projection of the conductive pattern formed on the first metal layer on the substrate.

[0029] Optionally, the plurality of signal lines include a first signal line, a second signal line, a third signal line, a first reset control line, a second reset control line, a first scan line, a second scan line, a data line, a power supply voltage line, and a first voltage line; the display substrate further includes pixel circuitry disposed on the substrate;

[0030] The pixel circuit includes a light-emitting element, a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a third initialization circuit.

[0031] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0032] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage line and the second node respectively, and is used to control the connection or disconnection between the power supply voltage line and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0033] The second light-emitting control circuit is electrically connected to the light-emitting control line, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element is electrically connected to the first voltage line;

[0034] The data writing circuit is electrically connected to the second scan line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second scan signal provided by the second scan line;

[0035] The compensation control circuit is electrically connected to the first scan line, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first scan signal provided by the first scan line.

[0036] The first initialization circuit is electrically connected to the first reset control line, the first signal line and the second node respectively, and is used to write the voltage signal provided by the first signal line into the second node under the control of the first reset control signal provided by the first reset control line;

[0037] The second initialization circuit is electrically connected to the first reset control line, the second signal line, and the first electrode of the light-emitting element, respectively, and is used to write the voltage signal provided by the second signal line into the first electrode of the light-emitting element under the control of the first reset control signal;

[0038] The third initialization circuit is electrically connected to the second reset control line, the third signal line, and the third node, respectively, and is used to write the voltage signal provided by the third signal line into the third node under the control of the second reset control signal provided by the second reset control line.

[0039] Optionally, the light emission control line, the first signal line, the second signal line, the third signal line, the first reset control line, the second reset control line, the first scan line, and the second scan line extend along a first direction;

[0040] The data line, the power supply voltage line, and the first voltage line extend along a second direction; the first direction intersects the second direction.

[0041] In a second aspect, embodiments of the present invention provide a display device including the aforementioned display substrate.

[0042] The display substrate and display device described in this embodiment can reduce the parasitic capacitance of the light-emitting control lines and reduce power consumption. Attached Figure Description

[0043] Figure 1 This is a layout diagram of the display substrate described in at least one embodiment of the present invention;

[0044] Figure 2 yes Figure 1 Layout diagram of the first semiconductor layer;

[0045] Figure 3 yes Figure 1 Layout diagram of the first gate metal layer in the middle;

[0046] Figure 4 yes Figure 1Layout diagram of the second gate metal layer;

[0047] Figure 5 yes Figure 1 Layout diagram of the second semiconductor layer;

[0048] Figure 6 yes Figure 1 Layout diagram of the third gate metal layer;

[0049] Figure 7 This is a layout diagram of the display substrate described in at least one embodiment of the present invention;

[0050] Figure 8 yes Figure 7 Layout diagram of the third gate metal layer;

[0051] Figure 9 yes Figure 7 Layout diagram of the first gate metal layer in the middle;

[0052] Figure 10 This is a layout diagram of the display substrate described in at least one embodiment of the present invention;

[0053] Figure 11 yes Figure 10 Layout diagram of the first gate metal layer in the middle;

[0054] Figure 12 yes Figure 10 Layout diagram of the third gate metal layer;

[0055] Figure 13 yes Figure 10 Layout diagram of the first source / drain metal layer in the image;

[0056] Figure 14 This is a layout diagram of the display substrate described in at least one embodiment of the present invention;

[0057] Figure 15 yes Figure 14 Layout diagram of the first semiconductor layer;

[0058] Figure 16 yes Figure 14 Layout diagram of the first gate metal layer in the middle;

[0059] Figure 17 yes Figure 14 Layout diagram of the second gate metal layer;

[0060] Figure 18 yes Figure 14 Layout diagram of the second semiconductor layer;

[0061] Figure 19 yes Figure 14 Layout diagram of the third gate metal layer;

[0062] Figure 20 yes Figure 14 Layout diagram of the first source / drain metal layer in the image;

[0063] Figure 21 This is a structural diagram of at least one embodiment of a pixel circuit;

[0064] Figure 22 This is a circuit diagram of at least one embodiment of a pixel circuit. Detailed Implementation

[0065] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0066] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0067] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0068] The display substrate described in this embodiment of the present invention includes a substrate and a plurality of signal lines extending along a first direction disposed on the substrate; the plurality of signal lines include light emission control lines;

[0069] The ratio between the overlapping area of ​​the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the signal lines (excluding the light-emitting control line) on the substrate, and the area of ​​the orthographic projection of the light-emitting control line on the substrate, is greater than or equal to 0 and less than or equal to 0.8.

[0070] In related technologies, during high-frequency displays, the frequency of the light-emitting control signal is relatively high, resulting in high power consumption for the light-emitting control signal generation module. Furthermore, the power consumption caused by the parasitic capacitance of the light-emitting control line is considered abnormal power loss, necessitating a reduction in this abnormal power loss. Therefore, this embodiment of the invention sets the ratio between the overlapping area of ​​the orthographic projection of the light-emitting control line onto the substrate and the orthographic projection of all signal lines (excluding the light-emitting control line) onto the substrate, and the area of ​​the orthographic projection of the light-emitting control line onto the substrate, to be greater than or equal to 0 and less than or equal to 0.8. The extension direction of the signal lines is a first direction, thereby reducing the parasitic capacitance of the light-emitting control line and lowering power consumption.

[0071] Optionally, the first direction can be horizontal, but is not limited to this.

[0072] In at least one embodiment of the present invention, the ratio between the overlapping area of ​​the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the signal lines (excluding the light-emitting control line) on the substrate, and the area of ​​the orthographic projection of the light-emitting control line on the substrate, is greater than or equal to 0 and less than or equal to 0.8.

[0073] In a preferred embodiment, the ratio can be greater than or equal to 0 and less than or equal to 0.5. For example, the ratio can be 0, 0.1, 0.2, 0.3, 0.4 or 0.5.

[0074] At least one embodiment of this utility model redesigns the stacked structure layout of the AA (effective display) area, removing the horizontal traces stacked directly above the light-emitting control line, so that there are no metal traces above the light-emitting control line forming a large parasitic capacitance with it, thereby reducing the high-frequency loss power consumption of the light-emitting control signal generation module, and thus achieving the effect of reducing the power consumption of DDIC (display driver integrated circuit) by at least 20% in 1Hz driving mode.

[0075] With the gradual maturation of LTPO (Low Temperature Polycrystalline Oxide) technology, LTPO adaptive frequency refresh technology has achieved mass production applications. With the addition of adaptive frequency conversion technology, the power consumption of DDIC (Display Driver Integrated Circuit) has been significantly reduced. Currently, the lowest operating frequency for adaptive frequency reduction technology is 1Hz, and there is still room for further improvement in DDIC power consumption under 1Hz drive. At least one embodiment of this invention can achieve a reduction of at least 20% in DDIC power consumption under 1Hz drive mode.

[0076] In at least one embodiment of the present invention, the plurality of signal lines include a first signal line;

[0077] The orthogonal projection of the light-emitting control line on the substrate covers the orthogonal projection of the first signal line on the substrate;

[0078] The line width of the first signal line is smaller than the line width of the light emission control line.

[0079] In a specific implementation, the multiple signal lines may include a first signal line, and the orthographic projection of the light-emitting control line on the substrate may cover the orthographic projection of the first signal line on the substrate; the line width of the first signal line is set to be smaller than the line width of the light-emitting control line, so that the overlap area between the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the first signal line on the substrate is small.

[0080] Optionally, the first signal line can be a first initial signal line.

[0081] Figure 1 This is a layout diagram of the display substrate according to at least one embodiment of the present invention. Figure 2 yes Figure 1 The layout diagram of the first semiconductor layer in the middle. Figure 3 yes Figure 1 Layout diagram of the first gate metal layer in the middle. Figure 4 yes Figure 1 The layout diagram of the second gate metal layer in the middle, Figure 5 yes Figure 1 The layout diagram of the second semiconductor layer in the middle. Figure 6 yes Figure 1 The layout diagram of the third gate metal layer.

[0082] like Figure 1 As shown, the display substrate of at least one embodiment of the present invention includes a pixel circuit, a first scan line, a second scan line GP, a first reset control line RH, a second reset control line RP, a first initial signal line I1, a second initial signal line I2, and a third initial signal line I3;

[0083] The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor;

[0084] like Figures 1-6 As shown, the first scan line includes a first scan line portion GN1 and a second scan line portion GN2;

[0085] GN1 is formed on the second gate metal layer, and GN2 is formed on the third gate metal layer; the second transistor is an n-type transistor, an oxide transistor, and a dual-gate transistor; the first, third, fourth, fifth, sixth, seventh, and eighth transistors are p-type transistors.

[0086] exist Figure 4 In the diagram, G21 is the bottom gate of the second transistor. Figure 6 In the diagram, G22 is the top gate of the second transistor;

[0087] exist Figure 2 In the diagram, A1 represents the active pattern of the first transistor, A3 represents the active pattern of the third transistor, A4 represents the active pattern of the fourth transistor, A5 represents the active pattern of the fifth transistor, A6 represents the active pattern of the sixth transistor, A7 represents the active pattern of the seventh transistor, and A8 represents the active pattern of the eighth transistor.

[0088] exist Figure 3 In the diagram, GP is the second scan line, G3 is the gate of the third transistor, and G3 is multiplexed as the first plate of the first capacitor; EM is the light emission control line, RH is the first reset control line, and RP is the second reset control line.

[0089] exist Figure 4 In the diagram, the plate labeled C1b is the second plate of C1;

[0090] exist Figure 5 In the diagram, the line labeled I1 is the first initial signal line, the line labeled I2 is the second initial signal line, and the line labeled I3 is the third initial signal line.

[0091] like Figures 1-6 As shown, GP, EM, RH1, I1, I2 and I3 all extend in the horizontal direction;

[0092] The orthographic projection of EM on the substrate covers the orthographic projection of I1 on the substrate. The line width K1 of I1 is smaller than the line width K2 of EM, such that the ratio between the overlapping area of ​​the orthographic projection of EM on the substrate and the orthographic projection of I1 on the substrate and the area of ​​the orthographic projection of EM on the substrate is greater than 0 and less than or equal to 80%.

[0093] By adopting Figures 1-6 At least one embodiment shown can change only the mask design of the third gate metal layer, with minimal impact on layout changes.

[0094] exist Figures 1-6 In at least one embodiment, the linewidth of I1 can be changed from 2.0 μm to 1.6 μm, but it is not limited thereto. In specific implementation, the linewidth of I1 can also be changed to 1.4 μm, 1.2 μm or 1 μm.

[0095] In at least one embodiment of the present invention, the third transistor included in the driving circuit may have a U-shaped channel, which can reduce the channel length of the third transistor and make the channel width-to-length ratio of the third transistor smaller, which is beneficial for subdividing the driving current at low gray levels.

[0096] In at least one embodiment of the present invention, the plurality of signal lines include a first signal line;

[0097] The orthographic projection of the light-emitting control line on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

[0098] In specific implementation, the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the first signal line on the substrate can partially overlap, changing from the current direct overlap state of the light-emitting control line and the first signal line to a half overlap state of the light-emitting control line and the first signal line. The direct overlap area can be reduced by about 50%, or even more.

[0099] In at least one embodiment of the present invention, the light emission control line includes a first light emission control signal line portion and a second light emission control signal line portion; both the first light emission control signal line portion and the second light emission control signal line portion extend along a first direction;

[0100] The orthographic projection of the first light-emitting control signal line on the substrate does not overlap with the orthographic projection of the first signal line on the substrate, while the orthographic projection of the second light-emitting control signal line on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

[0101] In a specific implementation, the light emission control line may include a first light emission control signal line portion and a second light emission control signal line portion extending along a first direction, wherein the orthographic projection of the first light emission control signal line portion on the substrate and the orthographic projection of the first signal line on the substrate may not overlap.

[0102] Figure 7 This is a layout diagram of the display substrate described in at least one embodiment of the present invention.

[0103] Figure 7 At least one embodiment shown and Figure 1 The difference in at least one of the embodiments shown is that the position of I1 is changed, and the orthographic projection of EM on the substrate is set to partially overlap with the orthographic projection of I1 on the substrate.

[0104] Figure 7 The layout of the first semiconductor layer in the middle can be as follows: Figure 2 As shown, Figure 7 The layout of the first gate metal layer in the middle can be as follows: Figure 3 and Figure 9 As shown, Figure 7The layout of the second gate metal layer can be as follows: Figure 4 As shown, Figure 7 The layout of the second semiconductor layer can be as follows: Figure 5 As shown.

[0105] Figure 8 yes Figure 7 Layout diagram of the third gate metal layer;

[0106] like Figure 8 As shown, the line labeled I1 is the first initial signal line, the line labeled I2 is the second initial signal line, and the line labeled I3 is the third initial signal line.

[0107] exist Figure 9 In the diagram, EM1 is the first light-emitting control signal line and EM2 is the second light-emitting control signal line. EM1 and EM2 extend in the horizontal direction.

[0108] like Figures 7-9 As shown, the orthographic projection of EM1 on the substrate does not overlap with the orthographic projection of I1 on the substrate, and the orthographic projection of EM2 on the substrate does not overlap with the orthographic projection of I1 on the substrate.

[0109] EM1, EM2, RH and RP can be arranged sequentially along the vertical direction.

[0110] In practice, EM1 and EM2 can be interchanged, that is, EM2, EM1, RH and RP can be arranged in sequence along the vertical direction.

[0111] In at least one embodiment of the present invention, the plurality of signal lines include a first signal line; the first signal line includes a plurality of first signal line portions and connecting line portions; the first signal line portions and the connecting line portions are arranged alternately along a first direction; adjacent first signal line portions and connecting line portions are electrically connected; the first signal line portions extend along the first direction.

[0112] The orthographic projection of the light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the first signal line portion on the substrate; the orthographic projection of the connecting line portion on the substrate does not overlap with the orthographic projection of the first signal line portion on the substrate.

[0113] In at least one embodiment of the present invention, the length of the light-emitting control line is greater than the sum of the lengths of the plurality of first signal lines.

[0114] In a specific implementation, the first signal line may include a first signal line portion and a connecting line portion arranged alternately along a first direction, the first signal line portion extending along the first direction, and the connecting line portion being an arc-shaped connecting line portion;

[0115] The orthographic projection of the light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate. The orthographic projection of the connecting line on the substrate and the orthographic projection of the first signal line on the substrate are set to not overlap, so as to reduce the overlap area between the light-emitting control line and the first signal line.

[0116] Figure 10 This is a layout diagram of the display substrate described in at least one embodiment of the present invention.

[0117] Figure 10 The layout diagram of the first semiconductor layer in the middle is as follows Figure 2 As shown, Figure 10 The layout diagram of the first gate metal layer in the middle is as follows Figure 11 As shown, Figure 10 The layout diagram of the second gate metal layer is as follows: Figure 4 As shown, Figure 10 The layout diagram of the second semiconductor layer is as follows: Figure 5 As shown, Figure 10 The layout diagram of the third gate metal layer is as follows: Figure 12 As shown, Figure 10 The layout diagram of the first source / drain metal layer in the middle is as follows: Figure 13 As shown.

[0118] exist Figure 12 In the diagram, the part labeled I11 is the first first signal line section, and the part labeled I21 is the second first signal line section;

[0119] exist Figure 13 In the diagram, the part labeled L1 is the first connecting line section;

[0120] like Figures 10-13 As shown, I11, L1 and I21 are arranged in sequence along the horizontal direction, and the extension directions of I11 and I21 are horizontal.

[0121] I11 and L1 are electrically connected through the first via H1, and I21 and L1 are electrically connected through the second via H2.

[0122] exist Figure 13 In the diagram, IS1 is the first longitudinal signal line section, and IS2 is the second longitudinal signal line section.

[0123] exist Figures 10-13 In at least one embodiment shown, the mask of the third gate metal layer is redesigned to break the lateral first signal line. The lateral signal line is bridged by the longitudinal signal line portion formed on the first source / drain metal layer and the line connecting the first semiconductor layer to realize the function of lateral input of the first initial voltage signal. The laterally extending first signal line portions are retained, and the unnecessary horizontally extending portions of the first signal line are reduced to reduce the overlapping area between the EM and the first signal line.

[0124] use Figures 10-13 At least one embodiment shown does not require moving the original routing position of the first signal line; it only requires interrupting the first signal line, resulting in minimal design changes.

[0125] Optionally, the ratio of the sum of the lengths of the plurality of first signal lines to the length of the light-emitting control line is greater than 0 and less than or equal to 0.8.

[0126] In specific implementation, the ratio of the sum of the lengths of each first signal line portion to the length of the light-emitting control line can be greater than 0 and less than or equal to 0.8; for example, the ratio of the sum of the lengths of each first signal line portion to the length of the light-emitting control line can be 0.3, 0.4, 0.5, 0.6, 0.7 or 0.8, but is not limited thereto.

[0127] The display substrate described in at least one embodiment of the present invention further includes a multi-row, multi-column pixel circuit disposed on the substrate; the first signal line portion is electrically connected to the active pattern of at least one transistor included in the pixel circuit through the connecting line portion;

[0128] The first signal line portion and the connecting line portion are disposed in different layers.

[0129] In a specific implementation, the first signal line portion can be electrically connected to the active pattern of at least one transistor included in the pixel circuit through the connecting line portion, and the first signal line portion and the connecting line portion can be disposed on different layers.

[0130] like Figures 10-13 As shown, the first first signal line I11 can be electrically connected to the active pattern A8 of the eighth transistor through the first connecting line L1, and the second first signal line I21 can be electrically connected to the active pattern A8 of the eighth transistor through the first connecting line L1.

[0131] I11 and L1 can be set on different layers, and I21 and L1 can be set on different layers.

[0132] In at least one embodiment of the present invention, the plurality of signal lines include a first signal line;

[0133] The orthographic projection of the light-emitting control line on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

[0134] In practical implementation, the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the first signal line on the substrate can be set to not overlap. All horizontally extending metal traces directly above the light-emitting control line are cleared. No metal traces completely parallel to the light-emitting control line are provided on the side of the light-emitting control line away from the substrate. Large-area metal stacks are avoided, and parasitic capacitance on the light-emitting control line is reduced as much as possible, thereby reducing its interference with the light-emitting control signal. The improvement of parasitic capacitance is thorough and will not affect the process margin, making it suitable for mass production.

[0135] In at least one embodiment of the present invention, the plurality of signal lines include a first reset control line;

[0136] The orthographic projection of the first reset control line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate.

[0137] In a specific implementation, the plurality of signal lines may further include a first reset control line, wherein the orthographic projection of the first reset control line on the substrate and the orthographic projection of the first signal line on the substrate are set to at least partially overlap, and the first signal line is moved down so that it does not overlap with the light emission control line in a direction perpendicular to the substrate.

[0138] Optionally, the light emission control line is disposed on the same layer as the first reset control line; the first reset control line is disposed on a different layer from the first signal line.

[0139] In a specific implementation, the light emission control line and the first reset control line can both be disposed on the first gate metal layer, and the first signal line can be disposed on the third gate metal layer.

[0140] In at least one embodiment of the present invention, the plurality of signal lines further include a second signal line, a third signal line, and a second reset control line; the second signal line, the third signal line, and the second reset control line all extend along a first direction;

[0141] The orthographic projection of the second reset control line on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate;

[0142] The second reset control line, the second signal line, and the third signal line are arranged in different layers.

[0143] Optionally, the first signal line can be a first initial signal line, the second signal line can be a second initial signal line, and the third signal line can be a third initial signal line.

[0144] In at least one embodiment of the present invention, the light emission control line, the first reset control line and the second reset control line are all formed on the first metal layer, the third signal line is formed on the second metal layer, and the first signal line and the second signal line are both formed on the third metal layer;

[0145] The orthographic projection of the third signal line on the substrate does not overlap with the orthographic projection of the conductive pattern formed on the first metal layer on the substrate.

[0146] In a specific implementation, the second signal line, the third signal line, and the second reset control line can all extend along the first direction. The orthographic projection of the second reset control line on the substrate and the orthographic projection of the second signal line on the substrate can be set to at least partially overlap. The second reset control line can be disposed on the first gate metal layer, the second signal line can be disposed on the third gate metal layer, and the third signal line can be disposed on the second gate metal layer. Since the distance between the first metal layer and the second metal layer is relatively close, the orthographic projection of the third signal line on the substrate and the orthographic projection of the conductive pattern formed on the first metal layer on the substrate are set to not overlap to avoid directly forming a capacitor.

[0147] Figure 14 This is a layout diagram of the display substrate described in at least one embodiment of the present invention.

[0148] Figure 15 yes Figure 14 The layout diagram of the first semiconductor layer in the middle. Figure 16 yes Figure 14 Layout diagram of the first gate metal layer in the middle. Figure 17 yes Figure 14 The layout diagram of the second gate metal layer in the middle, Figure 18 yes Figure 14 The layout diagram of the second semiconductor layer in the middle. Figure 19 yes Figure 14 Layout diagram of the third gate metal layer in the middle. Figure 20 yes Figure 14 The layout diagram of the first source / drain metal layer in the image.

[0149] exist Figure 14 In the diagram, the line labeled GP is the second scan line, the first scan line includes a first scan line portion GN1 and a second scan line portion GN2, the line labeled EM is the light emission control line, the line labeled RH is the first reset control line, the line labeled I1 is the first initial signal line, and the line labeled I3 is the third initial signal line.

[0150] exist Figure 15In the diagram, A1 represents the active pattern of the first transistor, A3 represents the active pattern of the third transistor, A4 represents the active pattern of the fourth transistor, A5 represents the active pattern of the fifth transistor, A6 represents the active pattern of the sixth transistor, A7 represents the active pattern of the seventh transistor, and A8 represents the active pattern of the eighth transistor.

[0151] exist Figure 16 In the diagram, the line labeled RP is the second reset control line, the line labeled G3 is the gate of the third transistor, and G3 is multiplexed as the first plate of the first capacitor.

[0152] exist Figure 17 In the diagram, the plate labeled C1b is the second plate of the first capacitor;

[0153] exist Figure 18 In the diagram, the one labeled A2 is the active pattern of the second transistor;

[0154] exist Figure 19 In the diagram, the line labeled I2 is the second initial signal line;

[0155] exist Figure 20 In the diagram, the part labeled DB1 is the first conductive part.

[0156] exist Figures 14-20 In at least one embodiment shown, the orthographic projection of EM on the substrate and the orthographic projection of I1 on the substrate do not overlap, so as to clear the metal traces extending laterally on the side of EM away from the substrate, minimize the parasitic capacitance on the light emission control line, reduce its interference with the light emission control signal, and reduce power consumption.

[0157] The third initial signal line I3 is adjusted from being disposed on the third gate metal layer to being disposed on the second gate metal layer. The first initial signal line I1 is moved down. The orthographic projection of I1 on the substrate is set to at least partially overlap with the orthographic projection of RH on the substrate. The orthographic projection of I2 on the substrate is set to at least partially overlap with the orthographic projection of RP on the substrate.

[0158] In at least one embodiment of the present invention, the plurality of signal lines include a first signal line, a second signal line, a third signal line, a first reset control line, a second reset control line, a first scan line, a second scan line, a data line, a power supply voltage line, and a first voltage line;

[0159] The pixel circuit includes a light-emitting element, a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a third initialization circuit.

[0160] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0161] The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage line and the second node respectively, and is used to control the connection or disconnection between the power supply voltage line and the second node under the control of the light-emitting control signal provided by the light-emitting control line;

[0162] The second light-emitting control circuit is electrically connected to the light-emitting control line, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element is electrically connected to the first voltage line;

[0163] The data writing circuit is electrically connected to the second scan line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second scan signal provided by the second scan line;

[0164] The compensation control circuit is electrically connected to the first scan line, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first scan signal provided by the first scan line.

[0165] The first initialization circuit is electrically connected to the first reset control line, the first signal line and the second node respectively, and is used to write the voltage signal provided by the first signal line into the second node under the control of the first reset control signal provided by the first reset control line;

[0166] The second initialization circuit is electrically connected to the first reset control line, the second signal line, and the first electrode of the light-emitting element, respectively, and is used to write the voltage signal provided by the second signal line into the first electrode of the light-emitting element under the control of the first reset control signal;

[0167] The third initialization circuit is electrically connected to the second reset control line, the third signal line, and the third node, respectively, and is used to write the voltage signal provided by the third signal line into the third node under the control of the second reset control signal provided by the second reset control line.

[0168] In at least one embodiment of the present invention, the light emission control line, the first signal line, the second signal line, the third signal line, the first reset control line, the second reset control line, the first scan line, and the second scan line extend along a first direction;

[0169] The data line, the power supply voltage line, and the first voltage line extend along a second direction; the first direction intersects the second direction.

[0170] Optionally, the first direction can be a horizontal direction, and the second direction can be a vertical direction. The data line, the power supply voltage line, and the first voltage line can be disposed on the source-drain metal layer. The source-drain metal layer is far from the first gate metal layer. Furthermore, the data line, the power supply voltage line, and the first voltage line all extend along the second direction, so the overlap area with the light emission control line is small.

[0171] Optionally, the first signal line can be a first initial signal line, the second signal line can be a second initial signal line, the third signal line can be a third initial signal line, and the first voltage line can be a low voltage line.

[0172] like Figure 21 As shown, the multiple signal lines include a first signal line S1, a second signal line S2, a third signal line S3, a first reset control line RH, a second reset control line RP, a first scan line GN, a second scan line GP, a data line DL, a power supply voltage line VDD, and a first voltage line V1; the display substrate also includes pixel circuits disposed on the substrate;

[0173] The pixel circuit includes a light-emitting element E1, a driving circuit 10, a first light-emitting control circuit 11, a second light-emitting control circuit 12, a data writing circuit 13, a compensation control circuit 14, a first initialization circuit 15, a second initialization circuit 16, and a third initialization circuit 17.

[0174] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1.

[0175] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line EM, the power supply voltage line VDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage line VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control line EM.

[0176] The second light-emitting control circuit 12 is electrically connected to the light-emitting control line EM, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal; the second pole of the light-emitting element E1 is electrically connected to the first voltage line V1.

[0177] The data writing circuit 13 is electrically connected to the second scan line GP, the data line DL and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the second scan signal provided by the second scan line GP.

[0178] The compensation control circuit 14 is electrically connected to the first scan line GN, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first scan signal provided by the first scan line GN.

[0179] The first initialization circuit 15 is electrically connected to the first reset control line RH, the first signal line S1 and the second node N2 respectively, and is used to write the voltage signal provided by the first signal line S1 into the second node N2 under the control of the first reset control signal provided by the first reset control line RH.

[0180] The second initialization circuit 16 is electrically connected to the first reset control line RH, the second signal line S2 and the first pole of the light-emitting element E1, respectively, and is used to write the voltage signal provided by the second signal line S2 into the first pole of the light-emitting element E1 under the control of the first reset control signal.

[0181] The third initialization circuit 17 is electrically connected to the second reset control line RP, the third signal line S3 and the third node N3 respectively, and is used to write the voltage signal provided by the third signal line S3 into the third node N3 under the control of the second reset control signal provided by the second reset control line RP.

[0182] like Figure 22 As shown, in Figure 21 Based on at least one embodiment of the pixel circuit shown, the light-emitting element is an organic light-emitting diode O1; the third initialization circuit includes a first transistor T1, the compensation control circuit includes a second transistor T2, the driving circuit includes a third transistor T3, the data writing circuit includes a fourth transistor T4, the first light-emitting control circuit includes a fifth transistor T5, the second light-emitting control circuit includes a sixth transistor T6, the second initialization circuit includes a seventh transistor T7, and the first initialization circuit includes an eighth transistor T8.

[0183] The gate of T1 is electrically connected to RP, the source of T1 is electrically connected to the third initial signal line I3, and the drain of T1 is electrically connected to N3.

[0184] The gate of T2 is electrically connected to GN, the source of T2 is electrically connected to N1, and the drain of T2 is electrically connected to N3.

[0185] The gate of T3 is electrically connected to N1, the source of T3 is electrically connected to N2, and the drain of T3 is electrically connected to N3.

[0186] The gate of T4 is electrically connected to GP, the source of T4 is electrically connected to DL, and the drain of T4 is electrically connected to N2.

[0187] The gate of T5 is electrically connected to EM, the source of T5 is electrically connected to VDD, and the drain of T5 is electrically connected to N2.

[0188] The gate of T6 is electrically connected to EM, the source of T6 is electrically connected to N3, and the drain of T6 is electrically connected to the anode of O1.

[0189] The gate of T7 is electrically connected to RH, the source of T7 is electrically connected to the second initial signal line I2, the drain of T7 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage line VSS.

[0190] The gate of T8 is electrically connected to RH, the source of T8 is electrically connected to the first initial signal line I1, and the drain of T8 is electrically connected to N2.

[0191] At least one embodiment of the pixel circuit further includes a first capacitor C1;

[0192] The first plate of C1 is electrically connected to N1, and the second plate of C1 is electrically connected to the power supply voltage line VDD.

[0193] exist Figure 22 In at least one embodiment shown, T2 is an n-type transistor, and T1, T3-T8 are p-type transistors.

[0194] Figure 22 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include a first stage, a second stage, a third node, and a fourth stage set sequentially.

[0195] In the first stage, T5 and T6 are turned off. After the reset preparation, T1 and T2 are turned on. The third initial voltage signal provided by I3 is written into N1 through T1 and T2 to reset the potential of the gate of T3.

[0196] In the second stage (the second stage is the data writing stage), T1 is off and T4 is on. The data voltage Vdata provided by DL is written to N1 through T4, T3 and T2. The potential of N1 is Vdata + Vth; Vth is the threshold voltage of T3.

[0197] In the third stage, T2 and T4 are turned off, and T7 and T8 are turned on. The first initial voltage signal provided by I1 is written to N2 through T8 to reset the potential of N2. The second initial voltage signal provided by I2 is written to the anode of O1 through T7 to reset the anode of O1.

[0198] In the fourth stage (the light-emitting stage), T7 and T8 are turned off, T5 and T6 are turned off, and T3 drives O1 to emit light.

[0199] The above four stages constitute the complete working steps for refreshing one frame. During the actual display time of one frame, the actual switching counts of T5 and T6 (transistors controlled by EM) are 12, 18, 32, or 36 times. The number of EM refreshes varies depending on different customer requirements. In specific implementation, the EM can switch on and off 18 times within one frame. The following description will use 18 switching counts of the EM within one frame as an example.

[0200] When the screen refreshes at 120Hz, 120 frames are refreshed per second. The EM switches on and off 18 times per frame. The frequency of the EM's light emission control signal is 2160Hz. The frequencies of the first scan signal provided by GN, the second scan signal provided by GP, and the second reset control signal provided by RP are all 120Hz. Due to the use of high-precision frequency conversion mode, the frequency of the first reset control signal provided by RH, i.e., the anode reset frequency, is 360Hz. When the screen refreshes at 1Hz, only one frame is refreshed per second. According to the low-frequency drive logic of LTPO (Low Temperature Polycrystalline Oxide) pixel circuit, the 1Hz drive only has timing related to refresh. The frequencies of the first scan signal, the second scan signal, and the second reset control signal are reduced to 1Hz. The timing related to display, the frequency of the light emission control signal remains 2160Hz, and the frequency of the first reset control signal remains 360Hz.

[0201] The above analysis shows that under 1Hz display conditions, the circuit responsible for the refresh section has already implemented frequency reduction processing, and the 2160Hz refresh rate of the light emission control signal becomes the main power consumption load of the DDIC. Based on the above problem, this embodiment of the invention sets the ratio between the overlapping area of ​​the orthographic projection of the light emission control line on the substrate and the orthographic projection of the signal lines (excluding the light emission control line) on the substrate, and the area of ​​the orthographic projection of the light emission control line on the substrate, to be greater than or equal to 0 and less than or equal to 0.8. The extension direction of the signal lines is a first direction, in order to reduce the parasitic capacitance of the light emission control line and thus reduce the power consumption of the DDIC.

[0202] The display device described in this embodiment includes the display substrate described above.

[0203] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.

Claims

1. A display substrate, characterized in that, It includes a substrate and a plurality of signal lines extending along a first direction disposed on the substrate; the plurality of signal lines include light emission control lines; The ratio between the overlapping area of ​​the orthographic projection of the light-emitting control line on the substrate and the orthographic projection of the signal lines (excluding the light-emitting control line) on the substrate, and the area of ​​the orthographic projection of the light-emitting control line on the substrate, is greater than or equal to 0 and less than or equal to 0.

8.

2. The display substrate as described in claim 1, characterized in that, The plurality of signal lines includes a first signal line; The orthogonal projection of the light-emitting control line on the substrate covers the orthogonal projection of the first signal line on the substrate; The line width of the first signal line is smaller than the line width of the light emission control line.

3. The display substrate as described in claim 1, characterized in that, The plurality of signal lines includes a first signal line; The orthographic projection of the light-emitting control line on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

4. The display substrate as described in claim 3, characterized in that, The light emission control line includes a first light emission control signal line portion and a second light emission control signal line portion; both the first light emission control signal line portion and the second light emission control signal line portion extend along a first direction. The orthographic projection of the first light-emitting control signal line on the substrate does not overlap with the orthographic projection of the first signal line on the substrate, while the orthographic projection of the second light-emitting control signal line on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

5. The display substrate as described in claim 1, characterized in that, The plurality of signal lines includes a first signal line; the first signal line includes a plurality of first signal line portions and connecting line portions; the first signal line portions and the connecting line portions are arranged alternately along a first direction; adjacent first signal line portions and connecting line portions are electrically connected; the first signal line portions extend along the first direction. The orthographic projection of the light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate; The orthographic projection of the connecting line portion on the substrate does not overlap with the orthographic projection of the first signal line portion on the substrate.

6. The display substrate as described in claim 5, characterized in that, The length of the light-emitting control line is greater than the sum of the lengths of the plurality of first signal lines.

7. The display substrate as described in claim 5, characterized in that, The ratio of the sum of the lengths of the plurality of first signal lines to the length of the light-emitting control line is greater than 0 and less than or equal to 0.

8.

8. The display substrate as described in claim 5, characterized in that, It also includes a multi-row, multi-column pixel circuit disposed on the substrate; the first signal line portion is electrically connected to the active pattern of at least one transistor included in the pixel circuit through the connecting line portion; The first signal line portion and the connecting line portion are disposed in different layers.

9. The display substrate as described in claim 1, characterized in that, The plurality of signal lines includes a first signal line; The orthographic projection of the light-emitting control line on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

10. The display substrate as claimed in claim 9, characterized in that, The plurality of signal lines includes a first reset control line; The orthographic projection of the first reset control line on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate.

11. The display substrate as claimed in claim 10, characterized in that, The light emission control line is disposed on the same layer as the first reset control line; the first reset control line is disposed on a different layer than the first signal line.

12. The display substrate as claimed in claim 10, characterized in that, The plurality of signal lines also includes a second signal line, a third signal line, and a second reset control line; the second signal line, the third signal line, and the second reset control line all extend along a first direction; The orthographic projection of the second reset control line on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate; The second reset control line, the second signal line, and the third signal line are arranged in different layers.

13. The display substrate as described in claim 12, characterized in that, The light emission control line, the first reset control line, and the second reset control line are all formed on the first metal layer, the third signal line is formed on the second metal layer, and the first signal line and the second signal line are both formed on the third metal layer. The orthographic projection of the third signal line on the substrate does not overlap with the orthographic projection of the conductive pattern formed on the first metal layer on the substrate.

14. The display substrate according to any one of claims 1 to 13, characterized in that, The plurality of signal lines include a first signal line, a second signal line, a third signal line, a first reset control line, a second reset control line, a first scan line, a second scan line, a data line, a power supply voltage line, and a first voltage line; the display substrate also includes pixel circuitry disposed on the substrate; The pixel circuit includes a light-emitting element, a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a third initialization circuit. The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node. The first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage line and the second node respectively, and is used to control the connection or disconnection between the power supply voltage line and the second node under the control of the light-emitting control signal provided by the light-emitting control line; The second light-emitting control circuit is electrically connected to the light-emitting control line, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element is electrically connected to the first voltage line; The data writing circuit is electrically connected to the second scan line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second scan signal provided by the second scan line; The compensation control circuit is electrically connected to the first scan line, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the first scan signal provided by the first scan line. The first initialization circuit is electrically connected to the first reset control line, the first signal line and the second node respectively, and is used to write the voltage signal provided by the first signal line into the second node under the control of the first reset control signal provided by the first reset control line; The second initialization circuit is electrically connected to the first reset control line, the second signal line, and the first electrode of the light-emitting element, respectively, and is used to write the voltage signal provided by the second signal line into the first electrode of the light-emitting element under the control of the first reset control signal; The third initialization circuit is electrically connected to the second reset control line, the third signal line, and the third node, respectively, and is used to write the voltage signal provided by the third signal line into the third node under the control of the second reset control signal provided by the second reset control line.

15. The display substrate as claimed in claim 14, characterized in that, The light emission control line, the first signal line, the second signal line, the third signal line, the first reset control line, the second reset control line, the first scan line, and the second scan line extend along a first direction; The data line, the power supply voltage line, and the first voltage line extend along a second direction; the first direction intersects the second direction.

16. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 15.

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