Integrated circuit device

Abstract

The embodiment of the utility model relates to an integrated circuit device. An integrated circuit device includes: a substrate including a semiconductor device; a first interconnect structure disposed over the semiconductor device, where the first interconnect structure includes: a plurality of first vias; and a first conductive metal electrically coupled to the semiconductor device through the first via; the dielectric layer surrounds the first interconnection structure; an insulating film disposed over the first conductive metal; and a second interconnect structure penetrating the insulating film and electrically coupled to the first conductive metal.

Description

Technical Field

[0001] This utility model relates to an integrated circuit device. Background Technology

[0002] In integrated circuits, a large number of circuit elements (such as transistors, capacitors, resistors, and the like) are formed in or on a suitable substrate. Due to the large number of circuit elements and the complex layout required for advanced integrated circuits, electrical connections between individual circuit elements are generally not established within the same layer on which the circuit elements are fabricated. Typically, these electrical connections are formed in one or more additional metallization layers. These metallization layers generally contain metal lines to provide intra-layer electrical connections, and also contain multiple inter-layer connections (also referred to as pathways) formed of suitable metals. Thus, pathways provide electrical connections between two adjacent stacked metallization layers.

[0003] As the size of circuit elements in modern integrated circuits continues to decrease, the number of circuit elements per given chip area is increasing, which necessitates a continuous increase in the number of electrical connections to provide the desired circuit functionality. Utility Model Content

[0004] Embodiments of this utility model relate to a method of manufacturing an integrated circuit device, comprising: forming a semiconductor device on a substrate; forming a first interconnect structure above the semiconductor device and a dielectric layer for surrounding the first interconnect structure, wherein the first interconnect structure includes a first conductive metal electrically coupled to the semiconductor device through a plurality of first channels; and forming a second interconnect structure above the first conductive metal, wherein forming the second interconnect structure includes: forming an insulating film above the first conductive metal; depositing an etch stop layer above the insulating film, wherein the etch stop layer and the insulating film comprise different materials; depositing an isolation layer above the etch stop layer; performing a first etch operation to form a hole penetrating the isolation layer to expose the etch stop layer; and causing the hole to extend through the etch stop layer and the insulating film and stop at the first conductive metal.

[0005] Embodiments of this utility model relate to a method of manufacturing an integrated circuit device, comprising: providing a first die, the first die comprising: a first substrate; a first interconnect structure located above the first substrate; and a first dielectric layer for surrounding the first interconnect structure; providing a second die, the second die comprising: a second substrate; a second interconnect structure located above the second substrate; a second dielectric layer for surrounding the second interconnect structure; an insulating film located on the second interconnect structure; an etch stop layer located above the second dielectric layer and the insulating film; and an isolation layer located above the etch stop layer; forming a hole penetrating the isolation layer to expose the etch stop layer; causing the hole to extend through the etch stop layer and the insulating film; and depositing a conductive material in the hole to form a conductive path electrically coupled to the second interconnect structure.

[0006] Embodiments of this utility model relate to an integrated circuit device, comprising: a substrate including a plurality of semiconductor devices; an interconnect structure electrically coupled to the substrate and including: a conductive metal electrically coupled to the substrate; an insulating film located on the conductive metal, wherein the insulating film and the conductive metal include a common element; an etch stop layer located above the insulating film; an isolation layer located above the etch stop layer; and a conductive path penetrating the isolation layer, the etch stop layer, and the insulating film and electrically coupled to the conductive metal. Attached Figure Description

[0007] The aspects of this disclosure are best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 This is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments of the present invention.

[0009] Figures 2A to 2N This is a cross-sectional view of an intermediate stage of a method for manufacturing an integrated circuit device according to some embodiments of the present invention.

[0010] Figure 3 This is a flowchart of a method for manufacturing an integrated circuit device according to some embodiments of the present invention.

[0011] Figures 4A to 4P This is a cross-sectional view of an intermediate stage of a method for manufacturing an integrated circuit device according to some embodiments of the present invention. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, an embodiment in which a first member is formed above or on a second member may include embodiments in which the first and second members form direct contact, and may also include embodiments in which additional members may be formed between the first and second members such that the first and second members do not form direct contact. Additionally, element symbols and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms (such as "below," "below," "down," "above," "upper," and the like) may be used herein to describe the relationship between one element or component illustrated in the figures and another element or component(s). In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and thus the spatial relative descriptive terms used herein may also be interpreted.

[0014] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited to these terms. These terms may be used only to distinguish elements, components, regions, layers, or sections from one another. Unless the context clearly indicates otherwise, the terms such as “first,” “second,” and “third” as used herein do not imply sequence, order, or importance.

[0015] While the numerical ranges and parameters described in this disclosure are approximate, the values ​​presented in specific examples should be reported as precisely as possible. However, any numerical value inherently contains a specific error that is necessarily caused by the normal deviations seen in its corresponding test measurements. Furthermore, as used herein, the terms “substantially,” “approximately,” or “about” generally mean within a value or range that would be expected by one of ordinary skill in the art (e.g., within 10%, 5%, 1%, or 0.5% of a given value or range). Alternatively, the terms “substantially,” “approximately,” or “about” mean within the acceptable standard error of the average value considered by one of ordinary skill in the art. One of ordinary skill in the art should understand that acceptable standard errors can vary depending on the technique. Except in operational / working examples or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein (e.g., numerical ranges, quantities, values, and percentages of material quantities, durations, temperatures, operating conditions, quantity ratios, and the like) should be understood to be modified by the terms “substantially,” “approximately,” or “about” in all instances. Therefore, unless otherwise indicated, the numerical parameters set forth in this disclosure and the appended claims are approximate values ​​that may vary as desired. Finally, each numerical parameter should be interpreted at least in light of the reported significant digits and by applying common rounding techniques. Ranges herein may be expressed as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints.

[0016] Figure 1 This is a flowchart of a method 100 for manufacturing an integrated circuit apparatus 20 according to some embodiments of the present invention. Figures 2A to 2N This is a cross-sectional view of an intermediate stage of a method 100 for manufacturing an integrated circuit apparatus 20 according to some embodiments of the present invention. In the following discussion, Figures 2A to 2N The manufacturing stage reference shown in the document Figure 1 The process steps shown in the diagram will be discussed. It should be understood that additional steps may be added. Figure 1 Some of the steps provided before, during, and after the steps shown in the diagram and described below may be replaced or eliminated in additional embodiments of method 100. The order of the steps may be changed.

[0017] refer to Figure 2A ,according to Figure 1 In step 102, one or more semiconductor devices 202 are formed in or on substrate 204. Substrate 204 may be a semiconductor substrate. In some embodiments, substrate 204 may be a silicon substrate. Alternatively, substrate 204 may include: another elemental semiconductor, such as germanium; a compound semiconductor comprising silicon carbide; an alloy semiconductor comprising silicon germanium; or a combination thereof.

[0018] Semiconductor device 202 may be formed during a front-end process (FEOL). Semiconductor device 202 may include (but is not limited to) active devices (e.g., transistors) and / or passive devices (e.g., diodes, resistors, or capacitors). Various processes are performed to form semiconductor device 202, such as deposition, etching, implantation, photolithography, annealing, and / or other applicable processes.

[0019] Still referencing Figure 2A ,according to Figure 1 In step 104, a first dielectric stack 210 is formed over the semiconductor device 202 and the substrate 204. The first dielectric stack 210 includes a series of first etch stop layers 212 and first isolation layers 214 alternately stacked on top of each other. For example, the first dielectric stack 210 may include two first etch stop layers 212A and 212B interleaved with two first isolation layers 214A and 214B. Figure 2A As shown, the first etch stop layer 212A is in contact with the upper surface 2042 of the substrate 204, and the first isolation layer 214A, the first etch stop layer 212B, and the first isolation layer 214B are sequentially disposed on the first etch stop layer 212A. In some embodiments, the first etch stop layer 212A may have a thickness T1, the first isolation layer 214A may have a thickness T2 greater than the thickness T1, and the first isolation layer 214B may have a thickness T3 greater than the thickness T2. For example, the thickness T3 of the first isolation layer 214B is in the range of about 500 angstroms to about 10 micrometers (100 k angstroms).

[0020] The first etch stop layers 212A and 212B comprise a first material different from the second material used to form the first isolation layers 214A and 214B. Specifically, the first material may have a high etch selectivity relative to the second material, and therefore the first etch stop layers 212A and 212B may be used to stop the etching of the first isolation layers 214A and 214B, respectively. Examples of the first material include (but are not limited to) silicon nitride, silicon carbide, undoped silicon glass (USG), phosphosilicate glass (PSG), fluorinated silica glass (FSG), black diamond, low dielectric constant (low k) materials, very low dielectric constant (ELK) materials, or the like. Examples of the second material include (but are not limited to) silicon oxide (SiO2). XMaterials suitable for low dielectric constant or very low dielectric constant (ELK) conditions include silicon dioxide (SiO2), silicon nitride, undoped silicon glass (USG), phosphosilicate glass (PSG), fluorinated silica glass (FSG), black diamond, and other materials suitable for low dielectric constant or very low dielectric constant (ELK) conditions and / or combinations thereof. The first etch stop layers 212A and 212B and the first isolation layers 214A and 214B can be formed by any suitable process, and suitability depends on the materials used. Examples of processes for depositing the first etch stop layers 212A and 212B and the first isolation layers 214A and 214B include spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other applicable processes. In some embodiments, the first isolation layers 214A and / or 214B can be planarized, for example, by a chemical mechanical polishing (CMP) operation to have a flat top surface.

[0021] After the dielectric stack 210 is fully formed, a first patterned mask layer 310 is formed over the first isolation layer 214B, wherein the first patterned mask layer 310 includes a plurality of first openings 312. A portion of the first isolation layer 214B is exposed through the first openings 312. In some embodiments, although in Figure 2A The diagram illustrates two first openings 312, but this number of first openings 312 in the first patterned mask layer 310 is not intended to be limited. For example, the first patterned mask layer 310 may contain only one first opening 312. The shape of the first opening 312 may be adjusted as needed. In some embodiments, the first patterned mask layer 310 may contain a photoresist, and the first opening 312 may be formed by a photolithography operation.

[0022] refer to Figures 2B to 2D ,according to Figure 1 In step 106, a first interconnect structure 220 is formed over the semiconductor device 202. After the first patterned mask layer 310 is formed, a first etching operation is performed to etch the first dielectric stack 210 through the first opening 312, such that one or more first vias 216 are formed in the first dielectric stack 210. Figure 2B As shown, the first dielectric stack 210 is etched until one or more portions of the semiconductor device 202 are exposed. In some embodiments, the first dielectric stack 210 is anisotropically etched by a plasma-based etching process (e.g., reactive ion etching (RIE) or similar). A first patterned mask layer 310 is used to confine the high-energy plasma etching to the desired pattern of the first via 216.

[0023] After the first via 216 is formed, the first patterned mask layer 310 is removed during, for example, ashing and / or wet stripping. Subsequently, a second patterned mask layer 320 is formed on the first dielectric stack 210 to cover a portion of the first insulating layer 214B. The second patterned mask layer 320 includes one or more second openings 322 connected to the first via 216.

[0024] exist Figure 2C In this process, a second etching operation is performed to etch the first isolation layer 214B to form one or more first trenches 218 in the first isolation layer 214B. The second etching operation stops at the first etch stop layer 212B. In some embodiments, the first isolation layer 214B is etched by an anisotropic etching process, such as a RIE process. In some embodiments, the first dielectric stack 210 is patterned using a dual damascene process, and the dual damascene process is, for example, a via-to-trench (VFTL) method.

[0025] After the second etching operation is performed, the second patterned mask layer 320 is removed. Next, a conductive material is provided to fill the first via 216 and the first trench 218, as shown below. Figure 2D As shown in the figure. In some embodiments, a conductive material is deposited and forms a first interconnect structure 220 electrically coupled to the semiconductor device 202. Examples of conductive materials include (but are not limited to) tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), aluminum-copper alloy (AlCu), aluminum-copper-silicon alloy, and the like. The conductive material can be formed or deposited by an electrochemical plating process, a CVD process, a PVD process, an ALD process, or other applicable deposition operations. After the conductive material fills or deposits in the first via 216 and the first trench 218, excess portions of the conductive material are removed to expose the top surface 215 of the first isolation layer 214B. Excess portions of the conductive material can be removed by a CMP operation.

[0026] In some embodiments, the first interconnect structure 220 may include one or more first conductive metals 224 surrounded by a first isolation layer 214B and a plurality of first channels 222 sandwiched between the first conductive metals 224 and the semiconductor device 202. The first channels 222 connect the semiconductor device 202 to the first conductive metals 224 and are surrounded by first etch stop layers 212A and 212B and the first isolation layer 214A.

[0027] When the conductive metal contains copper, the first interconnect structure 220 may further include a thin adhesive film (not shown) disposed between the first interconnect structure 220 and the semiconductor device 202 and between the first interconnect structure 220 and the first dielectric stack 210 to prevent copper from diffusing into the first dielectric stack 210. The adhesive film may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, or the like may also be used. The adhesive film is conformally deposited on the first isolation layer 214B and in the first via 216 and the first trench 218 prior to the deposition of the conductive material. After the conductive material is deposited, a CMP operation is performed to remove excess portions of the conductive material and the adhesive film from the top surface 215 of the first isolation layer 214B. The adhesive film may be deposited at a substantially uniform thickness using acceptable deposition operations such as CVD, PVD, ALD, or the like.

[0028] In some embodiments, an additional first dielectric stack 210 and a first interconnect structure 220 are formed over the substrate 204 to be electrically coupled to the semiconductor device 202. Reference Figure 2E Five layers of first interconnect structure 220 are shown above semiconductor device 202, but the actual number of first interconnect structures 220 is not limited to this.

[0029] refer to Figure 2F ,according to Figure 1 In step 108, a second dielectric stack 230 and a second interconnect structure 240 are formed over the first dielectric stack 210 and the first interconnect structure 220. The second dielectric stack 230 includes a series of second etch stop layers 232 and second isolation layers 234 deposited alternately with the second etch stop layers 232. For example, the second dielectric stack 230 may include two second etch stop layers 232A and 232B and two second isolation layers 234A and 234B.

[0030] The second etch stop layers 232A and 232B may include a first material for forming the first etch stop layers 212A and 212B, and the second isolation layers 234A and 234B may include a second material for forming the first isolation layers 214A and 214B. The second etch stop layers 232A and 232B may be formed in a manner similar to that used to form the first etch stop layers 212A and 212B, and the second isolation layers 234A and 234B may be formed in a manner similar to that used to form the first isolation layers 214A and 214B. In some embodiments, the second isolation layer 234A may have a thickness T4 greater than the thickness T3 of the first isolation layer 214B, and the second isolation layer 234B may have a thickness T5 greater than the thickness T4 of the second isolation layer 234A. For example, the thickness T5 of the second isolation layer 234B is in the range of about 1500 angstroms to about 10 micrometers (100 k angstroms).

[0031] Forming the second interconnect structure 240 may include a dual damascene process, comprising: forming a second via 236 in the second dielectric stack 230 and forming a second trench 238 in the second isolation layer 234B; depositing a conductive material in the second via 236 and the second trench 238; and then performing planarization, such as a CMP operation, to remove excess conductive material above the second isolation layer 234B. Thus, the top surface 246 of the conductive material is flush with the upper surface 235 of the second isolation layer 234B.

[0032] The second interconnect structure 240 includes a plurality of second channels 242 and one or more second conductive metals 244 connected to the second channels 242. The second channels 242 are sandwiched between the second conductive metals 244 and the uppermost first conductive metal 224 (i.e., the first conductive metal 224 furthest from the substrate 204). Figure 2F In this configuration, the second conductive metal 244 is surrounded by the second isolation layer 234B, and the second via 242 is surrounded by the second etch stop layers 232A and 232B and the second isolation layer 234A. In some embodiments, the second interconnect structure 240 may be formed of the same material as the first interconnect structure 220. The second interconnect structure 240 may be formed in a manner similar to that used to form the first interconnect structure 220.

[0033] Method 100 then proceeds to step 110, wherein an insulating film 200 is formed, as follows: Figure 2G and Figure 2H As shown in the figure. The insulating film 200 comprises a third material different from the first material of the first etch stop layers 212A and 212B. In some embodiments, the insulating film 200 comprises a metal oxide material, such as tungsten oxide (W). x O y ), copper oxide (Cu) x O y ), aluminum oxide (Al) x O y ), aluminum dioxide copper (Al) x Cu y O z Nickel oxide (Ni) x O y (e.g., but other dielectric materials can also be used.)

[0034] refer to Figure 2GThe surface region of the second conductive metal 244 is oxidized to form an insulating film 200. In this manner, the insulating film 200 comprises an oxide of the material of the second conductive metal 244, and from a top view, the insulating film 200 may have a pattern identical to the pattern of the second conductive metal 244. The insulating film 200 includes an upper surface 2002 and a lower surface 2004 opposite to the upper surface 2002. The lower surface 2004 of the insulating film 200 and the upper surface 235 of the second insulating layer 234B are located at different vertical levels, therefore the lower portion of the insulating film 200 is surrounded by the second insulating layer 234B. In some embodiments, the upper surface 235 of the second insulating layer 234B is located between the lower surface 2004 and the upper surface 2002 of the insulating film 200 in a cross-sectional view.

[0035] The oxidation of the second conductive metal 244 may include a baking operation in an oxygen atmosphere or a plasma treatment including an O2 plasma operation. In some embodiments, the oxidation is performed at a temperature greater than about 200°C.

[0036] refer to Figure 2H In some embodiments, the execution is different Figure 2G Alternative steps to the formation of the insulating film 200 shown in the embodiments. In these embodiments, the insulating film 200 is deposited on the second conductive metal 244. In these embodiments, the insulating film 200 may be formed of a material different from that of the second conductive metal 244. Additionally, the deposited insulating film 200 may have a lower surface 2006 flush with the upper surface 235 of the second insulating layer 234B. In some embodiments, the insulating film 200 may be formed by conformally depositing a dielectric layer on the second insulating layer 234B and the second conductive metal 244 and patterning the dielectric layer using a mask layer having a pattern identical to that of the second conductive metal 244.

[0037] refer to Figure 2I ,according to Figure 1In step 112, a third dielectric stack 250 is formed over the second dielectric stack 230 and the insulating film 200. The third dielectric stack 250 includes a third etch stop layer 252 and third isolation layers 254 interleaved with the third etch stop layer 252. In some embodiments, the third dielectric stack 250 contains two third etch stop layers 252A and 252B and two third isolation layers 254A and 254B. In some embodiments, the third etch stop layer 252A is conformally deposited to cover the insulating film 200 and the second dielectric stack 230, and the third isolation layer 254A may have a substantially flat upper surface. In some embodiments, the third etch stop layer 252A is made of a material different from that of the insulating film 200. The third isolation layer 254B may have a thickness T7 in the range of 1500 angstroms to 100 k angstroms, and the third isolation layer 254A may have a thickness T6 greater than the thickness T5 of the second isolation layer 234B and less than the thickness T7 of the third isolation layer 254B. The third etch stop layers 252A and 252B may be formed in a manner similar to that used to form the first etch stop layers 212A and 212B, and may be formed of the same material used to form the first etch stop layers 212A and 212B. The third isolation layers 254A and 254B may be formed in a manner similar to that used to form the first isolation layers 214A and 214B, and may be formed of the same material used to form the first isolation layers 214A and 214B.

[0038] After the third dielectric stack 250 is formed, a third patterned mask layer 330 is formed on the third isolation layer 254B. The third patterned mask layer 330 is used to pattern the third dielectric stack 250 and includes one or more third openings 332 that expose one or more portions of the third isolation layer 254B.

[0039] refer to Figures 2J to 2L A third etch operation is performed to form one or more deep holes 258 extending through the third dielectric stack 250 and the insulating film 200. In some embodiments, the third etch operation may include multiple sub-etching steps with different etch formulations to sequentially etch through the third isolation layer 254B, the third etch stop layer 252B, the third isolation layer 254A, the third etch stop layer 252A and the insulating film 200, while providing a desired etch rate and desired etch selectivity.

[0040] refer to Figure 2J ,according to Figure 1 Step 114 involves removing portions of the third isolation layer 254B, the third etch stop layer 252B, and the third isolation layer 254A that are not covered by the third patterned mask layer 330. Consequently, one or more third vias 256 are formed in the third dielectric stack 250. One or more portions of the third etch stop layer 252A are exposed through the third vias 256. (See reference...) Figure 2K A portion of the third etch stop layer 252A exposed through the third via 256 is removed so that the third via 256 extends through the third etch stop layer 252A, thereby exposing one or more portions of the insulating film 200.

[0041] refer to Figure 2L ,according to Figure 1 In step 116, the insulating film 200 is etched to allow the third via 256 to extend through the insulating film 200. Thus, one or more deep holes 258 are formed. The third isolation layer 254B, the third etch stop layer 252B, and the third isolation layer 254A are anisotropically etched by a plasma-based etching process, such as a RIE process or the like.

[0042] The first via 216 in the first dielectric stack 210 has a first aspect ratio, the second via 236 in the second dielectric stack 230 has a second aspect ratio, and the third via 256 in the third dielectric stack 250 has a third aspect ratio. The third aspect ratio is not only greater than the second aspect ratio but also greater than the first aspect ratio because the third insulating layers 254A and 254B have a thickness greater than the thickness of the second insulating layers 234A and 234B.

[0043] During the plasma-based etching process, reactive ions are generated and accelerated toward the surface to be treated to achieve highly directional removal of the component using incident ions to provide high-speed removal of the component, resulting in a substantially vertically oriented removal component combined with the chemical interactions of the reactive ions. In some embodiments, a suitable precursor material is added to the plasma etching gas to form a polymer compound that significantly reduces the lateral etching rate while substantially not affecting the vertical etching process at the corresponding etching front. Due to the very complex conditions within the plasma etching gas, negative ions accumulate in the second interconnect structure 240, while positive charges accumulate in the lower portion of the third via 256, thereby accumulating a vertical potential difference. Therefore, due to the accumulation of negative and positive charges, a local potential difference is generated near the bottom of the corresponding via.

[0044] The effect of a significant potential difference is particularly pronounced when the dielectric material is thinned from above. Therefore, when the dielectric material reaches a certain thickness, the potential difference can become large enough to cause dielectric breakdown of the remaining dielectric material, i.e., an uncontrolled discharge, also known as an arcing event. In this case, a large number of particles can be generated, for example, in the form of burning dielectric material, burning conductive material, or the like, which are scattered over a wide area of ​​the semiconductor substrate, thereby increasing the contamination range, which can then lead to significant yield losses or at least degrade the reliability of the completed integrated circuit device.

[0045] Plasma intensity depends on, for example, the type of etchant or gas, pressure, temperature, and radio frequency (RF) power used by the RF generator. In some embodiments, the third isolation layers 254A and 254B are etched with an RF power higher than 1000W. High RF power can cause more ions to accumulate on the lower portion of the third via 256.

[0046] In some embodiments, the effective capacitance around the second interconnect structure 240 and the third via 256 can be reduced by introducing an insulating film 200. The insulating film 200, located between the second interconnect structure 240 and the third dielectric stack 250, can share a portion of the capacitance used to reduce the equivalent capacitance between the second interconnect structure 240 and the surface etched in the third via 256 during the plasma etching process, thereby reducing the unwanted high potential difference buildup around the third via 256. Therefore, due to the reduction in high potential difference, the probability of arcing events can be significantly reduced or substantially eliminated.

[0047] Following the third etching operation, a removal operation, such as stripping or ozone ashing, is performed to remove the third patterned mask layer 330. Subsequently, a fourth patterned mask layer 340 is formed on a portion of the third isolation layer 254B. The fourth patterned mask layer 340 includes one or more fourth openings 342 connected to the deep via 258.

[0048] refer to Figure 2M ,according to Figure 1 In step 118, a fourth etching operation is performed to form one or more third trenches 259 in the third isolation layer 254B. The fourth etching operation is performed to selectively remove material from the third isolation layer 254B relative to the material of the third etch stop layer 252B. In some embodiments, the third trench 259 has a depth D greater than the thickness T of the first interconnect structure 220. In some embodiments, the third trench 259 has a width W1 greater than the width W2 of the deep hole 258.

[0049] After the fourth etch operation is performed, the fourth patterned mask layer 340 is removed. (Reference) Figure 2N ,according to Figure 1 In step 120, conductive material is provided to fill the deep via 258 and the third trench 259. In some embodiments, the conductive material is deposited and forms a third interconnect structure 260 that is physically and electrically connected to the second interconnect structure 240. After the conductive material is filled or deposited in the deep via 258 and the third trench 259, excess portions of the conductive material are removed to expose the top surface 255 of the third isolation layer 254B. Excess portions of the conductive material can be removed by a CMP operation. Thus, the integrated circuit device 20 is fully formed.

[0050] Figure 3 This is a flowchart of a method 400 for manufacturing an integrated circuit device 50 according to some embodiments of the present invention. Figures 4A to 4P This is a cross-sectional view of an intermediate stage of a method 400 for manufacturing an integrated circuit apparatus 50 according to some embodiments of the present invention. In the following discussion, Figures 4A to 4P The manufacturing stage reference shown in the document Figure 3 The process steps shown in the diagram will be discussed. It should be understood that additional steps may be added. Figure 3 Some of the steps provided before, during, and after the steps shown in the diagram and described below may be replaced or eliminated in additional embodiments of method 400. The order of the steps may be changed.

[0051] refer to Figure 4A ,according to Figure 3 Step 402 involves providing a first die 510. The first die 510 includes a first substrate 512, a first dielectric stack 514 disposed above the first substrate 512, and a plurality of first interconnect structures 516 surrounded by the first dielectric stack 514. The first substrate 512 may be or contain a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., doped with p-type or n-type dopants) or undoped. Various semiconductor devices may be located on or within the first substrate 512. For example, semiconductor devices may include FETs, diodes, capacitors, inductors, and other devices. For example, semiconductor devices may be entirely formed within the first substrate 512, partially formed in the first substrate 512 and partially formed in the first dielectric stack 514, or entirely formed in the first dielectric stack 514. The first interconnect structures 516 above the first substrate 512 are electrically coupled to the semiconductor devices to form an integrated circuit. The integrated circuit may be any circuit, such as an application-specific integrated circuit (ASIC), a processor, a memory, or another circuit.

[0052] refer to Figure 4B ,according to Figure 3 In step 404, a second substrate 522 is provided and a conductive pillar 530 is formed in the second substrate 522. The conductive pillar 530 is formed in the second substrate 522 by etching the second substrate 522 to form a groove 524 in the second substrate 522 and depositing conductive material in the groove 524. In some embodiments, a CMP operation is performed to remove excess portions of the conductive material from the upper surface 523 of the second substrate 522. The conductive pillar 530 may be made of at least one material (e.g., Cu, Al, AlCu, AlSiCu, AlSi, Co, Ni, or the like).

[0053] After the conductive pillars 530 are formed, an interconnect dielectric 540 is deposited to completely cover the second substrate 522 and the conductive pillars 530, such as Figure 4CAs shown in the figure. The lower interconnect dielectric 540 may, for example, include a low-k dielectric having a k value of less than about 4.0 (e.g., about 2.0 or less). The lower interconnect dielectric 540 may be deposited using a CVD operation, a spin coating operation, or another deposition technique. In some embodiments, a CMP operation or another planarization operation may be performed to planarize the top surface of the lower interconnect dielectric 540.

[0054] Next, a first etching operation is performed to remove a portion of the lower interconnect dielectric 540 and form a plurality of openings 542 through the lower interconnect dielectric 540, wherein the conductive pillars 530 are exposed through one of the openings 542. The first etching operation may be a plasma-based etching process, such as a RIE process. After the openings 542 are formed, according to Figure 3 In step 406, conductive material is deposited in the opening 542 to form a first wiring layer 550. The first wiring layer 550 is electrically coupled to the conductive pillar 530. In some embodiments, the first wiring layer 550 may be formed of the same material as the material used to form the conductive pillar 530. The first wiring layer 550 may be formed in a manner similar to that used to form the conductive pillar 530.

[0055] refer to Figure 4D and Figure 4E ,according to Figure 3 In step 408, an insulating film 500 is formed on one or more portions of the first wiring layer 550. In some embodiments, the insulating film 500 comprises a metal oxide material, such as tungsten oxide (W). x O y ), copper oxide (Cu) x O y ), aluminum oxide (Al) x O y ), aluminum dioxide copper (Al) x Cu y O z Nickel oxide (Ni) x O y (e.g., but other dielectric materials can also be used.)

[0056] In some embodiments, reference Figure 4D The insulating film 500 is formed by oxidizing one or more portions of the first wiring layer 550, such that the insulating film 500 and the first wiring layer 550 can have the same material. In other words, the insulating film 500 and the first wiring layer 550 contain common elements. The insulating film 500 includes an upper surface 5002 and a lower surface 5004 opposite to the upper surface. The lower surface 5004 of the insulating film 500 and the upper surface 541 of the lower interconnect dielectric 540 are located at different vertical levels. Furthermore, the upper surface 5002 of the insulating film 500 and the upper surface 541 of the lower interconnect dielectric 540 are located at different vertical levels. (Reference) Figure 4E In different Figure 4D In an alternative step shown, the insulating film 500 is formed by depositing dielectric material on the lower interconnect dielectric 540 and the first wiring layer 550 and performing a patterning operation to remove portions of the dielectric material covering portions of the lower interconnect dielectric 540 and the first wiring layer 550. Figure 4E The insulating film 500 includes an upper surface 5002 and a lower surface 5004 opposite to the upper surface, and the lower surface 5004 is flush with the upper surface of the lower interconnect dielectric 540.

[0057] refer to Figure 4F ,according to Figure 3 In step 410, a second dielectric stack 610 is formed on the lower interconnect dielectric 540, the first wiring layer 550, and the insulating film 500. For example, the second dielectric stack 610 may include two etch stop layers 612A and 612B interleaved with the two isolation layers 614A and 614B. Figure 4F As shown, the etch stop layer 612A is in contact with the lower interconnect dielectric 540, the first wiring layer 550, and the insulating film 500. The etch stop layer 612A has a material different from that of the insulating film 500. In some embodiments, the etch stop layer 612A is a conformal layer covering the lower interconnect dielectric 540, the first wiring layer 550, and the insulating film 500.

[0058] Isolation layer 614A, etch stop layer 612B, and isolation layer 614B are sequentially disposed on etch stop layer 612A. In some embodiments, etch stop layers 612A and 612B may have a thickness T8, isolation layer 614A may have a thickness T9 greater than the thickness T8, and isolation layer 614B may have a thickness T10 greater than the thickness T9. For example, the thickness T9 of isolation layer 614A and the thickness T10 of isolation layer 614B are in the range of about 500 angstroms to about 100 k angstroms.

[0059] refer to Figure 4G and Figure 4H ,according to Figure 3 In step 412, a second interconnect structure 620 is formed in the second dielectric stack 610. Forming the second interconnect structure 620 may include a dual damascene process, which includes: forming one or more vias 616 in the second dielectric stack 610 and forming one or more trenches 618 in the isolation layer 614B; depositing conductive material in the vias 616 and trenches 618; and then performing planarization, such as a CMP operation, to cause the top surface of the conductive material to be flush with the top surface of the isolation layer 614B.

[0060] An additional second dielectric stack 610 and an additional second interconnect structure 620 may be formed over the second substrate 522 to electrically couple the semiconductor device. Reference Figure 4IFive layers of second interconnect structures 620 are shown above the second substrate 522, but the actual number of second interconnect structures 620 is not limited to this.

[0061] Subsequently, a patterned mask layer 700 is formed on portions of the uppermost second dielectric stack 610 and the uppermost second interconnect structure 620. The patterned mask layer 700 includes one or more openings 702 that expose one or more regions of the uppermost isolation layer 614B. In some embodiments, the openings 702 may be disposed above the insulating film 500 or above the conductive pillars 530.

[0062] refer to Figures 4J to 4L A second etching operation is performed to form one or more through dielectric vias 640 through the second dielectric stack 610 and the insulating film 500. In some embodiments, the second etching operation may include multiple sub-etching steps with different etching formulations to sequentially etch through the isolation layer 614B, the etch stop layer 612B, the isolation layer 614A, the etch stop layer 612A, and the insulating film 500.

[0063] refer to Figure 4J ,according to Figure 3 In step 414, one or more deep vias 630 are formed in the second dielectric stack 610. In some embodiments, one or more portions of the lowermost etch stop layer 612A located directly above the insulating film 500 and the conductive pillars 530 are exposed through the deep vias 630. (See reference...) Figure 4K A portion of the lowest etch stop layer 612A exposed through the deep hole 630 is removed so that the deep hole 630 extends through the lowest etch stop layer 612A, thereby exposing a portion of the insulating film 500.

[0064] refer to Figure 4L ,according to Figure 3 In step 416, the insulating film 500 is etched to extend the deep via 630 through the insulating film 500. This forms one or more through-dielectric vias 640. In some embodiments, the through-dielectric via 640 has a depth D greater than the thickness T of the second interconnect structure 620. After the second etching operation, the patterned mask layer 700 is removed in, for example, an ashing and / or wet stripping operation.

[0065] refer to Figure 4M ,according to Figure 3 In step 418, a conductive material is provided to fill the through-dielectric via 640. In some embodiments, the conductive material is deposited and forms a through-dielectric via 650 that is physically and electrically connected to the first wiring layer 550. In some embodiments, excess portions of the conductive material are removed to expose the top surface of the uppermost insulating layer 614B. Excess portions of the conductive material may be removed by a CMP operation.

[0066] refer to Figure 4NSemiconductor device 660 may be formed on second dielectric stack 610 and connected to through dielectric path 650 and second interconnect structure 620. In some embodiments, semiconductor device 660 may be a light-emitting device. Semiconductor device 660 may include (but is not limited to) light-emitting elements, transmission elements, modulation elements, signal processing elements, switching circuits, amplifiers, input / output couplers, and photosensing / detection circuits. Various processes are performed to form semiconductor device 660, such as deposition, etching, implantation, photolithography, annealing, and / or other applicable processes.

[0067] refer to Figure 4O ,according to Figure 3 In step 420, the second substrate 522 is thinned to expose the conductive pillars 530. Thus, the second die 520 is fully formed. In some embodiments, the second substrate 522 is thinned to reduce its overall thickness. The thinning of the second substrate 522 can be accomplished by mechanical polishing, CMP, wet etching, atmospheric downstream plasma (ADP), dry chemical etching (DCE), a combination of the foregoing processes, or any other suitable thinning method(s).

[0068] refer to Figure 4P ,according to Figure 3 In step 422, a bonding operation is performed to bond the second die 520 to the first die 510. Thus, the integrated circuit device 50 is formed. After the bonding operation, the second substrate 522 is in contact with a portion of the first dielectric stack 514 and the (uppermost) first interconnect structure 516, and is connected to the (uppermost) first interconnect structure 516 through the dielectric path 650.

[0069] According to some embodiments of the present invention, a method of manufacturing an integrated circuit device includes: forming a semiconductor device on a substrate; forming a first interconnect structure above the semiconductor device and a dielectric layer for surrounding the first interconnect structure, wherein the first interconnect structure includes a first conductive metal electrically coupled to the semiconductor device through a plurality of first channels; and forming a second interconnect structure above the first conductive metal, wherein forming the second interconnect structure includes: forming an insulating film above the first conductive metal; depositing an etch stop layer above the insulating film, wherein the etch stop layer and the insulating film comprise different materials; depositing a dielectric layer above the etch stop layer; performing a first etch operation to form a hole penetrating the dielectric layer to expose the etch stop layer; and causing the hole to extend through the etch stop layer and the insulating film and stop at the first conductive metal.

[0070] According to some embodiments of the present invention, a method of manufacturing an integrated circuit device includes: providing a first die comprising a first substrate, a first interconnect structure above the first substrate, and a first dielectric layer for surrounding the first interconnect structure; providing a second die comprising a second substrate, a second interconnect structure above the second substrate, a second dielectric layer for surrounding the second interconnect structure, an insulating film on the second interconnect structure, an etch stop layer above the second dielectric layer and the insulating film, and an isolation layer above the etch stop layer; forming a hole penetrating the isolation layer to expose the etch stop layer; causing the hole to extend through the etch stop layer and the insulating film; and depositing a conductive material in the hole to form a conductive path electrically coupled to the second interconnect structure.

[0071] According to some embodiments of the present invention, an integrated circuit device includes: a substrate comprising a plurality of semiconductor devices; an interconnect structure electrically coupled to the substrate and comprising: a conductive metal electrically coupled to the substrate; an insulating film located on the conductive metal, wherein the insulating film and the conductive metal include a common element; an etch stop layer located above the insulating film; an isolation layer located above the etch stop layer; and a conductive path penetrating the isolation layer, the etch stop layer, and the insulating film and electrically coupled to the conductive metal.

[0072] The foregoing summary of features of several embodiments enables those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0073] Symbol Explanation

[0074] 20: Integrated circuit devices

[0075] 50: Integrated circuit devices

[0076] 100: Method

[0077] 102: Steps

[0078] 104: Steps

[0079] 106: Steps

[0080] 108: Steps

[0081] 110: Steps

[0082] 112: Steps

[0083] 114: Steps

[0084] 116: Steps

[0085] 118: Steps

[0086] 120: Steps

[0087] 200: Insulating film

[0088] 202: Semiconductor Devices

[0089] 204: Substrate

[0090] 210: First dielectric stack

[0091] 212: First etch stop layer

[0092] 212A: First etch stop layer

[0093] 212B: First etch stop layer

[0094] 214: First isolation layer

[0095] 214A: First isolation layer

[0096] 214B: First isolation layer

[0097] 215: Top surface

[0098] 216: First through hole

[0099] 218: First trench

[0100] 220: First interconnect structure

[0101] 222: First Pathway

[0102] 224: First conductive metal

[0103] 230: Second dielectric stack

[0104] 232: Second etch stop layer

[0105] 232A: Second etch stop layer

[0106] 232B: Second etch stop layer

[0107] 234: Second isolation layer

[0108] 234A: Second isolation layer

[0109] 234B: Second isolation layer

[0110] 235: Upper surface

[0111] 236: Second through hole

[0112] 238: Second trench

[0113] 240: Second interconnect structure

[0114] 242: Second Pathway

[0115] 244: Second conductive metal

[0116] 246: Top surface

[0117] 250: Third dielectric stack

[0118] 252: Third Etching Stop Layer

[0119] 252A: Third Etching Stop Layer

[0120] 252B: Third Etching Stop Layer

[0121] 254: Third Isolation Layer

[0122] 254A: Third isolation layer

[0123] 254B: Third isolation layer

[0124] 255: Top surface

[0125] 256: Third through hole

[0126] 258:Deep hole

[0127] 259: Third trench

[0128] 260: Third interconnect structure

[0129] 310: First patterned mask layer

[0130] 312: First Opening

[0131] 320: Second patterned mask layer

[0132] 322: Second opening

[0133] 330: Third patterned mask layer

[0134] 332: Third opening

[0135] 340: Fourth Patterned Mask Layer

[0136] 342: Fourth opening

[0137] 400: Method

[0138] 402: Steps

[0139] 404: Steps

[0140] 406: Steps

[0141] 408: Steps

[0142] 410: Steps

[0143] 412: Steps

[0144] 414: Steps

[0145] 416: Steps

[0146] 418: Steps

[0147] 420: Steps

[0148] 422: Steps

[0149] 500: Insulating film

[0150] 510: The First Nude Film

[0151] 512: First substrate

[0152] 514: First dielectric stack

[0153] 516: First interconnect structure

[0154] 520: The Second Nude Film

[0155] 522: Second substrate

[0156] 523: Upper surface

[0157] 524: Groove

[0158] 530: Conductive post

[0159] 540: Under-interconnect dielectric

[0160] 541: Upper surface

[0161] 542: Opening

[0162] 550: First wiring layer

[0163] 610: Second dielectric stack

[0164] 612A: Etching Stop Layer

[0165] 612B: Etching Stop Layer

[0166] 614A: Isolation layer

[0167] 614B: Isolation Layer

[0168] 616: Through hole

[0169] 618: Trench

[0170] 620: Second interconnect structure

[0171] 630:Deep hole

[0172] 640: Through-dielectric via

[0173] 650: Through dielectric path

[0174] 660: Semiconductor Device

[0175] 700: Patterned mask layer

[0176] 702: Opening

[0177] 2002: Upper Surface

[0178] 2004: Lower surface

[0179] 2006: Lower Surface

[0180] 2042: Upper surface

[0181] 5002: Upper surface

[0182] 5004: Lower surface

[0183] D: Depth

[0184] T: Thickness

[0185] T1: Thickness

[0186] T2: Thickness

[0187] T3: Thickness

[0188] T4: Thickness

[0189] T5: Thickness

[0190] T6: Thickness

[0191] T7: Thickness

[0192] T8: Thickness

[0193] T9: Thickness

[0194] T10: Thickness

[0195] W1: Width

[0196] W2: Width.

Claims

1. An integrated circuit device, characterized in that... It includes: Substrate, which includes semiconductor devices; A first interconnect structure is disposed above the semiconductor device, wherein the first interconnect structure includes: Multiple first pathways; and A first conductive metal is electrically coupled to the semiconductor device through the first passage; A dielectric layer that surrounds the first interconnect structure; An insulating film is disposed above the first conductive metal; and A second interconnect structure penetrates the insulating film and is electrically coupled to the first conductive metal.

2. The integrated circuit device according to claim 1, characterized in that... The insulating film and the first conductive metal have substantially the same pattern.

3. The integrated circuit device according to claim 1, characterized in that... The upper surface of the dielectric layer is located between the lower surface of the insulating film and the upper surface of the insulating film in the cross-sectional view.

4. The integrated circuit device according to claim 1, characterized in that... When viewed in cross-section, the lower surface of the insulating film is flush with the upper surface of the dielectric layer.

5. An integrated circuit device, characterized in that... It includes: The first nude film, which includes: First substrate; A first interconnect structure is located above the first substrate; and A first dielectric layer is used to surround the first interconnect structure; The second nude film includes: Second substrate; A second interconnect structure is located above the second substrate; A second dielectric layer is used to surround the second interconnect structure; An insulating film is located on the second interconnect structure; An etch stop layer is located above the second dielectric layer and the insulating film; and An isolation layer, which is located above the etch stop layer; and A conductive path that penetrates the insulating film, the etch stop layer, and the isolation layer and is electrically coupled to the second interconnect structure.

6. The integrated circuit device according to claim 5, characterized in that... The lower and upper surfaces of the insulating film and the upper surface of the second dielectric layer are located at different vertical levels.

7. The integrated circuit device according to claim 5, characterized in that... When viewed in cross-section, the lower surface of the insulating film is flush with the upper surface of the second dielectric layer.

8. An integrated circuit device, characterized in that... It includes: A substrate comprising multiple semiconductor devices; Interconnection structure electrically coupled to the substrate and comprising: A conductive metal electrically coupled to the substrate; An insulating film is located on the conductive metal, wherein the insulating film and the conductive metal comprise a common element; An etch stop layer is located above the insulating film; An isolation layer, which is located above the etch stop layer; and A conductive path that penetrates the isolation layer, the etch stop layer, and the insulating film and is electrically coupled to the conductive metal.

9. The integrated circuit device according to claim 8, characterized in that... The insulating film and the conductive metal have substantially the same pattern.

10. The integrated circuit device according to claim 8, characterized in that... The conductive metal has a thickness smaller than that of the conductive path.

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