Packaging structure with heat dissipation enclosure
By introducing heat dissipation barriers and thermal interface material layers into the chip packaging structure, the problem of poor heat dissipation in the chip packaging structure is solved, and a more efficient heat dissipation effect is achieved.
Patent Information
- Application Number
- CN202423312353.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing chip packaging structures have shortcomings in heat dissipation, especially in terms of poor heat dissipation in the horizontal direction and high thermal resistance in the vertical direction, resulting in poor heat dissipation.
The packaging structure with a heat dissipation enclosure includes a substrate, an enclosure body and support legs. The enclosure body has through holes and is filled with thermal interface material. The support legs are connected to the substrate and combined with the thermal interface material layer to reduce thermal resistance and enhance heat dissipation.
It retains a large heat dissipation area in the horizontal direction, while significantly reducing the thermal resistance in the vertical direction, thereby improving the heat dissipation efficiency of the chip and preventing short circuits or thermal failures caused by the overflow of thermal interface material.
Smart Images
Figure CN223899695U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to semiconductor packaging, and in particular to a packaging structure with a heat dissipation barrier. Background Technology
[0002] Conventional high-power CPUs are typically packaged in FC-BGA (Functionally Open-Frame GA) architecture. Heat is primarily dissipated through the top, and the system typically places a heatsink on top of the package to increase the heat dissipation area, then uses air cooling or liquid cooling to remove the heat. In FC-BGA packaging, a flat heatsink is usually added to the top for heat dissipation, or the chip is directly packaged as a bare die. When using a flat heatsink, the horizontal heat dissipation area is increased, and the chip is protected. However, due to the presence of the heatsink and the thermal interface material, there is a significant contact thermal resistance between the heatsink and the chip, leading to an increase in vertical thermal resistance.
[0003] While using bare die packaging reduces the vertical thermal resistance, it can easily damage the chip when assembling the system heatsink. In addition, the chip area is generally small, resulting in poor horizontal heat dissipation.
[0004] Therefore, this application provides a packaging structure to solve the existing chip heat dissipation problem. Utility Model Content
[0005] This invention provides a packaging structure with a heat dissipation barrier, which aims to solve the problem of poor heat dissipation in existing chips during the packaging process.
[0006] To achieve the above objectives, embodiments of this utility model provide an encapsulation structure with a heat dissipation barrier, comprising:
[0007] A substrate on which a chip is disposed, wherein the chip is connected to the substrate by a bump connection.
[0008] A heat dissipation enclosure includes an enclosure body and supporting legs. The enclosure body has through holes along its thickness direction. The enclosure body is attached to the upper surface of the chip. The through holes have the same shape as the chip, but the size of the through holes is smaller than the size of the chip. The through holes are coaxial with the chip. The supporting legs are disposed between the substrate and the enclosure body to support the enclosure body. An annular cavity is formed between the supporting legs and the chip.
[0009] The through-hole is filled with a first thermal interface material layer.
[0010] Preferably, a second thermal interface material layer is provided between the enclosure body and the upper surface of the chip, and the enclosure body and the chip are connected through the second thermal interface material layer.
[0011] Preferably, a third thermal interface material layer is provided between the support leg and the substrate, and the support leg and the substrate are connected through the third thermal interface material layer.
[0012] Preferably, the enclosure body and the supporting leg are integrally formed.
[0013] Preferably, the fence body is rectangular, the supporting leg is a rectangular frame, and the length and width of the fence body are equal to the length and width of the outer diameter of the supporting leg.
[0014] Preferably, the dimensions of the via include the length and width of the via, and the dimensions of the chip include the length and width of the chip, wherein the length of the via is less than the length of the chip, and the width of the via is less than the length of the chip.
[0015] Preferably, the difference between the length of the through hole and the length of the chip is the same as the difference between the width of the through hole and the width of the chip.
[0016] The above-mentioned solution of this utility model has the following beneficial effects:
[0017] This application combines the advantages of planar heat sink and bare die packaging, retaining the heat dissipation area in the horizontal direction while significantly reducing the contact thermal resistance in the vertical direction, enabling the heat generated by the chip to be quickly transferred to the top and sides, effectively improving the heat dissipation effect.
[0018] Other features and advantages of this invention will be described in detail in the following detailed description section. Attached Figure Description
[0019] Figure 1 This is a longitudinal sectional view of the present invention;
[0020] Figure 2 This is a top view of the present invention.
[0021] [Explanation of Labels in the Attached Image]
[0022] 100 - substrate, 200 - chip
[0023] 300-Heat dissipation enclosure, 310-Enclosure body, 320-Support leg, 311-Through hole, 321-Annular cavity, 330-First thermal interface material layer
[0024] 400 - Second thermal interface material layer
[0025] 500 - Third thermal interface material layer. Detailed Implementation
[0026] To make the technical problems, technical solutions and advantages of this utility model clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.
[0027] like Figure 1 and 2 As shown, an embodiment of this utility model provides a packaging structure with a heat dissipation barrier, including a substrate 100 and a heat dissipation barrier 300. A chip 200 is disposed on the substrate 100, and the chip 200 is connected to the substrate 100 via a bump connection. The substrate 100 provides support for the chip 200. The heat dissipation barrier 300 includes a barrier body 310 and support legs 320. A through-hole 311 is formed on the barrier body 310, extending through the barrier body 310 along its thickness direction. The barrier body 310 is fitted to the upper surface of the chip 200. The shape of the through-hole 311 is the same as that of the chip 200, but the size of the through-hole 311 is smaller than that of the chip 200. The through-hole 311 and the chip 200 are coaxially arranged in the horizontal direction. The aforementioned support legs 320 are disposed between the substrate 100 and the barrier body 310 to support the barrier body 310, forming an annular cavity 321 between the support legs 320 and the chip 200. The aforementioned through-hole 311 is filled with a first thermal interface material, and a first thermal interface material layer 330 is formed within the through-hole 311.
[0028] In this application, by creating a through-hole 311 on the enclosure body 310, the advantage of the planar heat sink with a large heat dissipation area in the horizontal direction is retained. Simultaneously, by providing the through-hole 311 on the enclosure body 310, with the through-hole 311 located directly above the chip 200 and filled with a first thermal interface material layer 330, the vertical junction thermal resistance is significantly reduced, allowing the heat generated by the chip 200 to be quickly transferred to the top and surrounding areas. Furthermore, in conventional packaging structures, heat dissipation in the central area is relatively difficult; however, by creating a through-hole 311 in the center of the enclosure body 310 in this application, the heat dissipation effect is significantly improved. In addition, the placement of the first thermal interface material layer 330 within the through-hole 311 can prevent short circuits or thermal failures caused by the overflow of the first thermal interface material layer 330. In addition, phase change thermal interface materials are solid at room temperature, but melt and become liquid when the chip 200 heats up. If there is no through hole 311 to restrict them, the first thermal interface material layer 330 will flow everywhere after melting, causing the first thermal interface material to be lost or even gone. This results in a large air gap inside the through hole 311, which greatly reduces the heat transfer performance and causes the chip 200 to overheat and fail.
[0029] Furthermore, a second thermal interface material layer 400 is provided between the upper surface of the enclosure body 310 and the chip 200, and the enclosure body 310 and the chip 200 are connected through the second thermal interface material layer 400. Preferably, the second thermal interface material layer 400 is disposed around the first thermal interface material layer 330.
[0030] Furthermore, a third thermal interface material layer 500 is provided between the support leg 320 and the substrate 100, and the support leg 320 and the substrate 100 are connected through the third thermal interface material layer 500.
[0031] Preferably, in this application, the enclosure body 310 and the support leg 320 are integrally formed.
[0032] In this application, the fence body 310 is rectangular, and the support leg 320 is a rectangular frame. The length and width of the fence body 310 are equal to the length and width of the outer diameter of the support leg 320.
[0033] The dimensions of the aforementioned via 311 include its length and width, and the dimensions of the chip 200 include its length and width. The length of the via 311 is less than the length of the chip 200, and the width of the via 311 is less than the length of the chip 200, such that the cross-sectional area of the via 311 is less than the cross-sectional area of the chip 200. Preferably, the difference between the length of the via 311 and the length of the chip 200 is the same as the difference between the width of the via 311 and the width of the chip 200.
[0034] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.
Claims
1. A packaging structure with a heat dissipation enclosure, characterized in that, include: A substrate (100) is provided with a chip (200), and the chip (200) is connected to the substrate (100) by a bump connection. A heat dissipation enclosure (300) includes an enclosure body (310) and a support leg (320). The enclosure body (310) has a through hole (311) along the thickness direction of the enclosure body (310). The enclosure body (310) is attached to the upper surface of the chip (200). The through hole (311) has the same shape as the chip (200). The size of the through hole (311) is smaller than the size of the chip (200). The through hole (311) is coaxial with the chip (200). The support leg (320) is disposed between the substrate (100) and the enclosure body (310) to support the enclosure body (310). An annular cavity (321) is formed between the support leg (320) and the chip (200). The through hole (311) is filled with a first thermal interface material layer (330).
2. The encapsulation structure with a heat dissipation barrier according to claim 1, characterized in that: A second thermal interface material layer (400) is provided between the upper surface of the enclosure body (310) and the chip (200), and the enclosure body (310) and the chip (200) are connected through the second thermal interface material layer (400).
3. The encapsulation structure with a heat dissipation barrier according to claim 1, characterized in that: A third thermal interface material layer (500) is provided between the support leg (320) and the substrate (100), and the support leg (320) and the substrate (100) are connected through the third thermal interface material layer (500).
4. The encapsulation structure with a heat dissipation barrier according to claim 1, characterized in that: The enclosure body (310) and the supporting leg (320) are integrally formed.
5. The encapsulation structure with a heat dissipation barrier according to claim 1, characterized in that: The enclosure body (310) is rectangular, and the support leg (320) is a rectangular frame. The length and width of the enclosure body (310) are equal to the length and width of the outer diameter of the support leg (320).
6. The encapsulation structure with a heat dissipation barrier according to claim 1, characterized in that: The dimensions of the via (311) include the length and width of the via (311), and the dimensions of the chip (200) include the length and width of the chip (200). The length of the via (311) is less than the length of the chip (200), and the width of the via (311) is less than the length of the chip (200).
7. The encapsulation structure with a heat dissipation barrier according to claim 6, characterized in that: The difference between the length of the through hole (311) and the length of the chip (200) is the same as the difference between the width of the through hole (311) and the width of the chip (200).