Semiconductor structure and semiconductor device
By placing a high thermal conductivity thermally conductive layer at the edge of the back of the chip in the semiconductor structure, the problem of insufficient heat dissipation capacity of the chip is solved, and faster heat conduction and better heat resistance are achieved.
Patent Information
- Application Number
- CN202520456402.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2035-03-14
AI Technical Summary
In existing technologies, semiconductor chips have poor heat dissipation capabilities, resulting in high-temperature areas concentrated in the center of the chip, which affects the chip's overcurrent resistance.
In semiconductor structures, a thermally conductive layer with a thermal conductivity higher than that of the substrate is placed at the edge of the back side of the chip, especially in the terminal area. The high thermal conductivity of the thermally conductive layer increases the rate of heat conduction from the center of the chip to the edge, reducing the accumulation of heat in the center of the chip.
By increasing the rate at which heat is conducted to the chip edges, heat accumulation in the chip center is reduced, thereby enhancing the chip's heat resistance and heat dissipation efficiency.
Smart Images
Figure CN223899700U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a semiconductor device. BACKGROUND
[0002] Silicon Carbide (SiC) as a kind of wide band gap semiconductor material, with its wide band gap, high critical electric field strength, high thermal conductivity and high saturation drift speed, has broad application prospect in high-voltage, high-power, high-temperature and high-frequency application fields.
[0003] In TO (Transistor Outlin, transistor outline) packaging or other non-double-sided soldering packaging, the heat in steady state will be mainly dissipated by the back plate and the heat sink of the chip. However, the cell area of the chip is in the center, which determines that the heat is conducted from the center to the edge of the chip, so the rate of conduction heat affects the overcurrent resistance of the chip. CONTENT OF THE UTILITY MODEL
[0004] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to solve the problem that the poor heat dissipation capacity of the chip in the prior art causes the high temperature region to be concentrated in the center of the chip.
[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate comprising opposite first and second surfaces; an epitaxial layer on the first surface, the epitaxial layer having a third surface on the side away from the substrate; a cell region in a portion of the epitaxial layer close to the third surface; a termination region in a portion of the epitaxial layer close to the third surface, the termination region surrounding the cell region on the third plane, a projection of the termination region on the first surface being a first region; a heat-conducting layer on a portion of the second surface, a projection of the heat-conducting layer on the first surface being located in at least a portion of the first region, the heat-conducting layer having a thermal conductivity greater than that of the substrate.
[0006] Optionally, a projection of the cell region on the first surface is a second region, and the thickness of the substrate corresponding to the second region is greater than the thickness of the substrate corresponding to a portion of the first region.
[0007] Optionally, a projection of the heat-conducting layer on the first surface is located in a portion of the first region, and the heat-conducting layer has one of a grid shape, a strip shape, a fan shape and a corrugated shape.
[0008] Optionally, the thickness of the substrate gradually decreases in steps from the second region to the first region, wherein the steps are acute angle steps or right angle steps.
[0009] Optionally, part of the first region forms a plurality of fan-shaped grooves in a direction from the second region to the first region, a side wall of the fan-shaped groove forms an obtuse angle with a groove bottom of the fan-shaped groove.
[0010] Optionally, part of the heat-conducting layer is located on the side wall of the fan-shaped groove.
[0011] Optionally, in the direction from the second region to the first region, the thickness of the heat-conducting layer is different.
[0012] Optionally, the material of the heat-conducting layer is graphene.
[0013] Optionally, the heat-conducting layer is a single-layer or multi-layer graphene layer.
[0014] Optionally, the semiconductor structure further comprises: a back metal layer covering the heat-conducting layer and part of the substrate.
[0015] Optionally, the epitaxial layer comprises: a first sub-epitaxial layer located on the first surface; and a second sub-epitaxial layer located on a surface of the first sub-epitaxial layer away from the heat-conducting layer, a doping concentration of the first sub-epitaxial layer is greater than a doping concentration of the second sub-epitaxial layer.
[0016] Optionally, the material of the substrate is silicon carbide.
[0017] Optionally, the thickness of the heat-conducting layer is less than the thickness of the back metal layer, and the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the back metal layer.
[0018] According to another aspect of the present application, a semiconductor device is provided, comprising any one of the semiconductor structures.
[0019] By applying the technical solution of the present application, the semiconductor structure comprises a substrate with a first surface and a second surface, an epitaxial layer located on the first surface, a cell region and a terminal region located in the epitaxial layer, and a heat-conducting layer located on part of the second surface, wherein the terminal region surrounds the cell region on a third plane, a projection of the terminal region on the first surface is a first region, a projection of the heat-conducting layer on the first surface is located in part of the first region, and the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the substrate. Compared with the problem that the poor heat dissipation capacity of the chip in the prior art leads to the high-temperature region being concentrated in the center of the chip, the heat-conducting layer with a thermal conductivity higher than that of the substrate is arranged at the edge position of the back surface of the chip (i.e., the position corresponding to the terminal region) in the present application, the advantage of high thermal conductivity of the heat-conducting layer is utilized, the rate of heat conduction from the center of the chip to the edge of the chip is ensured to be fast, the accumulation of heat in the center of the chip is ensured to be less, and thus the heat resistance of the chip is ensured to be good. BRIEF DESCRIPTION OF DRAWINGS
[0020] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0021] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided according to an embodiment of this application is shown;
[0022] Figure 2 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;
[0023] Figure 3 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;
[0024] Figure 4 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;
[0025] Figure 5 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;
[0026] Figure 6 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;
[0027] Figure 7 A top view schematic diagram of a semiconductor structure provided according to an embodiment of this application is shown;
[0028] Figure 8 A top view schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;
[0029] Figure 9 A top view schematic diagram of yet another semiconductor structure provided according to an embodiment of this application is shown;
[0030] Figure 10 A top view schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown.
[0031] The above figures include the following reference numerals:
[0032] 10. Substrate; 11. Epitaxial layer; 12. Cell region; 13. Termination region; 14. Thermally conductive layer; 15. Back metal layer; 101. First region; 102. Second region; 16. Sector groove. Detailed Implementation
[0033] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0034] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0035] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.
[0036] As described in the background section, chips in the prior art have poor heat dissipation capabilities. To address the above-mentioned problems, embodiments of this application provide a semiconductor structure and a semiconductor device.
[0037] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0038] This application provides a semiconductor structure, such as... Figures 1 to 10 As shown, it includes:
[0039] Substrate 10 includes opposing first and second surfaces;
[0040] Epitaxial layer 11 is located on the first surface, and the epitaxial layer 11 has a third surface on the side opposite to the substrate 10;
[0041] Cell region 12 is located in the portion of the epitaxial layer 11 that is close to the third surface.
[0042] Terminal region 13 is located in the portion of the epitaxial layer 11 near the third surface. Terminal region 13 surrounds cell region 12 on the third plane. The projection of terminal region 13 on the first surface is first region 101.
[0043] A thermally conductive layer 14 is located on a portion of the second surface, and the projection of the thermally conductive layer 14 on the first surface is located in at least a portion of the first region 101. The thermal conductivity of the thermally conductive layer 14 is greater than that of the substrate 10.
[0044] In the above embodiments, the semiconductor structure includes a substrate having a first surface and a second surface, an epitaxial layer located on the first surface, a cell region and a termination region located in the epitaxial layer, and a thermally conductive layer located on a portion of the second surface. The termination region surrounds the cell region on a third plane, and the projection of the termination region onto the first surface forms a first region. The projection of the thermally conductive layer onto the first surface is located at least in a portion of the first region, and the thermal conductivity of the thermally conductive layer is greater than that of the substrate. Compared to the problem in existing technologies where poor heat dissipation leads to a concentration of high-temperature areas at the chip center, this application arranges a thermally conductive layer with a thermal conductivity higher than that of the substrate at the edge of the back side of the chip (i.e., the location corresponding to the termination region). Utilizing the high thermal conductivity of the thermally conductive layer, the rate of heat conduction from the chip center to the chip edge is faster, minimizing heat accumulation at the chip center and thus ensuring better heat resistance of the chip.
[0045] Specifically, such as Figures 1 to 6 As shown, the projection of the aforementioned cell region 12 onto the aforementioned first surface is the second region 102.
[0046] Specifically, the specific structures of the aforementioned active area and terminal area can be configured according to actual needs, and this application does not impose specific restrictions on them.
[0047] Among the alternative solutions in this application, such as Figures 3 to 6 As shown, the projection of the cell region 12 onto the first surface is the second region 102, and the thickness of the substrate 10 corresponding to the second region 102 is greater than the thickness of the substrate 10 corresponding to a portion of the first region 101. In this embodiment, by making the substrate thickness corresponding to the projection region (second region) of the cell region on the first surface greater than the substrate thickness corresponding to the projection region (first region) of the terminal region on the first surface, the heat dissipation area of the cell region can be increased, thereby further improving the heat dissipation efficiency of the entire semiconductor structure.
[0048] In one alternative, such as Figure 1 , Figures 3 to 10 As shown, the projection of the aforementioned heat-conducting layer 14 onto the aforementioned first surface is located within a portion of the aforementioned first region 101. The shape of the aforementioned heat-conducting layer is one of a grid, a strip, a fan, or a corrugated shape. In this embodiment, different shapes may be suitable for different heat dissipation requirements and spatial layouts. For example, a grid-shaped heat-conducting layer can provide uniform heat dissipation, while a strip or fan-shaped heat-conducting layer may be more suitable for a specific spatial layout, and a corrugated shape may help to enhance the surface area for heat conduction.
[0049] like Figure 8 As shown, the heat-conducting layer 14 described above is strip-shaped. (As...) Figure 9 As shown, the heat-conducting layer 14 has a mesh-like shape.
[0050] In another alternative, such as Figure 2 As shown, the projection of the heat-conducting layer 14 onto the first surface is located in the first region 101.
[0051] In some other alternatives to this application, such as Figures 4 to 6 As shown, the thickness of the substrate 10 gradually decreases in a stepped manner from the second region 102 to the first region 101, wherein the steps are acute-angled steps or right-angled steps. In this embodiment, this stepped design helps to conduct heat more effectively from the center (cell region) of the chip to the edge (terminal region). Since heat is conducted from the center of the chip to the edge, the stepped design can provide a more direct heat conduction path and reduce thermal resistance.
[0052] Specifically, such as Figure 4 As shown, the stairs are right-angled stairs; Figure 5 and Figure 6 As shown, the steps are acute-angled steps.
[0053] In other embodiments, such as Figure 10 As shown, a portion of the first region (not shown) forms a plurality of sector-shaped grooves 16 in a direction pointing from the second region (not shown) to the first region, and the sidewalls of the sector-shaped grooves 16 form an obtuse angle with the bottom of the sector-shaped grooves 16.
[0054] In other embodiments, such as Figure 10 As shown, part of the aforementioned heat-conducting layer 14 is located on the side wall of the aforementioned fan-shaped groove 16.
[0055] Specifically, Figures 1 to 6 This is a schematic diagram of a cross-sectional structure of a semiconductor structure cut along a direction parallel to the substrate thickness. Figures 7 to 10 This is a top-view diagram showing the location of the thermally conductive layer in the semiconductor structure.
[0056] In other embodiments, such as Figure 6 As shown, the thickness of the thermal conductive layer 14 varies in the direction from the second region 102 to the first region 101. In this embodiment, by designing thermal conductive layers of different thicknesses in different regions, a thicker thermal conductive layer can be used in regions with higher heat flux density to improve heat conduction efficiency, thereby more effectively conducting heat from the chip center to the edge and further enhancing the heat dissipation capacity of the entire semiconductor structure.
[0057] In other embodiments, such as Figures 1 to 5As shown, the thickness of the thermally conductive layer 14 is the same in the direction from the second region 102 to the first region 101. In this embodiment, the uniform thickness of the thermally conductive layer helps to achieve a more uniform heat distribution on the second surface of the substrate, thereby further improving heat dissipation efficiency.
[0058] According to some exemplary embodiments of this application, the material of the above-mentioned thermal conductive layer is graphene. In this embodiment, the material of the thermal conductive layer is graphene. Since graphene has a very high thermal conductivity and excellent thermal conductivity, it further ensures that the heat from the center of the chip is conducted to the edge of the chip at a relatively fast rate, thus further ensuring that the chip has good heat dissipation capabilities.
[0059] In addition, graphene is introduced at the corresponding position of the terminal area on the back of the chip. Since graphene is also conductive and the terminal position is not the main current flow path, it has a weak impact on electrical performance.
[0060] According to some other exemplary embodiments of this application, the above-mentioned thermally conductive layer is a single-layer or multi-layer graphene layer.
[0061] Specifically, graphene has excellent thermal conductivity. Pure, defect-free monolayer graphene has a thermal conductivity of up to 5300 W / mK, which is higher than that of single-walled carbon nanotubes (3500 W / mK) and multi-walled carbon nanotubes (3000 W / mK). When used as a carrier, its thermal conductivity can also reach 600 W / mK.
[0062] Specifically, monolayer graphene has a thermal conductivity as high as 3000-5000 W / m·K, a thermal emissivity of over 0.98, and a large specific surface area (theoretically up to 2600 m² / g). Graphene itself possesses excellent thermal stability, weather resistance, aging resistance, and high mechanical strength, thus improving the performance of chips in various aspects.
[0063] In some of the alternative solutions of this application, such as Figures 1 to 6 As shown, the semiconductor structure further includes a back metal layer 15, covering the thermally conductive layer 14 and a portion of the substrate 10. In this embodiment, the back metal layer can serve as an electrical ground layer for the semiconductor device, helping to reduce parasitic inductance and capacitance, and improve the high-frequency performance of the device.
[0064] In other embodiments, the epitaxial layer includes: a first sub-epitaxial layer located on the first surface; and a second sub-epitaxial layer located on the surface of the first sub-epitaxial layer away from the thermally conductive layer, wherein the doping concentration of the first sub-epitaxial layer is greater than the doping concentration of the second sub-epitaxial layer. In this embodiment, the first sub-epitaxial layer serves as a buffer layer, and the second sub-epitaxial layer serves as a drift region. By providing the buffer layer, the doping influence between the substrate and the drift region is isolated, thereby reducing the negative impact of substrate doping on device performance and ensuring good device performance.
[0065] Specifically, the aforementioned cell region and the aforementioned terminal region are located in the aforementioned second sub-epithelial layer.
[0066] According to some other exemplary embodiments of this application, the substrate is made of silicon carbide. In this embodiment, silicon carbide has a higher thermal conductivity than conventional silicon materials, which helps to more effectively conduct heat from the core of the semiconductor device, thereby further improving the heat dissipation efficiency of the device.
[0067] In other embodiments, the thickness of the thermally conductive layer is less than the thickness of the back metal layer, and the thermal conductivity of the thermally conductive layer is greater than that of the back metal layer. In this embodiment, by using a thermally conductive layer with high thermal conductivity but a thin thickness, heat dissipation performance can be improved without significantly increasing material costs, which helps to achieve a balance between cost and performance.
[0068] In other embodiments, the thickness of the thermally conductive layer is less than the thickness of the substrate. In this embodiment, the thermal conductivity of the thermally conductive layer is higher than that of the substrate. When the thermally conductive layer is thinner, its thermal resistance is relatively smaller, which means that heat can be transferred through the thermally conductive layer more quickly, thereby further reducing the accumulation of heat inside the chip.
[0069] This application also provides a semiconductor device, including any of the above-described semiconductor structures.
[0070] In the above embodiments, the semiconductor device includes a semiconductor structure, wherein the semiconductor structure includes a substrate having a first surface and a second surface, an epitaxial layer located on the first surface, a cell region and a termination region located in the epitaxial layer, and a thermally conductive layer located on a portion of the second surface. The termination region surrounds the cell region on a third plane, and the projection of the termination region on the first surface is a first region. The projection of the thermally conductive layer on the first surface is located at least in a portion of the first region, and the thermal conductivity of the thermally conductive layer is greater than that of the substrate. Compared with the problem in the prior art where poor heat dissipation leads to the concentration of high-temperature areas in the chip center, this application arranges a thermally conductive layer with a thermal conductivity higher than that of the substrate at the edge of the back side of the chip (i.e., the location corresponding to the termination region). Utilizing the high thermal conductivity of the thermally conductive layer, the rate of heat conduction from the chip center to the chip edge is faster, ensuring less heat accumulation in the chip center, thereby ensuring better heat resistance of the chip.
[0071] As can be seen from the above description, the embodiments of this application achieve the following technical effects:
[0072] 1) In the semiconductor structure of this application, the semiconductor structure includes a substrate having a first surface and a second surface, an epitaxial layer located on the first surface, a cell region and a termination region located in the epitaxial layer, and a thermally conductive layer located on a portion of the second surface. The termination region surrounds the cell region on a third plane, and the projection of the termination region onto the first surface is a first region. The projection of the thermally conductive layer onto the first surface is located at least in a portion of the first region, and the thermal conductivity of the thermally conductive layer is greater than that of the substrate. Compared with the problem in the prior art where poor heat dissipation leads to the concentration of high-temperature areas in the chip center, this application arranges a thermally conductive layer with a thermal conductivity higher than that of the substrate at the edge of the back side of the chip (i.e., the position corresponding to the termination region). Utilizing the high thermal conductivity of the thermally conductive layer, the rate of heat conduction from the chip center to the chip edge is faster, ensuring less heat accumulation in the chip center, thereby ensuring better heat resistance of the chip.
[0073] 2) In the semiconductor device of this application, the semiconductor device includes a semiconductor structure, wherein the semiconductor structure includes a substrate having a first surface and a second surface, an epitaxial layer located on the first surface, a cell region and a termination region located in the epitaxial layer, and a thermally conductive layer located on a portion of the second surface. The termination region surrounds the cell region on a third plane, and the projection of the termination region on the first surface is a first region. The projection of the thermally conductive layer on the first surface is located at least in a portion of the first region, and the thermal conductivity of the thermally conductive layer is greater than that of the substrate. Compared with the problem in the prior art where poor heat dissipation of chips leads to the concentration of high-temperature areas in the chip center, this application arranges a thermally conductive layer with a thermal conductivity higher than that of the substrate at the edge position of the back side of the chip (i.e., the position corresponding to the termination region). Utilizing the high thermal conductivity of the thermally conductive layer, the rate of heat conduction from the chip center to the chip edge is ensured to be faster, ensuring less heat accumulation in the chip center, thereby ensuring better heat resistance of the chip.
[0074] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes opposing first and second surfaces; An epitaxial layer is located on the first surface, and the epitaxial layer has a third surface on the side opposite to the substrate; The cell region is located in the epitaxial layer near the third surface; The terminal region is located in the epitaxial layer near the third surface. The terminal region surrounds the cell region on the third surface. The projection of the terminal region on the first surface is a first region. A thermally conductive layer is located on a portion of the second surface, the projection of the thermally conductive layer on the first surface being at least located in a portion of the first region, and the thermal conductivity of the thermally conductive layer being greater than that of the substrate.
2. The semiconductor structure according to claim 1, characterized in that, The projection of the cell region onto the first surface is a second region, and the thickness of the substrate corresponding to the second region is greater than the thickness of the substrate corresponding to a portion of the first region.
3. The semiconductor structure according to claim 1, characterized in that, The projection of the heat-conducting layer on the first surface is located in a portion of the first region, and the shape of the heat-conducting layer is one of a grid, a strip, a fan, or a corrugated shape.
4. The semiconductor structure according to claim 2, characterized in that, The thickness of the substrate gradually decreases in steps from the second region to the first region, wherein the steps are acute-angled steps or right-angled steps.
5. The semiconductor structure according to claim 2, characterized in that, The first region is partially formed with a plurality of fan-shaped grooves in a direction from the second region to the first region, and the sidewalls of the fan-shaped grooves form an obtuse angle with the bottom of the fan-shaped grooves.
6. The semiconductor structure according to claim 5, characterized in that, A portion of the heat-conducting layer is located on the sidewall of the fan-shaped groove.
7. The semiconductor structure according to claim 2, characterized in that, The thickness of the thermally conductive layer varies in the direction from the second region to the first region.
8. The semiconductor structure according to claim 1, characterized in that, The thermally conductive layer is made of graphene.
9. The semiconductor structure according to claim 8, characterized in that, The thermally conductive layer is a single-layer or multi-layer graphene layer.
10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a back metal layer covering the thermally conductive layer and a portion of the substrate.
11. The semiconductor structure according to claim 1, characterized in that, The epitaxial layer includes: The first sub-epipolar layer is located on the first surface; The second sub-epitaxial layer is located on the surface of the first sub-epitaxial layer away from the thermally conductive layer, and the doping concentration of the first sub-epitaxial layer is greater than that of the second sub-epitaxial layer.
12. The semiconductor structure according to claim 1, characterized in that, The substrate is made of silicon carbide.
13. The semiconductor structure according to claim 10, characterized in that, The thickness of the thermally conductive layer is less than the thickness of the back metal layer, and the thermal conductivity of the thermally conductive layer is greater than that of the back metal layer.
14. A semiconductor device, characterized in that, The semiconductor structure includes any one of claims 1 to 13.