High-density interconnection bridge and packaging structure

Abstract

The utility model provides a high density interconnection bridge and packaging structure, the high density interconnection bridge comprises an interconnection bridge body, rewiring layers, silicon through holes / glass through holes and micro welding columns, the rewiring layers are arranged on the upper surface and the lower surface of the interconnection bridge body, the rewiring layers are used for transverse interconnection, and the micro welding columns are arranged on the upper surface and the lower surface of the interconnection bridge body. The silicon through hole / glass through hole is formed in the interconnection bridge body, the silicon through hole / glass through hole is used for longitudinal interconnection of the rewiring layers on the upper surface and the lower surface of the interconnection bridge body, and the micro welding columns are bonded with the rewiring layers. According to the utility model, the chips can be subjected to transverse high-density interconnection through the interconnection bridges, and the chips and the substrate can be subjected to longitudinal high-density interconnection through the interconnection bridges, so that the connection mode not only reduces the packaging area, improves the interconnection density in unit area, and realizes high integration of complex functions; the flexibility and the expandability of the system are improved, and meanwhile, the power consumption and the delay are reduced, so that the efficiency and the reliability of the whole system are improved.

Description

Technical Field

[0001] This utility model relates to the field of microelectronic packaging technology, and in particular to a high-density interconnect bridge and its packaging structure. Background Technology

[0002] High-density interconnect technology has been widely used in data centers, cloud computing, 5G, and other fields, demonstrating characteristics such as modularity, high scalability, high transmission speed, and low power consumption. It also plays a crucial role in semiconductor manufacturing and chip packaging.

[0003] In semiconductor manufacturing, high-density interconnect technology is mainly used to connect internal chips. As chip manufacturing processes continue to advance, the number of transistors inside chips continues to increase, and the requirements for interconnect technology are becoming increasingly stringent. Increasing interconnect density, especially lateral interconnect density, through high-density interconnect bridges (without material limitations) can significantly improve the packaging performance of products.

[0004] Currently, 2.5D and 3D packaging processes are complex, have long design cycles, are difficult to implement, require advanced equipment, and are costly. They are only used in high-value products such as HPC, GPUs, and AI. Intel's 2.3D EMIB packaging technology embeds silicon interconnect bridges in the substrate, reducing packaging difficulty but increasing substrate manufacturing complexity and offering little cost improvement. IBM's technology, with its large-area openings on the substrate, also faces similar issues, limiting its wider application. For large-scale, low-cost applications of high-density chip packaging, there is an urgent need to propose lower-cost multi-chip high-density interconnect solutions based on existing mature processes. Utility Model Content

[0005] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing an interconnect bridge and packaging solution for high-density interconnection within a chip, thereby increasing chip interconnect density, improving packaging integration, and enhancing product performance.

[0006] To achieve the above objectives, this utility model provides a high-density interconnect bridge, including an interconnect bridge body, a redistribution layer, through-silicon vias / glass vias, and micro-bonding pillars. The redistribution layer is disposed on the upper and lower surfaces of the interconnect bridge body and is used for lateral interconnection. The through-silicon vias / glass vias are disposed inside the interconnect bridge body and are used for longitudinal interconnection of the redistribution layer on the upper and lower surfaces of the interconnect bridge body. The micro-bonding pillars are bonded to the redistribution layer.

[0007] Furthermore, the interconnect bridge body is made of silicon or glass.

[0008] Furthermore, the interconnect material within the redistribution layer is copper, and the dielectric material is polyimide.

[0009] Furthermore, the linewidth / spacing of the redistribution layer is smaller than the linewidth / spacing of the substrate.

[0010] This utility model also provides a high-density packaging structure, including at least a substrate, a first chip, a second chip, and a high-density interconnect bridge as described above. The first chip and the second chip are provided with multiple solder joints, including conventional solder joints and micro solder joints. The conventional solder joints are spaced relatively far apart and are bonded to the substrate by solder balls. The micro solder joints are spaced relatively far apart and are bonded to micro solder pillars on the upper surface of the high-density interconnect bridge. The micro solder pillars on the lower surface of the high-density interconnect bridge are bonded to the substrate. All bonding positions are filled with filler glue.

[0011] Furthermore, the micro-welding pillars on the upper and lower surfaces of the high-density interconnect bridge are preset to ensure that the first chip and the second chip are parallel to the substrate after packaging.

[0012] The above-mentioned solution of this utility model has the following beneficial effects:

[0013] The high-density interconnect bridge and packaging structure provided by this utility model enables high-density horizontal interconnection between chips and high-density vertical interconnection between chips and the substrate through the interconnect bridge by setting the redistribution layer of the interconnect bridge and through silicon vias / glass vias. This connection method not only reduces the packaging area and increases the interconnection density per unit area, but also achieves high integration of complex functions, increases the flexibility and scalability of the system, and reduces power consumption and latency, thereby improving the efficiency and reliability of the overall system.

[0014] Other beneficial effects of this invention will be described in detail in the following detailed description section. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the high-density interconnect bridge structure of this utility model;

[0016] Figure 2 This is a schematic diagram of the high-density packaging structure of this utility model;

[0017] Figure 3 This is a schematic diagram of the process flow for the high-density packaging structure of this utility model.

[0018] [Explanation of Labels in the Attached Image]

[0019] 1-Interconnect bridge body; 2-Reconnection layer; 3-Through silicon via / glass via; 4-Micro solder pillar; 5-Substrate; 6-Solder ball; 7-First chip; 8-Second chip; 9-Filling adhesive. Detailed Implementation

[0020] To make the technical problems, solutions, and advantages of this utility model clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0021] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0023] like Figure 1 As shown, an embodiment of this utility model provides a high-density interconnect bridge, including an interconnect bridge body 1, which is manufactured using wafer fabrication and substrate fabrication processes and has bidirectional high-density interconnection capabilities. The interconnect bridge body 1 is typically made of silicon or glass, and a redistribution layer 2 (RDL) is disposed on the surface of the interconnect bridge body 1 for lateral interconnection. Vertical interconnection is achieved within the interconnect bridge body 1 through through-silicon vias (TSVs) / through-glass vias (TGVs) 3.

[0024] In this design, the interconnect material within the redistribution layer 2 is typically copper, and the dielectric material is typically polyimide. The redistribution layer 2 enables high-density lateral signal transmission. Through-silicon vias (TSVs) / through-glass vias (TVs) 3 are used for high-density vertical signal transmission. The interconnect bridges are equipped with micro-bond posts 4, which are bonded to the redistribution layer 2. The upper and lower redistribution layers 2 are connected via the TSVs / TVs 3. Therefore, when the micro-bond posts 4 are bonded to the chip, high-density lateral interconnection with each other and high-density vertical interconnection with the substrate 5 can be achieved through the interconnect bridges.

[0025] It should be noted that in this embodiment, the redistribution layer 2 is disposed on the upper and lower surfaces of the interconnect bridge body 1. When the chip is located above the interconnect bridge, it can perform lateral high-density communication through the redistribution layer 2 on the upper surface of the interconnect bridge body 1, and can also communicate to a certain extent through the redistribution layer 2 on the lower surface of the interconnect bridge body 1. This arrangement of the redistribution layer 2 makes its packaging more flexible.

[0026] It should be noted that in this embodiment, the linewidth / spacing of the redistribution layer 2 is typically smaller than that of the substrate 5 (e.g., 10 / 10μm), thus achieving a higher communication density compared to lateral communication in the substrate 5. Meanwhile, the chip is still vertically interconnected with the substrate 5 via solder balls 6, and this interconnection is relatively low-density compared to interconnect bridges.

[0027] Therefore, by setting up interconnect bridges, low-cost, high-density, and high-speed interconnection between chips can be achieved, while significantly improving the performance of the package.

[0028] At the same time, such as Figure 2 As shown, based on the same concept, this embodiment also provides a high-density packaging structure, including a substrate 5, a first chip 7, a second chip 8, and an interconnect bridge. The first chip 7 and the second chip 8 have multiple solder joints, including conventional solder joints and micro solder joints. The conventional solder joints are spaced larger and are bonded to the substrate 5 via solder balls 6. The micro solder joints are spaced smaller and are bonded to micro solder pillars 4 on the upper surface of the interconnect bridge. The micro solder pillars 4 on the lower surface of the interconnect bridge are bonded to the substrate 5. All bonding sites are protected by filler adhesive 9.

[0029] It should be noted that in this embodiment, the chip packaging height can be controlled by the size of the micro-soldering pillars 4 on the upper and lower surfaces of the interconnect bridge, so that the chip is horizontal after packaging, avoiding product warping and other phenomena that affect product quality.

[0030] At the same time, such as Figure 3As shown, the process flow of the high-density packaging structure provided in this embodiment is as follows: a high-density interconnect bridge with horizontal and vertical bidirectional interconnection function is manufactured through wafer manufacturing process and substrate manufacturing process; the interconnect bridge is soldered and bonded to substrate 5; the first chip 7 and the second chip 8 are soldered and bonded to substrate 5 through solder balls 6, and simultaneously soldered and bonded to the interconnect bridge through micro solder pillars 4; the solder bonding positions are protected by filler glue 9 to achieve stress buffering and protection; finally, solder balls 6 are implanted on the back of substrate 5 to connect with PCB.

[0031] It should be noted that the above embodiments only involve the first chip 7 and the second chip 8. When more chips need to be interconnected at high density, they can still be interconnected using the interconnect bridges provided in this embodiment. For example, the four chips shown in the figure are interconnected simultaneously through a single interconnect bridge. High-density silicon channel interconnect bridges are used, and interconnection is achieved with the substrate 5 through micro-bond posts 4. Based on this, the four chips are interconnected with the substrate 5 and the interconnect bridges using a pick-and-place machine. The micro-bond posts 4 for each chip are located at opposite diagonal positions of the interconnect bridges, and finally protected with filler adhesive 9, as shown in the figure.

[0032] In summary, the high-density interconnect bridge and packaging structure provided in this embodiment improves the communication efficiency between chips by increasing the interconnect density, while also improving the space utilization of the packaging structure and adapting to the needs of more complex circuit designs. This interconnect bridge has significant advantages in multi-chip connectivity, effectively connecting multiple chips tightly together and improving the integration and performance of integrated circuits.

[0033] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0034] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A high-density interconnect bridge, characterized in that, The device includes an interconnect bridge body, a redistribution layer, through-silicon vias (TSVs) / glass vias, and micro-bonding pillars. The redistribution layer is disposed on the upper and lower surfaces of the interconnect bridge body and is used for lateral interconnection. The TSVs / glass vias are disposed inside the interconnect bridge body and are used for longitudinal interconnection of the redistribution layer on the upper and lower surfaces of the interconnect bridge body. The micro-bonding pillars are bonded to the redistribution layer.

2. The high-density interconnect bridge according to claim 1, characterized in that, The interconnect bridge body is made of silicon or glass.

3. A high-density interconnect bridge according to claim 1, characterized in that, The interconnect material in the rewiring layer is copper, and the dielectric material is polyimide.

4. A high-density interconnect bridge according to claim 1, characterized in that, The linewidth / spacing of the redistribution layer is smaller than the linewidth / spacing of the substrate.

5. A high-density packaging structure, characterized in that, The system includes at least a substrate, a first chip, a second chip, and a high-density interconnect bridge as described in any one of claims 1-4. The first chip and the second chip are provided with multiple solder joints, including conventional solder joints and micro solder joints. The conventional solder joints are spaced relatively far apart and are bonded to the substrate by solder balls. The micro solder joints are spaced relatively far apart and are bonded to micro solder pillars on the upper surface of the high-density interconnect bridge. The micro solder pillars on the lower surface of the high-density interconnect bridge are bonded to the substrate. All bonding positions are filled with filler adhesive.

6. The high-density packaging structure according to claim 5, characterized in that, The micro-welding pillars on the upper and lower surfaces of the high-density interconnect bridge are preset to ensure that the first chip and the second chip are parallel to the substrate after packaging.

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