Semiconductor structure

Abstract

A semiconductor structure is provided. The semiconductor structure includes a logic device, a first contact connected to the logic device, a first power rail on and connected to the logic device, and a second power rail on the logic device. A transistor having a channel region including indium, gallium, zinc, and oxygen is on and connected to the second power rail.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure. BACKGROUND

[0002] As the semiconductor industry enters nanometer technology process nodes to pursue higher device densities, higher performance, and lower costs, challenges from both manufacturing and design have led to the development of three-dimensional designs, such as gate-all-around (GAA) transistors. GAA transistors are composed of one or more nano-sheet or nano-wire channel regions, with a gate wrapped around the nano-sheet or nano-wire. GAA transistors can reduce short channel effects. SUMMARY

[0003] A semiconductor structure includes a logic device, a first contact to the logic device, a first power rail on the logic device and to the logic device, and a second power rail on the logic device. A transistor has a channel region including amorphous indium gallium zinc oxide (IGZO) on the second power rail and connected to the second power rail.

[0004] A semiconductor structure includes a carrier wafer and a device wafer. The carrier wafer includes a substrate layer, a first dielectric layer, and a first conductive layer embedded in the first dielectric layer. The device wafer includes a logic device connected to the first conductive layer, a backside contact to the logic device, and a second dielectric layer under the logic device and bonded to the first dielectric layer of the carrier wafer. A third dielectric layer is on the logic device and a first power rail is embedded in the third dielectric layer and connected to the logic device. A fourth dielectric layer is on the logic device and a second power rail is embedded in the fourth dielectric layer. A memory device is on the second power rail and connected to the second power rail. The memory device includes a transistor having a channel layer including amorphous indium gallium zinc oxide (IGZO).

[0005] A semiconductor structure includes a logic device, a backside contact to the logic device, a second power rail, and a memory device. The memory device is on the second power rail and connected to the second power rail. The memory device includes a transistor and a storage element connected to the transistor. The transistor has a channel region. The channel region includes amorphous indium gallium zinc oxide (IGZO). BRIEF DESCRIPTION OF DRAWINGS

[0006] The detailed description of embodiments of the disclosure will be fully understood when read in conjunction with the accompanying drawings. It should be noted that the features are not drawn to scale and are only for illustrative purposes according to standard industry practice. In fact, the size of each feature can be arbitrarily increased or decreased for the purpose of clarity of discussion.

[0007] Figures 1 to 11Figures showing a plurality of views of a semiconductor structure at various stages of fabrication in accordance with some embodiments;

[0008] Figures 12 to 16 Figures showing a plurality of views of a semiconductor structure at various stages of fabrication in accordance with some embodiments;

[0009] Figures 17 to 20 Figures showing a plurality of views of a semiconductor structure at various stages of fabrication in accordance with some embodiments;

[0010] Figures 21 to 26 Figures showing a plurality of views of a semiconductor structure at various stages of fabrication in accordance with some embodiments;

[0011] Figures 27 to 30 Figures showing a plurality of views of a semiconductor structure at various stages of fabrication in accordance with some embodiments;

[0012] Figures 31 to 32 Figures showing a plurality of views of a semiconductor structure at various stages of fabrication in accordance with some embodiments.

[0013] Legend

[0014] 100 : semiconductor structure

[0015] 101 : logic device

[0016] 102 : wafer

[0017] 104 : channel (semiconductor) layer

[0018] 106 : gate structure

[0019] 108 : sidewall spacer

[0020] 110 : end spacer

[0021] 112 : source / drain region

[0022] 114 : bottom dielectric layer

[0023] 116 : isolation structure

[0024] 118 : source / drain contact

[0025] 120 : metallization layer

[0026] 122 : dielectric layer

[0027] 124 : gate dielectric layer

[0028] 126 : work function material layer

[0029] 128 : gate electrode layer

[0030] 130 : dielectric layer

[0031] 132 : etch stop layer

[0032] 134 : conductive structure

[0033] 134V : via portion

[0034] 134L : line portion

[0035] 200 : wafer

[0036] 202 : substrate layer

[0037] 204 : metallization layer

[0038] 206 : conductive structure

[0039] 208 : dielectric layer

[0040] 210 : etch stop layer

[0041] 212 : interface

[0042] 214 : dielectric layer

[0043] 216 : dielectric layer

[0044] 218,220 : power rail

[0045] 222 : etch stop layer

[0046] 224 : dielectric layer

[0047] 226 : gate contact

[0048] 228 : gate electrode

[0049] 230 : gate dielectric layer

[0050] 232 : channel layer

[0051] 234 : contact layer

[0052] 234A, 234B : source / drain contact

[0053] 236 : thin film transistor (TFT)

[0054] 238 : metallization layer

[0055] 240 : dielectric layer

[0056] 242 : etch stop layer

[0057] 244 : storage element

[0058] 244A : first layer

[0059] 244B : second layer

[0060] 244C : third layer

[0061] 245 : storage element

[0062] 246 : conductive structure

[0063] 248 : metallization layer

[0064] 250 : dielectric layer

[0065] 252 : etch stop layer

[0066] 254, 256 : conductive structure

[0067] 258 : memory device

[0068] 300 : transistor / top gate finFET device

[0069] 302 : dielectric layer

[0070] 304A, 304B : contact

[0071] 306 : dielectric layer

[0072] 308 : trench

[0073] 310A, 310B : source / drain contact

[0074] 312 : channel layer

[0075] 314 : gate dielectric layer

[0076] 316 : gate electrode

[0077] 318 : memory device

[0078] 400 : transistor / plane FET device

[0079] 402 : gate electrode

[0080] 404 : gate dielectric layer

[0081] 406 : channel layer

[0082] 408A, 408B : source / drain contact

[0083] 410 : memory device

[0084] 500: transistor / bottom-gate finFET device

[0085] 502: gate electrode

[0086] 504: gate dielectric

[0087] 504A, 504B: trenches

[0088] 506: channel layer

[0089] 508A, 508B: source / drain contacts

[0090] 510: memory device

[0091] 600: transistor / top-gate finFET device

[0092] 602A, 602B: source / drain contacts

[0093] 604: channel layer

[0094] 606: gate dielectric

[0095] 608: gate electrode layer

[0096] 610: memory device

[0097] 700: seal ring

[0098] 700A: first portion

[0099] 700B: second portion DETAILED DESCRIPTION

[0100] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed directly contacting each other, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact each other. Additionally, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0101] Moreover, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0102] The present disclosure provides one or more techniques for fabricating semiconductor structures. In some embodiments, the semiconductor structures include nanostructure transistors and nanostructure storage structures. As used herein, a nanostructure device, such as a nanostructure transistor or a nanostructure memory structure, refers to a substantially planar, near two-dimensional structure, such as sometimes referred to as a nano-sheet, as well as a two-dimensional structure with similar dimensions, such as sometimes referred to as a nano-wire. A nano-sheet device can have a rectangular cross-section and a nano-wire device can have an elliptical cross-section.

[0103] In some implementations, a semiconductor wafer with logic devices (referred to as a device wafer) is inverted and its top surface is bonded to a carrier wafer. Memory devices are formed within multiple layers located at the backside of the device wafer using low thermal budget back-end-of-line (BEOL) processes. A first buried power rail connects the logic devices, and a second buried power rail connects the memory devices. The memory devices can be three-dimensional memory devices, such as resistive random access memory (RRAM) devices, dynamic random access memory (DRAM) devices, magnetic random access memory (MRAM) devices, ferromagnetic random access memory (FeRAM) devices, or some other memory technology. In some implementations, additional memory devices, such as metal-insulator-metal (MIM) devices, are formed on the carrier wafer located below the logic devices.

[0104] The device wafer can be bonded to the carrier wafer through a hybrid bonding process, in which the conductive structures embedded in the dielectric layers of the device wafer are aligned with the conductive structures embedded in the dielectric layers of the carrier wafer to form interconnect structures. In the hybrid bonding process, heat or pressure is applied to cause the conductive structures in the device wafer to bond with the conductive structures of the carrier wafer, and heat or pressure is applied to cause the dielectric layers of the device wafer to bond with the dielectric layers of the carrier wafer.

[0105] Figures 1 to 11 A plurality of views of a semiconductor structure 100 at various stages of fabrication according to some embodiments. Figures 1 to 11 The plurality of views are a plurality of cross-sectional views taken through the semiconductor structure 100 in a direction corresponding to a gate width direction through a logic device 101 formed on a device wafer 102. Referring to FIG. 1A, a plurality of views of the semiconductor structure 100 at a first stage of fabrication according to some embodiments are shown. The semiconductor structure 100 includes a substrate 102, a channel semiconductor layer 104, a gate structure 106, a sidewall spacer 108, an end spacer 110, a source / drain region 112, a bottom dielectric layer 114, an isolation structure 116, a source / drain contact 118, and a metallization layer 120. Figure 1 According to some embodiments, the logic device 101 is a nanosheet structure including the channel semiconductor layer 104, the gate structure 106, the sidewall spacer 108, the end spacer 110, the source / drain region 112, and the bottom dielectric layer 114. The isolation structure 116 is formed under the logic device 101, and the source / drain contact 118 is embedded in the isolation structure 116 and contacts the source / drain region 112. The source / drain region 112 can include epitaxial silicon doped with n-type or p-type dopants. The source / drain region 112 can include germanium (Ge) or carbon (C) to create compressive stress or tensile stress, respectively. The isolation structure 116 can be a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a deep trench isolation (DTI) structure. In some embodiments, the metallization layer 120 is formed on the logic device 101. Although the logic device 101 is a nanosheet structure as shown, other types of logic devices can additionally be formed on or instead of the nanosheet structure, such as planar devices, finFET devices, or some other type of logic device.

[0106] In some embodiments, the logic device 101 is formed on a semiconductor layer that is subsequently removed, such as by a planarization process. The semiconductor layer is part of a substrate of the device wafer 102, which includes at least one of a epitaxial layer, a single crystalline semiconductor material such as but not limited to Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, and InP, a silicon-on-insulator (SOI) substrate, a wafer, or a die formed from a wafer. The semiconductor layer can also include single crystalline silicon. The logic device 101 can be formed by forming a stack including the channel layer 104 and the sacrificial semiconductor layers. The material of the channel layer 104 can be different from the material of the sacrificial semiconductor layers to provide an etch selectivity and allow the sacrificial semiconductor layers to be removed. In some embodiments, the channel semiconductor layer 104 can include substantially pure silicon, and the sacrificial semiconductor layers can include silicon germanium (SiGe x Ge (1-x) where x is in the range between 0.25 and 0.85). In some embodiments, the number of channel semiconductor layers 104 and the number of sacrificial semiconductor layers are variable. The order of the channel semiconductor layers 104 and the sacrificial semiconductor layers is variable. The thickness of the channel semiconductor layers 104 and the thickness of the sacrificial semiconductor layers are variable, and need not be the same. For example, the thickness of the channel semiconductor layers 104 and the thickness of the sacrificial semiconductor layers are decreasing from the bottom layer to the top layer.

[0107] In some embodiments, the gate structure 106 is formed by forming a sacrificial gate structure and forming a sidewall spacer 108 adjacent to the sacrificial gate electrode. An end spacer 110 is formed at the end of the adjacent sacrificial semiconductor layer and the source / drain region 112. The sidewall spacer 108 can include nitrogen and silicon or other suitable materials. The sacrificial gate electrode can include a sacrificial gate dielectric layer such as silicon dioxide and a sacrificial semiconductor layer such as polysilicon. A deposition process is performed to form a dielectric spacer layer over the channel semiconductor layer 104, the sacrificial semiconductor layers, and the gate structure 106, and an isotropic etch process is performed to remove portions of the dielectric spacer layer outside the end cavity to define the end spacer 110. The end spacer 110 can include a low-k dielectric material such as SiON, SiOCN, SiCN, SiOC, or other suitable materials. The end spacer 110 can include the same material composition as the sidewall spacer 108.

[0108] In some embodiments, the source / drain regions 112 are formed after the formation of the sacrificial gate structures and the end spacers 110. An epitaxial growth process can be performed to form the source / drain regions 112. The source / drain regions 112 can include SiP, SiC, or other suitable materials for n-type devices, and SiGe, SiB, or other suitable materials for p-type devices. The source / drain regions 112 can be individually or collectively referred to as source or drain depending on the context.

[0109] The dielectric layer 122 is formed adjacent to the sidewall spacers 108 and planarized to expose the sacrificial gate structures. The dielectric layer 122 includes silicon dioxide, a low-k dielectric material, one or more layers of low-k dielectric material, or other suitable materials. The materials used for the dielectric layer 122 can include at least one of silicon, oxygen, carbon, or hydrogen, such as SiCOH and SiOC, or other suitable materials. Organic materials, such as polymers, can be used for the dielectric layer 122. The dielectric layer 122 can include one or more layers of carbon-containing materials, organosilicate glass, pore former-containing materials, or combinations thereof. The dielectric layer 122 can also include nitrogen. The dielectric layer 122 can be formed by using at least one of, for example, low pressure chemical vapor deposition (LPCVD), atomic layer CVD (ALCVD), or a spin-on technique.

[0110] The sacrificial gate structures and the sacrificial semiconductor layer are removed to form gate cavities, and the gate structures 106 are formed within the gate cavities. The gate cavities include intermediate regions between the channel semiconductor layers 104, such that the gate structures 106 surround the channel semiconductor layers 104, which arrangement is referred to as a gate-all-around (GAA) structure. An etching process is performed to remove the sacrificial gate electrodes and the sacrificial gate dielectric layers. The etching process can be a wet etching process that is selective to the materials of the sacrificial gate electrodes and the materials of the sacrificial gate dielectric layers. Another etching process, such as a wet etching process, is performed to remove the sacrificial semiconductor layer to define the gate cavities.

[0111] The gate structure 106 is formed in the gate cavity, including the intermediate cavity between the channel semiconductor layers 104. In some embodiments, the gate structure 106 includes a gate dielectric layer 124, a work function material layer 126, and a gate electrode layer 128. The gate dielectric layer 124 can include SiO2, HfO, La, SiON, SiCON, Zn, Zr, or some other suitable material. The gate dielectric layer 124 can include a native oxide layer formed by exposing the semiconductor structure 100 to oxygen at various points in the process flow, resulting in the formation of silicon dioxide on exposed surfaces of the channel semiconductor layers 104. An additional dielectric layer is formed over the native oxide, the additional dielectric layer being, for example, a material such as a high-k dielectric material or other suitable material, to form the gate dielectric layer 124. As used herein, the term high-k refers to a material having a dielectric constant k value greater than about 3.9, where 3.9 is the dielectric constant k value of SiO2. The material of the high-k dielectric layer can be any suitable material. Examples of materials of the high-k dielectric layer include, but are not limited to, Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2O x N y x N y x N y x N y x N y x N y x N y x N y x ​​​​​​​​SiON, SiCON, ZnO, silicates thereof, or alloys thereof. Each value of x is independently between 0.5 and 3, and each value of y is independently between 0 and 2. The p-type device work function material layer 126 can include TiN, TaN, WN, MoN, or some other suitable material, or the n-type device work function material layer 126 can include AlC, TiAlC, TaAlC, TiSi, TaSi, WSi, CoSi, NiSi, or some other suitable material. The gate electrode layer 128 can include a metal fill layer, such as W, Ti, Ta, Al, Zn, In, Ga, Ge, C, or other suitable material. The gate dielectric layer 124, the work function material layer 126, and / or the gate electrode layer 128, as well as any other suitable layers of the gate structure 106, can be deposited by at least one of atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable process. According to some embodiments, a planarization process is performed to remove portions of the material that form the gate structure 106 above the dielectric layer 122.

[0112] In some embodiments, the metallization layer 120 includes one or more dielectric layers 130 formed above the dielectric layer 122. Any number of dielectric layers 130 can be considered. In some embodiments, at least one of the dielectric layers 130 includes a material having a medium or low dielectric constant, such as SiO2. The dielectric layers 130 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, plasma enhanced CVD (PECVD), and / or other suitable techniques. In some embodiments, the semiconductor structure 100 includes one or more etch stop layers 132 that separate the dielectric layers 130. In some embodiments, the etch stop layers 132 stop an etching process between the dielectric layers 130. According to some embodiments, the etch stop layers 132 include a dielectric material having a different etch selectivity than the dielectric layers 130. In some embodiments, at least one of the etch stop layers 132 includes SiN, SiCN, SiCO, and / or CN. The etch stop layers 132 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques.

[0113] In some embodiments, the metallization layer 120 includes one or more conductive structures 134 electrically connected to the gate electrode layer 128 or the lower conductive structures 134. In one embodiment, the conductive structures 134 extend through the respective dielectric layers 130. In some embodiments, at least some of the conductive structures 134 include a via portion 134V and a line portion 134L. The line portion 134L is wider than the via portion 134V and has an axial length that extends into the page. In some embodiments, the conductive structures 134 include a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, and / or other suitable materials. Other structures and / or configurations of the conductive structures 134 are within the scope of this disclosure.

[0114] In some embodiments, the source / drain contacts 118 are formed by flipping the device wafer 102, removing the semiconductor layer that was the substrate of the device wafer 102, forming openings in the isolation structures 116, and forming the source / drain contacts 118 in the openings.

[0115] Referring to Figure 2 , according to some embodiments, the device wafer 102 is inverted and bonded to the carrier wafer 200. For ease of illustration, Figure 2 not all of the reference numerals on the device wafer 102 are included in FIG. 2. In some embodiments, the carrier wafer 200 includes a substrate layer 202 and a metallization layer 204 over the substrate layer 202. Conductive structures 206 are embedded in dielectric layers 208 of the metallization layer 204. In some embodiments, the conductive structures 206 include a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, and / or other suitable materials. Other structures and / or configurations of the conductive structures 206 are within the scope of this disclosure. In some embodiments, at least one of the dielectric layers 208 includes a material with a medium or low dielectric constant, such as Si02. The dielectric layers 208 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. In some embodiments, etch stop layers 210 are formed to separate the dielectric layers 208. In some embodiments, the etch stop layers 210 stop an etching process between the dielectric layers 208 when forming the recesses of the conductive structures 206. According to some embodiments, the etch stop layers 210 include a dielectric material with a different etch selectivity than the dielectric layers 208. In some embodiments, at least one of the etch stop layers 210 includes SiN, SiCN, SiCO, and / or CN. The etch stop layers 210 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques.

[0116] In some embodiments, the device wafer 102 is bonded to the carrier wafer 200 using a hybrid bonding process to form the hybrid bonding interface 212. In the hybrid bonding process, the conductive structures embedded in the dielectric layers of the device wafer are aligned and bonded with the conductive structures embedded in the dielectric layers on the carrier wafer to form interconnect structures. In the hybrid bonding process, heat and / or pressure are applied to bond the conductive structures in the device wafer with the conductive structures in the carrier wafer and to bond the dielectric layers of the device wafer with the dielectric layers of the carrier wafer. For example, when temperature and / or heat are applied to the device wafer 102 and the carrier wafer 200, similar materials on each semiconductor wafer 102, 200 form hybrid bonds with each other. The embedded conductive structures 206 in the carrier wafer 200 are bonded with the conductive structures 134 in the device wafer 102. Other bonds between the conductive structures can exist within or outside the page. The exposed dielectric layers 208 of the carrier wafer 200 are bonded with the exposed dielectric layers 130 of the device wafer 102. The conductive structures 206 and the conductive structures 134 increase heat transfer between the device wafer 102 and the carrier wafer 200, potentially increasing the performance of the semiconductor structure 100.

[0117] Referring to Figure 3 Dielectric layers 214, 216 are formed over the upper exposed dielectric layers 130 and the source / drain contacts 118, and power rails 218, 220 are formed in the dielectric layers 214, 216, respectively, according to some embodiments. The power rail 218 contacts the source / drain contacts 118. In some embodiments, the power rail 218 has a smaller width than the power rail 220 to support a different power voltage. For example, the voltage on the power rail 220 can be higher than the voltage on the power rail 218. The dielectric layers 214, 216 can include a material with a medium or low dielectric constant, such as SiO2. The dielectric layers 214, 216 can be formed by a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. In some embodiments, a trench is formed in the dielectric layer 214, and the trench is filled with a conductive material and planarized to form the power rail 218. The dielectric layer 216 is formed over the power rail 218 and the dielectric layer 214. For example, a via opening is formed in the dielectric layer 216 using a dual damascene process and an etch stop layer 222, and the trench and the via opening are filled with a conductive material and planarized. In some embodiments, the power rails 218, 220 include a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes W, Ru, Ir, and / or other suitable materials. Other structures and / or configurations of the power rails 218, 220 are within the scope of the present disclosure.

[0118] Referring to Figure 4According to some embodiments, a dielectric layer 224 is formed over the power rail 220 and the dielectric layer 216, and a gate contact 226 is formed in the dielectric layer 224. The dielectric layer 224 can include a material with a medium or low dielectric constant, such as SiO2. The dielectric layer 224 can be formed by a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. In some embodiments, a trench is formed in the dielectric layer 224, and the trench is filled with a conductive material and planarized to form the gate contact 226. In some embodiments, the gate contact 226 includes a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, and / or other suitable materials.

[0119] Referring to Figure 5 According to some embodiments, a gate electrode 228 is formed over the dielectric layer 224 and the gate contact 226. In some embodiments, the gate electrode 228 is formed by depositing a layer of gate electrode material and performing a patterned etching process to form a fin. In some embodiments, the gate electrode 228 includes titanium nitride.

[0120] Referring to Figure 6 According to some embodiments, a gate dielectric layer 230, a channel layer 232, and a contact layer 234 are formed over the gate electrode 228. The gate dielectric layer 230 can include a high dielectric constant dielectric material. In some embodiments, the channel layer 232 includes amorphous indium gallium zinc oxide (IGZO). The contact layer 234 can include the same material as the gate electrode 228, such as titanium nitride.

[0121] Referring to Figure 7 According to some embodiments, the gate dielectric layer 230, the channel layer 232, and the contact layer 234 are patterned. The gate dielectric layer 230, the channel layer 232, and the contact layer 234 can be patterned by performing an etching process in the presence of a patterned etching mask.

[0122] Referring to Figure 8 According to some embodiments, the contact layer 234 is patterned to form source / drain contacts 234A, 234B. The contact layer 234 can be patterned by performing an etching process in the presence of a patterned etching mask. In some embodiments, the gate electrode 228, the gate dielectric layer 230, the channel layer 232, and the source / drain contacts 234A, 234B define a thin film transistor (TFT) 236. In some embodiments, the gate electrode 228 includes a fin structure, and the TFT 236 is a bottom gate finFET.

[0123] Referring toFigure 9 According to some embodiments, a metallization layer 238 is formed over the TFT 236. In some embodiments, the metallization layer 238 includes one or more dielectric layers 240 formed over the TFT 236. Any number of dielectric layers 240 can be contemplated. In some embodiments, at least one of the dielectric layers 240 includes a material having a medium-low or low dielectric constant, such as Si02. The dielectric layers 240 can be formed by a variety of means, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. In some embodiments, the semiconductor structure 100 includes one or more etch stop layers 242 separating the dielectric layers 240. In some embodiments, the etch stop layers 242 stop an etching process between the dielectric layers 240. According to some embodiments, the etch stop layers 242 include a dielectric material having a different etch selectivity than the dielectric layers 240. In some embodiments, at least one of the etch stop layers 242 includes SiN, SiCN, SiCO, and / or CN. The etch stop layers 242 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques.

[0124] In some embodiments, the metallization layer 238 includes one or more conductive structures 246 electrically connected to the source / drain contacts 234A, 234B. In some embodiments, the conductive structures 246 extend through the respective dielectric layers 130. In some embodiments, at least some of the conductive structures 246 include a via portion and a line portion. The line portion is wider than the via portion and has an axial length that extends into the page. In some embodiments, the conductive structures 246 include a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, and / or other suitable materials. Other structures and / or configurations of the conductive structures 246 are within the scope of the present disclosure.

[0125] Referring to Figure 10According to some embodiments, storage elements 244 are formed over metallization layer 238 and connected to source / drain contacts 234B by conductive structures 246. In some embodiments, storage elements 244 are defined by depositing a first layer 244A, depositing a second layer 244B over first layer 244A, and depositing a third layer 244C over second layer 244B and performing an etching process in the presence of a patterned etch mask. Storage elements 244 can include metal-insulator-metal (MIM) storage elements. In some embodiments, storage elements 244 can include additional layers. For DRAM storage elements, first layer 244A and third layer 244C can include conductive materials, such as TiN or Ti, and second layer 244B can be an insulator layer, such as Hf02or a different high-k material. For RRAM storage elements, first layer 244A and third layer 244C can include conductive materials, such as TiN or Ti, and second layer 244B can be an insulator layer that acts as a resistor, such as Hf02or a different high-k material. For MRAM storage elements, first layer 244A can include a pinned layer with a ferromagnetic material, such as a cobalt iron (CoFe) film, a cobalt iron boron (CoFeB) film, or other suitable ferromagnetic material. Second layer 244B can include a tunnel barrier layer (insulator layer), such as MgO. Third layer 244C can include a free layer with a ferromagnetic material, such as a cobalt iron (CoFe) film, a cobalt iron boron (CoFeB) film, or other suitable ferromagnetic material. For FeRAM storage elements, first layer 244A and third layer 244C can include conductive materials, such as TiN or Ti, and second layer 244B can be a ferromagnetic layer, such as HfZrO, HfSiO, or a different ferromagnetic material.

[0126] Referring to Figure 11According to some embodiments, a metallization layer 248 is formed over the storage element 244. In some embodiments, the metallization layer 248 includes one or more dielectric layers 250 formed over the storage element 244. Any number of dielectric layers 250 can be contemplated. In some embodiments, at least one of the dielectric layers 250 includes a material having a medium or low dielectric constant, such as SiO2. The dielectric layers 250 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. In some embodiments, the semiconductor structure 100 includes one or more etch stop layers 252 that separate the dielectric layers 250. In some embodiments, the etch stop layers 252 stop an etching process between the dielectric layers 250. According to some embodiments, the etch stop layers 252 include a dielectric material having a different etch selectivity than the dielectric layers 250. In some embodiments, at least one of the etch stop layers 252 includes SiN, SiCN, SiCO, and / or CN. The etch stop layers 252 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques.

[0127] In some embodiments, the metallization layer 248 includes one or more conductive structures 254, 256 electrically connected to the source / drain contacts 234A, 234B. In one embodiment, the conductive structures 254, 256 extend through the respective dielectric layers 130. In some embodiments, at least some of the conductive structures 254, 256 include a via portion and a line portion. The line portion is wider than the via portion and has an axial length that extends into the page. In some embodiments, the conductive structures 254, 256 include a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, and / or other suitable materials. In some embodiments, the conductive structures 256 contact the second power rail 220.

[0128] In some embodiments, the TFTs 236, the storage elements 244, and the interconnect structures that interconnect the second power rail 220 define a memory device 258 formed over the logic device 101. Rather than bonding a second wafer including the memory device to the device wafer 102, the logic device 101 and the memory device 258 are formed on the device wafer 102.

[0129] Figures 12 to 16 A top gate finFET device 300 is formed according to some embodiments. Referring to Figure 12 From the Figure 3semiconductor structure, a dielectric layer 302 is formed over the power rail 220 and the dielectric layer 216, and contacts 304A, 304B are formed in the dielectric layer 302, according to some embodiments. The dielectric layer 302 can include a material with a medium or low dielectric constant, such as Si02. The dielectric layer 302 is formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. In some embodiments, a trench is formed in the dielectric layer 302, and the trench is filled with a conductive material and planarized to form the contacts 304A, 304B. In some embodiments, the contacts 304A, 304B include a barrier layer, a seed layer, a metal fill layer, and / or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, and / or other suitable materials.

[0130] Referring to Figure 13 , a dielectric layer 306 is formed over the dielectric layer 302 and the contacts 304A, 304B, and a trench 308 is formed in the dielectric layer 306, according to some embodiments. The dielectric layer 306 can include a material with a medium or low dielectric constant, such as Si02. The dielectric layer 306 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, and / or other suitable techniques. The trench 308 is formed by performing an etching process in the presence of a patterned etching mask.

[0131] Referring to Figure 14 , a contact layer is formed in the trench 308 and is patterned to form source / drain contacts 310A, 310B, according to some embodiments. The contact layer can include titanium nitride or other suitable materials. The contact layer can be patterned by performing an etching process in the presence of a patterned etching mask.

[0132] Referring to Figure 15 , a channel layer 312 is formed in the trench 308 over the source / drain contacts 310A, 310B, a gate dielectric layer 314, a gate electrode 316 are formed in the trench 308 over the channel layer 312. According to some embodiments, a gate dielectric layer 314 is formed over the gate dielectric layer 314 to fill the trench 308, and portions of the channel layer 312, the gate dielectric layer 314, and the gate electrode 316 outside the trench 308 are removed. In some embodiments, the channel layer 312 includes amorphous indium gallium zinc oxide (IGZO). The gate dielectric layer 314 can include a high dielectric constant dielectric material. The gate electrode 316 can include the same material as the source / drain contacts 310A, 310B, such as titanium nitride. Portions of the channel layer 312, the gate dielectric layer 314, and the gate electrode 316 outside the trench 308 can be removed by performing a planarization process.

[0133] Referring toFigure 16 According to some embodiments, the process of Figures 9 to 11 is repeated to form metallization layers 238, 248 and storage elements 244. In some embodiments, the top gate FinFET device 300, storage elements 244, and interconnect structures interconnecting the second power rail 220 define a memory device 318 formed above the logic device 101.

[0134] Figures 17 to 20 A bottom gate three-dimensional finFET device 500 is formed according to some embodiments. Referring to Figure 17 According to some embodiments, starting from Figure 4 a semiconductor structure, a gate electrode 402 is formed above the dielectric layer 224 and gate contact 226. In some embodiments, the gate electrode 402 is formed by depositing a layer of gate electrode material and performing an etching process in the presence of a patterned mask. In some embodiments, the gate electrode 402 includes titanium nitride.

[0135] Referring to Figure 18 According to some embodiments, a gate dielectric layer 404 and a channel layer 406 are formed above the gate electrode 402. The gate dielectric layer 404 can include a high dielectric constant dielectric material. In some embodiments, the channel layer 406 includes amorphous indium gallium zinc oxide (IGZO). The channel layer 406 can be patterned by performing an etching process in the presence of a patterned mask.

[0136] Referring to Figure 19 According to some embodiments, a contact layer is formed above the channel layer 406 and is patterned to form source / drain contacts 408A, 408B. The contact layer can be patterned by performing an etching process in the presence of a patterned mask. The source / drain contacts 408A, 408B can include the same material as the gate electrode 402, e.g., titanium nitride.

[0137] Referring to Figure 20 According to some embodiments, the process of Figures 9 to 11 is repeated to form metallization layers 238, 248 and storage elements 244. In some embodiments, the planar FET device 400, storage elements 244, and interconnect structures interconnecting the second power rail 220 define a memory device 410 formed above the logic device 101.

[0138] Figures 21 to 26 A bottom gate three-dimensional finFET device 500 is formed according to some embodiments. Referring to Figure 21 According to some embodiments, starting from Figure 4semiconductor structure, a gate electrode 502 is formed over the dielectric layer 224 and over the gate contact 226. In some embodiments, the gate electrode 502 is formed by depositing a layer of gate electrode material and performing an etching process in the presence of a patterned etch mask to define the fin. In some embodiments, the gate electrode 502 includes titanium nitride.

[0139] Referring to Figure 22 , according to some embodiments, a gate dielectric layer 504 is formed over the gate electrode 502. The gate dielectric layer 504 can include a high dielectric constant dielectric material.

[0140] Referring to Figure 23 , according to some embodiments, trenches 504A, 504B are formed in the gate dielectric layer 504. The trenches 504A, 504B can be formed by performing an etching process in the presence of a patterned etch mask.

[0141] Referring to Figure 24 , according to some embodiments, a channel layer 506 is formed in the trenches 504A, 504B, and source / drain contacts 508A, 508B are formed over the channel layer 506 to fill the trenches 504A, 504B. In some embodiments, the channel layer 506 includes amorphous indium gallium zinc oxide (IGZO). In some embodiments, a planarization process is performed to remove portions of the source / drain contacts 508A, 508B outside of the trenches 504A, 504B. The source / drain contacts 508A, 508B can include the same material as the gate electrode 502, e.g., titanium nitride.

[0142] Referring to Figure 25 , according to some embodiments, portions of the gate dielectric layer 504 and the channel layer 506 are removed. The portions of the gate dielectric layer 504 and the channel layer 506 can be removed by performing an etching process in the presence of a patterned etch mask.

[0143] Referring to Figure 26 , according to some embodiments, the process of Figures 9 to 11 is repeated to form the metallization layers 238, 248 and the storage elements 244. In some embodiments, the bottom gate three-dimensional finFET device 500, the storage elements 244, and the interconnect structure that interconnects with the second power rail 220 define a memory device 510 formed over the logic device 101.

[0144] Figures 27 to 30 are multiple views of a semiconductor structure at various stages of fabrication according to some embodiments. Referring to Figure 27 , according to some embodiments, from Figure 12semiconductor structure 100, source / drain contacts 602A, 602B are formed over dielectric layer 302 and over contacts 304A, 304B. In some embodiments, source / drain contacts 602A, 602B are formed by depositing a layer of contact material and performing an etching process in the presence of a patterned etch mask to define the fins. In some embodiments, source / drain contacts 602A, 602B include titanium nitride.

[0145] Referring to Figure 28 , a channel layer 604 is formed over source / drain contacts 602A, 602B, a gate dielectric layer 606 is formed over channel layer 604, and a gate electrode layer 608 is formed over gate dielectric layer 606. According to some embodiments, gate electrode layer 608 is planarized, and gate electrode layer 608 is planarized. In some embodiments, channel layer 604 includes amorphous indium gallium zinc oxide (IGZO). Gate dielectric layer 606 can include a high dielectric constant dielectric material. Gate electrode layer 608 can include the same material as source / drain contacts 602A, 602B, such as titanium nitride.

[0146] Referring to Figure 29 , according to some embodiments, portions of channel layer 604, gate dielectric layer 606, and gate electrode layer 608 are removed. Portions of channel layer 604, gate dielectric layer 606, and gate electrode layer 608 can be removed by performing an etching process in the presence of a patterned etch mask.

[0147] Referring to Figure 30 , according to some embodiments, the process of Figures 9 to 11 is repeated to form metallization layers 238, 248 and storage elements 244. In some embodiments, top gate three-dimensional finFET devices 600, storage elements 244, and interconnect structures that interconnect with second power rail 220 define a memory device 610 formed over logic device 101.

[0148] Referring to Figure 31 , according to some embodiments, Figure 12 semiconductor structure 100 is illustrated with a second storage element 245 formed in carrier wafer 200. In some embodiments, second storage element 245 has the same configuration as storage element 244. Metallization layers 204 of carrier wafer 200 can have a different configuration to provide interconnects between second storage element 245 and logic device 101. Storage element 245 can be provided in any of the embodiments of Figure 16 , Figure 20 , Figure 26 or Figure 30 .

[0149] Referring to Figure 32According to some embodiments, Figure 12 The semiconductor structure 100 is illustrated with a seal ring 700 adjacent to the memory devices 258 and logic devices 101. The seal ring 700 can include a first portion 700A in the carrier wafer 200 that is connected to a second portion 700B in the device wafer 102. The seal ring 700 can be fabricated in parallel with the various metallization layers. The seal ring 700 can include a barrier layer, a seed layer, and a fill layer, such as copper. The seal ring 700 can be disposed between the memory devices 258 and the logic devices 101. Figure 16 、 Figure 20 、 Figure 26 、 Figure 30 or Figure 31 in any of the embodiments.

[0150] The use of IGZO material for the channel layer of the transistors 236, 300, 400, 500, 600 in the memory devices 258, 318, 410, 510, 610 eliminates the need for a dopant activating anneal, providing a low thermal budget process that is compatible with BEOL processing. The memory devices can be devices such as resistive random access memory (RRAM) devices, dynamic random access memory (DRAM) devices, magnetic random access memory (MRAM) devices, ferroelectric random access memory (FeRAM) devices, or some other memory technology. The use of hybrid bonding with the conductive structures in the carrier wafer 200 improves heat transfer and potentially performance. Dual side memory can be provided by including additional memory devices in the carrier wafer 200.

[0151] A semiconductor structure includes a logic device, a first contact connected to the logic device, a first power rail on the logic device and connected to the logic device, and a second power rail on the logic device. A transistor has a channel region including indium, gallium, zinc, and oxygen on the second power rail and connected to the second power rail. In one or more embodiments, the semiconductor structure includes a first storage element connected between the second power rail and the transistor. In some embodiments, the first storage element includes a first conductive layer, an insulating layer on the first conductive layer, and a second conductive layer. In some embodiments, the first storage element includes at least one of a resistive random access memory storage element, a dynamic random access memory storage element, a magnetic random access memory storage element, or a ferroelectric random access memory storage element. In one or more embodiments, the transistor includes at least one of a bottom gate fin field effect transistor device, a top gate fin field effect transistor device, or a planar device. In one or more embodiments, the semiconductor structure includes a seal ring adjacent to the logic device and the transistor. In one or more embodiments, the semiconductor structure includes a second storage element under the logic device.

[0152] A method of forming a semiconductor structure includes forming logic devices on a device wafer; inverting the device wafer; forming backside contacts connecting the logic devices; forming a first power rail connecting the backside contacts; forming a second power rail; and forming memory devices on the second power rail. Forming the memory devices includes forming transistors including a channel layer having indium, gallium, zinc, and oxygen; forming first storage elements connecting the transistors; and connecting the second power rail to the memory devices. In one or more embodiments, forming the logic devices includes forming the logic devices on the device wafer. The method of forming the semiconductor structure includes bonding a carrier wafer to the device wafer. Forming the memory devices includes forming the memory devices on the device wafer after bonding the carrier wafer to the device wafer. In some embodiments, bonding the carrier wafer to the device wafer includes accepting first dielectric layers within the carrier wafer to second dielectric layers within the device wafer and bonding first conductive structures embedded in the first dielectric layers to second conductive structures embedded in the second dielectric layers. In some embodiments, the method of forming the semiconductor structure includes forming second storage elements within the carrier wafer prior to bonding the carrier wafer to the device wafer. In some embodiments, the method of forming the semiconductor structure includes forming a seal ring adjacent to the logic devices and the memory devices, where a first portion of the seal ring is within the carrier wafer and a second portion of the seal ring is within the device wafer. In one or more embodiments, forming the first storage elements includes forming a first conductive layer; forming an insulating layer on the first conductive layer; and forming a second conductive layer on the insulating layer. In some embodiments, forming the insulating layer includes forming at least one of a dielectric material, a resistive material, or a ferromagnetic material. In some embodiments, at least one of forming the first conductive layer or forming the second conductive layer includes forming a ferromagnetic material.

[0153] A semiconductor structure includes a carrier wafer and a device wafer. The carrier wafer includes a substrate layer, a first dielectric layer, and a first conductive layer embedded in the first dielectric layer. The device wafer includes a logic device connected to the first conductive layer, a backside contact connected to the logic device, and a second dielectric layer under the logic device and bonded to the first dielectric layer of the carrier wafer. A third dielectric layer is over the logic device and a first power rail is embedded in the third dielectric layer and connected to the logic device. A fourth dielectric layer is over the logic device and a second power rail is embedded in the fourth dielectric layer. A memory device is on and connected to the second power rail. The memory device includes a transistor having a channel layer including indium, gallium, zinc, and oxygen. In one or more embodiments, the memory device includes a first storage element connected between the second power rail and the transistor. In some embodiments, the first storage element includes a first conductive layer, an insulating layer over the first conductive layer, and a second conductive layer over the insulating layer. In one or more embodiments, the carrier wafer includes a second storage element. In one or more embodiments, the semiconductor structure includes a seal ring adjacent to the logic device and the memory device. A first portion of the seal ring is within the carrier wafer. A second portion of the seal ring is within the device wafer.

[0154] A semiconductor structure includes a logic device, a backside contact connected to the logic device, a first power rail connected to the backside contact, a second power rail, and a memory device. The memory device is on and connected to the second power rail. The memory device includes a transistor and a storage element. The transistor has a channel region. The channel region includes indium, gallium, zinc, and oxygen. The storage element is connected to the transistor. In one or more embodiments, the semiconductor structure includes a device wafer, a carrier wafer, and a seal ring. The logic device and the memory device are on the device wafer. The carrier wafer is bonded to the device wafer. The seal ring is adjacent to the logic device and the memory device. A first portion of the seal ring is within the carrier wafer and a second portion of the seal ring is within the device wafer.

[0155] The foregoing summary of features of several embodiments has been presented for the purposes of providing those of ordinary skill in the art with a better understanding of the aspects of the disclosure. It will be understood by those of ordinary skill in the art that they can readily apply the disclosure as a basis for the designing or modifying other processes and structures for carrying out the same purposes and / or for the same advantages herein introduced. Those of ordinary skill in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

[0156] Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

[0157] The present disclosure provides various operations for embodiments. The order in which some or all of the operations are described is not intended to be construed as a limitation, and any number of the described operations can be combined in any order and / or omitted. Additional operations and / or operations that are not described can also be incorporated.

[0158] It will be understood that the layers, components, elements, etc. described herein are shown with particular dimensions relative to one another, such as structural dimensions and / or orientations, for example, in some embodiments, the actual dimensions of the components described above can be substantially different than the dimensions shown in the present disclosure for the sake of simplicity and ease of understanding. Additionally, the present disclosure contemplates various techniques for forming layers, components, elements, etc., such as implantation techniques, doping techniques, spin-on techniques, sputtering techniques (e.g., magnetron or ion beam sputtering), growth techniques (e.g., thermal growth), and / or deposition techniques, such as chemical vapor deposition (CVD).

[0159] Also, as used in the present application, the term "exemplary" means serving as an example, instance, or illustration, and not necessarily as a preferred or advantageous implementation. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, use of "one" or "the" as in "one of the" or "the of the" is generally construed to mean "one or more" unless specifically stated otherwise or clear from context to mean a singular form. Moreover, as used in the present application, the following phrases are also intended to have the following meanings: "including" "includes" "included" and variations thereof mean "including without limitation"; "comprising" "comprises" "comprised of" and variations thereof mean "comprising without limitation"; and "coupled" means directly or indirectly connected, whether mechanically, electrically, logically, or otherwise.

[0160] While the present disclosure has been shown and described with reference to one or more implementations, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure. The disclosure includes all such modifications and variations and is limited only by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a logic device; a first contact connected to the logic device; a first power rail on and connected to the logic device; a second power rail on the logic device; and a transistor having a channel region comprising amorphous indium gallium zinc oxide (IGZO) on and connected to the second power rail. Comprising:

2. The semiconductor structure of claim 1, wherein, a first storage element connected between the second power rail and the transistor. The first storage element comprises:

3. The semiconductor structure of claim 2, wherein, a first conductive layer; an insulating layer on the first conductive layer; and a second conductive layer on the insulating layer. Comprising:

4. The semiconductor structure of claim 1, wherein, a sealing ring adjacent to the logic device and the transistor. Comprising:

5. The semiconductor structure of claim 1, wherein, a second storage element under the logic device. Comprising:

6. A semiconductor structure, characterized by a carrier wafer comprising: a substrate layer; a first dielectric layer; and a first conductive layer embedded in the first dielectric layer; and a device wafer comprising: a logic device connected to the first conductive layer; a backside contact connected to the logic device; a second dielectric layer under the logic device and bonded to the first dielectric layer of the carrier wafer; a third dielectric layer on the logic device; a first power rail embedded in the third dielectric layer and connected to the logic device; a fourth dielectric layer on the logic device; a second power rail embedded in the fourth dielectric layer; and a memory device on and connected to the second power rail, wherein the memory device comprises a transistor having a channel layer comprising amorphous indium gallium zinc oxide (IGZO). The carrier wafer comprises:

7. The semiconductor structure of claim 6, wherein, a second storage element. Comprising:

8. The semiconductor structure of claim 6, wherein, a sealing ring adjacent to between the logic device and the memory device, wherein: a first portion of the sealing ring is within the carrier wafer; and a second portion of the sealing ring is within the device wafer. Comprising: a logic device; 9. A semiconductor structure, characterized by a backside contact connected to the logic device; a first power rail connected to the backside contact; a second power rail; and a memory device on and connected to the second power rail, wherein the memory device comprises: a transistor having a channel region comprising amorphous indium gallium zinc oxide (IGZO); and a storage element connected to the transistor. Comprising: a device wafer, wherein the logic device and the memory device are on the device wafer; a carrier wafer bonded to the device wafer; and a sealing ring adjacent to between the logic device and the memory device, wherein a first portion of the sealing ring is within the carrier wafer and a second portion of the sealing ring is within the device wafer.

10. The semiconductor structure of claim 9, wherein, ​ ​ ​ ​ ​

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