Semiconductor device

Abstract

Embodiments of the present disclosure relate to a semiconductor device having a lower plurality of source / drain regions to reduce channel resistance (Rch) and source / drain contact resistance loads. The semiconductor device includes a semiconductor substrate, a semiconductor channel, an epitaxial source / drain region, and a buried epitaxial layer. A semiconductor channel is disposed over a top surface of the semiconductor substrate. An epitaxial source / drain region is connected to the semiconductor channel, wherein the epitaxial source / drain region includes sidewalls connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate. A buried epitaxial layer is disposed below the epitaxial source / drain region, where a top surface of the buried epitaxial layer conforms to a bottom surface of the epitaxial source / drain region, and the top surface of the buried epitaxial layer is disposed below a top surface of the semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components. To a large extent, the improvement in integration density has come from a continual reduction in the minimum feature size, allowing more components to be integrated into a given chip area. As the minimum feature size is reduced, however, the effects of undesirable physical and electrical phenomena such as leakage, parasitic capacitance, and resistance degradation can become significant maladies. Therefore, there is a need for addressing these issues. SUMMARY

[0003] In some embodiments, the present disclosure provides a semiconductor device including a semiconductor substrate, a semiconductor channel, an epitaxial source / drain region, and a buried epitaxial layer. The semiconductor channel is disposed over a top surface of the semiconductor substrate. The epitaxial source / drain region is connected to the semiconductor channel, wherein the epitaxial source / drain region includes a sidewall connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate. The buried epitaxial layer is disposed below the epitaxial source / drain region, wherein a top surface of the buried epitaxial layer conforms to the bottom surface of the epitaxial source / drain region and the top surface of the buried epitaxial layer is disposed below the top surface of the semiconductor substrate.

[0004] In some embodiments, the present disclosure provides a semiconductor device including a semiconductor substrate, two or more semiconductor channel layers, two or more internal spacers, an epitaxial source / drain region, and a buried epitaxial layer. The two or more semiconductor channel layers are vertically stacked over a top surface of the semiconductor substrate. The two or more internal spacers are alternately stacked with the two or more semiconductor channel layers. The epitaxial source / drain region has a bottom surface extending below the top surface of the semiconductor substrate. The buried epitaxial layer is disposed below the bottom surface of the epitaxial source / drain region, wherein a top surface of the buried epitaxial layer is disposed below the top surface of the semiconductor substrate.

[0005] In some embodiments, the present disclosure provides a semiconductor device including a semiconductor substrate, a semiconductor channel, a buried epitaxial layer, and an epitaxial source / drain region. The semiconductor channel is disposed over a top surface of the semiconductor substrate. The buried epitaxial layer is disposed in the semiconductor substrate, wherein a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate. The epitaxial source / drain region is over the buried epitaxial layer, wherein a bottom surface of the epitaxial source / drain region is below the top surface of the semiconductor substrate, the epitaxial source / drain region has a first width above the top surface of the semiconductor substrate and a second width below the top surface of the semiconductor substrate, the second width is greater than the first width. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be better understood when read in conjunction with the following detailed description and with reference to the drawings. It is noted that, for the sake of brevity, various features of the drawings can not be to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity.

[0007] Figures 1A-1Q A semiconductor device according to embodiments of the present disclosure is schematically illustrated;

[0008] Figure 2 A flowchart of a method of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0009] Figures 3A-3J Various stages of manufacturing a semiconductor device according to embodiments of the present disclosure are schematically illustrated;

[0010] Figure 4 A flowchart of a method of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0011] Figures 5A-5C Various stages of manufacturing a semiconductor device according to embodiments of the present disclosure are schematically illustrated;

[0012] Figure 6 A flowchart of a method of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0013] Figures 7A-7D Various stages of manufacturing a semiconductor device according to embodiments of the present disclosure are schematically illustrated.

[0014]

Symbol Explanation

[0015] 1D: rectangular region

[0016] 1K: rectangular region

[0017] 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10m, 10n, 10o: semiconductor device

[0018] 12: semiconductor substrate

[0019] 12f: top surface

[0020] 12M: mesa portion

[0021] 12s: sidewall

[0022] 16: semiconductor channel layer

[0023] 16t: top surface

[0024] 16s: sidewall

[0025] 18: stack

[0026] 20: fin

[0027] 22: isolation layer

[0028] 30: sidewall spacer

[0029] 32: inner spacer

[0030] 36: buried epitaxial layer

[0031] 36b: bottom surface

[0032] 36t: top surface

[0033] 38: bottom dielectric layer

[0034] 38t: top surface

[0035] 40: epitaxial source / drain region

[0036] 40b: bottom horizontal plane

[0037] 40p: bottom profile

[0038] 40P: bottom profile

[0039] 40t: top surface

[0040] 40Pc: central portion

[0041] 40Ps: side portion

[0042] 40Xc: length

[0043] 40Xs: length

[0044] 41: first epitaxial source / drain layer

[0045] 41B: bottom portion

[0046] 41Bt: top surface

[0047] 41C: channel portion

[0048] 41S: sidewall portion

[0049] 42: contact etch stop layer (CESL)

[0050] 43: bulk epitaxial source / drain layer

[0051] 44: interlayer dielectric (ILD) layer

[0052] 50: gate structure

[0053] 52: source / drain contact

[0054] 54: silicide layer

[0055] 100: method

[0056] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 311, 502: operation

[0057] 200: semiconductor device

[0058] 210: substrate

[0059] 210f: front surface

[0060] 212: well portion

[0061] 212c: cavity

[0062] 212s: sidewall

[0063] 212sp: sidewall

[0064] 212v: cavity

[0065] 214: first semiconductor layer

[0066] 216: second semiconductor layer

[0067] 218: channel portion

[0068] 218S: semiconductor stack

[0069] 220: semiconductor fin

[0070] 222: isolation layer

[0071] 224: sacrificial gate dielectric layer

[0072] 226: sacrificial gate electrode layer

[0073] 228: sacrificial gate structure

[0074] 230: gate sidewall spacer

[0075] 232: inner spacer

[0076] 234: source / drain recess

[0077] 234b: bottom

[0078] 236: buried epitaxial layer

[0079] 236c: center layer

[0080] 236f: front surface

[0081] 236s: side wall layer

[0082] 236t: top surface

[0083] 236tc: central portion

[0084] 236ts: side wall portion

[0085] 238: bottom dielectric layer

[0086] 239: opening

[0087] 240: epitaxial source / drain region

[0088] 241: first epitaxial source / drain layer

[0089] 241B: bottom portion

[0090] 241C: channel portion

[0091] 242: contact etch stop layer (CESL)

[0092] 243: bulk epitaxial source / drain layer

[0093] 244: interlayer dielectric (ILD) layer

[0094] 246: gate dielectric layer

[0095] 248: gate electrode layer

[0096] 250: replacement gate structure

[0097] 252: source / drain contact

[0098] 254: contact hole

[0099] 300: method

[0100] 400: semiconductor device

[0101] 500: method

[0102] 600: semiconductor device

[0103] 614: sacrificial layer

[0104] 618: stack

[0105] 620: fin structure

[0106] D 36 : depth

[0107] D 40 : drop height

[0108] D 43 : drop distance

[0109] E 40 :distance

[0110] H 12 :height

[0111] H 16 :passage height

[0112] H 36 :height

[0113] H 40 :height

[0114] W 12 :width

[0115] W 40 :width

[0116] W 41Ba :second width

[0117] W 41Bu :first width

[0118] W 43 :width

[0119] θ1, θ2: angle DETAILED DESCRIPTION

[0120] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Each of the following described embodiments and / or examples and / or configurations is provided merely as one or more specific examples of various modes by which the disclosure can be implemented. Of course, various modifications and changes can be made to these embodiments, by those skilled in the art, without departing from the spirit and scope of the disclosure, which is set forth in the appended claims. Moreover, although specific configurations can be described herein as being used in a particular example, such configurations can be used in other examples, and / or configurations can be modified to be used in other examples. For example, a first feature described above or over a second feature in the following description can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features are formed between the first and second features, such that the first and second features can not be in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0121] In addition, for the purpose of convenience and brevity, spatially relative terms, such as "under", "below", "lower", "on", "above", "upper", "top", "bottom", and the like, can be used herein for describing an element's or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0122] The foregoing generally outlines some aspects of the implementations described in this disclosure. While some implementations described herein are described in the context of nanosheet channel field-effect transistors (FETs), implementation of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, fin FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. One of ordinary skill in the art will readily recognize other modifications that can be made to the implementations within the scope of the present disclosure. In addition, while method implementations can be described by a particular order, various other method implementations can be performed in any reasonable order, and can include fewer or more steps than those described herein. In this disclosure, source / drain regions refer to source and / or drain. Source and drain are used interchangeably.

[0123] The fins can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) can be used to pattern the fins. Generally, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes, allowing for the creation of patterns with, for example, smaller pitch than is obtainable using a single direct photolithography process.

[0124] Implementations of the present disclosure relate to a semiconductor device including a nanosheet channel region with reduced channel resistance (R ch ) and reduced source / drain contact resistance loading. In particular, implementations of the present disclosure provide a GAA semiconductor device for source / drain epitaxial regions in P-type FETs with reduced channel resistance and contact resistance loading. Implementations of the present disclosure provide a GAA device including a source / drain region having a bottom surface that extends below a top surface of a substrate on which a channel stack is formed. Implementations of the present disclosure reduce channel resistance, increase mobility, and reduce resistance loading in source / drain contacts by reducing the source / drain region, increasing the volume of the source / drain region, introducing additional stress to the source / drain region, improving the uniformity of the top surface of the source / drain region.

[0125] In some embodiments, the GAA device includes a buried epitaxial layer. Source / drain regions are formed over the buried epitaxial layer. The location and profile of the bottom surface of the source / drain regions conform to the top surface of the buried epitaxial layer. In some embodiments, the top surface of the buried epitaxial layer can be controlled by selecting appropriate epitaxial growth parameters. In some embodiments, a bottom dielectric film can be formed between the buried epitaxial layer and the source / drain regions.

[0126] Figure 1A A semiconductor device 10 according to embodiments of the disclosure is schematically illustrated. Figure 1A A cross-sectional view of a semiconductor device 10 according to the disclosure.

[0127] The semiconductor device 10 is a GAA device including semiconductor channel layers 16 formed between epitaxial source / drain regions 40. Gate structures 50 are formed over and around the semiconductor channel layers 16. The semiconductor device 10 is formed by depositing a stack 18 including a plurality of semiconductor channel layers 16 formed over a top surface 12f of a semiconductor substrate 12, patterning the stack 18 and the semiconductor substrate 12 into a plurality of fins 20, forming a plurality of sacrificial gate structures over the fins 20, recessing the fins 20 outside the sacrificial gate structures to form the epitaxial source / drain regions 40, and replacing the sacrificial gate structures with the gate structures 50. A plurality of sidewall spacers 30 are disposed on sidewalls of the gate structures 50. An inner spacer 32 can be disposed between the gate structures 50 and the epitaxial source / drain regions 40.

[0128] In some embodiments, a bottom profile 40p of the epitaxial source / drain regions 40 is lower than the top surface 12f of the semiconductor substrate 12. In other words, at least a portion of the bottom profile 40p of the epitaxial source / drain regions 40 extends downward in the z-direction to a level between mesa portions 12M of the semiconductor substrate 12. The mesa portions 12M refer to the well portions of the fins 20 that are formed from the semiconductor substrate 12 during formation of the fins 20. The bottom profile 40p of the epitaxial source / drain regions 40 has a bottom level 40b.

[0129] A buried epitaxial layer 36 is disposed between the epitaxial source / drain regions 40. The buried epitaxial layer 36 can be an epitaxial semiconductor layer formed in a recess in the semiconductor substrate 12 between the mesa portions 12M. The buried epitaxial layer 36 is in contact with a shallow trench isolation layer (not shown) and / or the sidewall spacers 30. In some embodiments, the buried epitaxial layer 36 is an epitaxial semiconductor material formed from the semiconductor substrate 12. The buried epitaxial layer 36 can be a transition layer between the crystalline structure of the semiconductor substrate 12 and the epitaxial source / drain regions 40. In some embodiments, the buried epitaxial layer 36 can serve as an alignment feature for forming backside source / drain contacts.

[0130] Epitaxial source / drain regions 40 are formed from semiconductor channel layer 16 and a top surface 36t of buried epitaxial layer 36. In some embodiments, top surface 36t of buried epitaxial layer 36 is formed to achieve a desired bottom profile 40p of epitaxial source / drain regions 40. Top surface 36t is formed below top surface 12f of semiconductor substrate 12, thus enabling epitaxial source / drain regions 40 to be formed below top surface 12f and increasing the volume of epitaxial source / drain regions 40. The increased volume of epitaxial source / drain regions 40 increases the compressive force F on semiconductor channel layer 16. The increased compressive force F causes compressive strain in semiconductor channel layer 16, which in turn increases the mobility of the channel region. Semiconductor channel layer 16 is separated by interior spacers 32 and surrounded by gate structure 50. Gate structure 50 can be a gate stack including an interface layer, a gate dielectric layer, and a gate electrode layer. The gate electrode layer can further include one or more work function layers and one or more metal fill layers. Sidewall spacers 30 are disposed between epitaxial source / drain regions 40 and gate structure 50.

[0131] Semiconductor device 10 can further include source / drain contacts 52 disposed on epitaxial source / drain regions 40. A silicide layer 54 can be formed between source / drain contacts 52 and epitaxial source / drain regions 40 to facilitate electrical connection therebetween. A contact etch stop layer (CESL) 42 is deposited over epitaxial source / drain regions 40 to protect epitaxial source / drain regions 40 during formation. An interlayer dielectric (ILD) layer 44 is deposited over CESL 42 to provide electrical isolation to source / drain contacts 52 and epitaxial source / drain regions 40.

[0132] During operation, when a gate bias greater than a threshold voltage is applied to gate structure 50, a conductive channel is formed within semiconductor channel layer 16. If an appropriate bias is applied to epitaxial source / drain regions 40 through source / drain contacts 52, current can flow between epitaxial source / drain regions 40 through the channel formed within semiconductor channel layer 16. Under the above operating conditions, the portion of gate structure 50 closest to mesa portion 12M can form a parasitic FET. If epitaxial source / drain regions 40 are in physical contact with mesa portion 12M, unwanted leakage current can flow between epitaxial source / drain regions 40 via mesa portion 12M. Bottom dielectric layer 38 in semiconductor device 10 provides sufficient electrical isolation and leakage current suppression for epitaxial source / drain regions 40.

[0133] In some embodiments, the semiconductor device 10 is formed on a bulk semiconductor substrate 12, e.g., as opposed to a silicon-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 12 includes crystalline silicon (Si) or another elemental semiconductor, e.g., germanium (Ge). Alternatively, the semiconductor substrate 12 can include (i) a compound semiconductor, e.g., silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (ii) an alloy semiconductor, e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or (iv) a combination thereof.

[0134] The stack 18 can include a plurality of semiconductor channel layers 16 alternating with sacrificial layers (not shown). In some embodiments, the number of semiconductor channel layers 16 is between 1 and 6. The semiconductor channel layers 16 can be formed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor channel layers 16 can include the same material as the semiconductor substrate 12. In some embodiments, the semiconductor channel layers 16 can include a different material than the semiconductor substrate 12. In some embodiments, the semiconductor channel layers 16 and the sacrificial semiconductor layers are made of materials having different lattice constants. In some embodiments, the sacrificial layers include epitaxially grown silicon germanium (SiGe) layers and the semiconductor channel layers 16 include epitaxially grown silicon (Si) layers. In some embodiments, the sacrificial layers can be dielectric layers, e.g., silicon oxide. Alternatively, in some embodiments, either of the semiconductor channel layers 16 and the sacrificial layers can include other materials, e.g., Ge, a compound semiconductor, e.g., SiC, GeAs, GaP, InP, InAs, and / or InSb, an alloy semiconductor, e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or a combination thereof.

[0135] In some embodiments, each semiconductor channel layer 16 has a channel height H 16 In some embodiments, the semiconductor channel layers 16 in the stack 18 have a channel height H 16It is uniform. In some embodiments, the semiconductor channel layer 16 in the stack 18 is at the channel height H. 16 There have been changes.

[0136] In some embodiments, for p-type devices, the epitaxial source / drain region 40 may include boron-doped silicon-germanium (SiGe), boron-doped germanium (Ge), boron-doped germanium-tin (GeSn), or combinations thereof. In some embodiments, for n-type devices, the epitaxial source / drain region 40 may include arsenic-doped or phosphorus-doped silicon (Si), carbon-doped silicon (Si:C), or combinations thereof.

[0137] In some implementations, the epitaxial source / drain region 40 may include two or more epitaxial growth layers. For example, as... Figure 1A As shown, the epitaxial source / drain region 40 may include a first epitaxial source / drain layer 41 and a bulk epitaxial source / drain layer 43. The first epitaxial source / drain layer 41 grows from a plurality of sidewalls 16s of the semiconductor channel layer 16 and the top surface 36t of the buried epitaxial layer 36. The first epitaxial source / drain layer 41 is separated from the exposed semiconductor surface. For example, the first epitaxial source / drain layer 41 includes a plurality of channel portions 41C grown from the plurality of sidewalls 16s of the semiconductor channel layer 16 and a bottom portion 41B grown from the buried epitaxial layer 36. The first epitaxial source / drain layer 41 is grown to a desired thickness to achieve high-quality crystal growth in subsequent bulk epitaxial growth. Due to the different surface orientations, materials and / or locations of the respective seed layers, the channel portions 41C and the bottom portion 41B may have different physical properties, such as thickness, shape or surface orientation. In some implementations, the bottommost channel portion 41C may be merged with the bottom portion 41B.

[0138] The first epitaxial source / drain layer 41 may comprise one or more layers of Si, SiP, SiC, and SiCP for an NFET, or Si, SiGe, and Ge for a PFET. For a PFET, a p-type dopant, such as boron (B), may also be included in the first epitaxial source / drain layer 241. For an NFET, an n-type dopant, such as arsenic (As), phosphorus (P), carbon (C), or a combination thereof, may also be included in the first epitaxial source / drain layer 41.

[0139] In some embodiments, the semiconductor device 10 is a p-type device, and the first epitaxial source / drain layer 41 comprises Si or SiGe having a p-type dopant (e.g., B or Ga). In some embodiments, the first epitaxial source / drain layer 41 may comprise Si 1-x Ge x B, where x is in the range of 0 to 0.5 and the concentration of B is 1E19 atoms*cm. -3With 3E21 atoms *cm -3 Within the range between.

[0140] A bulk epitaxial source / drain layer 43 is formed above the first epitaxial source / drain layer 41. The bulk epitaxial source / drain layer 43 fills the source / drain groove. Although Figure 1A Only one layer is shown, but the bulk epitaxial source / drain layer 43 may include two or more layers. The bulk epitaxial source / drain layer 43 is epitaxially grown from the first epitaxial source / drain layer 41. The bulk epitaxial source / drain layer 43 has a higher dopant concentration than the first epitaxial source / drain layer 41. In some embodiments, the composition of the bulk epitaxial source / drain layer 43 is also different from that of the first epitaxial source / drain layer 41. The bulk epitaxial source / drain layer 43 and the first epitaxial source / drain layer 41 have different crystal structures. For NFETs, the bulk epitaxial source / drain layer 43 may include one or more layers of Si, SiP, SiC, and SiCP, or for PFETs, it may include Si, SiGe, and Ge. For PFETs, p-type dopants, such as boron (B), are also included in the bulk epitaxial source / drain layer 43. For NFETs, n-type dopants, such as arsenic (As), phosphorus (P), carbon (C), or combinations thereof, are included in the bulk epitaxial source / drain layer 43.

[0141] In some embodiments, the semiconductor device 10 is a p-type device, and the bulk epitaxial source / drain layer 43 comprises Si or SiGe with a p-type dopant (e.g., B or Ga). In some embodiments, the bulk epitaxial source / drain layer 43 may be Si 1-x Ge x B, where x is in the range of 0.3 and 0.8 and the concentration of B is 1E20 atoms*cm. -3 and 5E21 atoms *cm -3 Within the range between.

[0142] In some embodiments, the epitaxial source / drain region 40 has a width W along the x-direction in the range of about 9 nm to about 32 nm. 40 In some embodiments, the epitaxial source / drain region 40 has a source / drain height H along the z-direction in the range of about 20 nm to about 105 nm. 40 Because the bottom portion of the epitaxial source / drain region 40 grows from the buried epitaxial layer 36, which is located below the top surface 12f of the mesa portion 12M or the bottom of the stack 18, with a height H. 40 Increase. In some implementations, the drop height D of the epitaxial source / drain region 40 is increased. 40 Within the range of approximately 5nm to approximately 20nm, the drop height D 40The height difference D is defined by the distance between the top surface 12f of the mesa portion 12M and the bottom horizontal plane 40b of the epitaxial source / drain region 40. In some embodiments, the height difference D... 40 With source / drain height H 40 The ratio is in the range of approximately 5% to approximately 50%.

[0143] In some embodiments, the buried epitaxial layer 36 is an undoped semiconductor layer. For example, the buried epitaxial layer 36 may include Si, SiB, or Si 1-x Ge x or Si 1-x Ge x B, where x is in the range of 0 to 0.5, and the concentration of B is in the range of 1E19 atoms*cm. -3 and 3E21 atoms *cm -3 Within the range of approximately 0 nm to approximately 50 nm. In some embodiments, the embedded epitaxial layer 36 has a height H along the z-direction within the range of approximately 0 nm to approximately 50 nm. 36。 In some embodiments, the depth D of the embedded epitaxial layer 36 36 Within the range of approximately 3nm to approximately 50nm, depth D 36 It is defined by the distance between the top surface 12f of the mesa portion 12M and the bottom surface 36b of the embedded epitaxial layer 36.

[0144] In some embodiments, the gate structure 50 occupies the middle portion of the semiconductor channel layer 16. The edge portions of the semiconductor channel layer 16 are covered by internal spacers 32. Sidewall spacers 30 are disposed on both sides of the gate structure 50, excluding the spaces between the semiconductor channel layers 16. In some embodiments, the sidewall spacers 30 and the internal spacers 32 may include nitrides, such as silicon nitride (Si3N4 or "SiN"), silicon carbonitride (SiCN), and silicon carbonitride oxide (SiCON). The internal spacers 32 are interposed between the gate structure 50 and the epitaxial source / drain region 40 to electrically isolate the gate structure 50 from the epitaxial source / drain region 40.

[0145] The silicide layer 54 inserted between the source / drain contact 52 and the epitaxial source / drain region 40 may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), platinum silicide (PtSi), or a suitable silicide material. By way of example and not limitation, each silicide layer 54 may have a thickness between about 4 nm and about 8 nm. In some embodiments, the silicide layer reduces the contact resistance between the source / drain contact 52 and the epitaxial source / drain region 40.

[0146] In some embodiments, the ILD layer 44 comprises one or more layers of dielectric material. In some embodiments, the ILD layer 44 is a silicon oxide-based dielectric having nitrogen, hydrogen, carbon, or a combination thereof. According to some embodiments, the ILD layer 44 provides electrical isolation and structural support for the gate structure 50, the source / drain contacts 52, and the epitaxial source / drain regions 40.

[0147] like Figure 1A As shown, the epitaxial source / drain region 40 extends into the mesa portion 12M in the semiconductor substrate 12, thereby increasing the volume of the epitaxial source / drain region 40 without overgrowing on the top surface 16t of the topmost semiconductor channel layer 16. In some embodiments, the top surface 40t of the epitaxial source / drain region 40 may be located above the top surface 16t of the topmost semiconductor channel layer 16, separated by a distance E. 40 In some implementations, the distance E 40 Within the range of approximately 10nm to 15nm, the relatively low top profile of the epitaxial source / drain region 40 enables process uniformity during the formation of the source / drain contact 52, thereby reducing the resistive load between the epitaxial source / drain region 40 and the source / drain contact 52.

[0148] Figure 1B Semiconductor device 10a is schematically shown according to embodiments of this disclosure. Semiconductor device 10a is similar to semiconductor device 10, except that in semiconductor device 10a, the first epitaxial source / drain layer 41 includes a plurality of sidewalls 12s from the mesa portion 12M and a bottom portion 41B grown into the top surface 36t of the buried epitaxial layer 36. As... Figure 1B As shown, the bottom portion 41B contacts the top surface 36t of the embedded epitaxial layer 36 and the two sidewalls 12s of the mesa portion 12M. In some embodiments, the height H of the sidewalls 12s along the z-direction is... 12 It contacts the bottom portion 41B. In some embodiments, the height H 12 Within the range of approximately 0 nm to approximately 20 nm. In some embodiments, the channel portion 41C in the semiconductor device 10a is a plurality of separate portions that do not merge with each other or with the bottom portion 41B.

[0149] Figure 1C and Figure 1D A semiconductor device 10b according to an embodiment of this disclosure is schematically shown. Semiconductor device 10b is similar to semiconductor device 10, except that in semiconductor device 10b, the bottom profile 40P is a rounded profile. Figure 1D yes Figure 1C A magnified view of the rectangular region 1D in the image. (See image below.) Figure 1DAs shown, the bottom profile 40P is a substantially continuous curve. In some embodiments, the bottom profile 40P can include two side portions 40Ps and a central portion 40Pc. Each side portion 40Ps can start near the top surface 12f of the substrate and slope downward. The central portion 40Pc is substantially level with the x-axis. The side portions 40Ps and the central portion 40Pc form an angle Θ1. In some embodiments, the angle Θ1 is in a range between about 120° and about 180°. o The side portions 40Ps have a length 40Xs along the x-direction. The central portion 40Pc has a length 40Xc along the x-direction. In some embodiments, a ratio of the length 40Xs to the length 40Xc is in a range between about 0.1 and about 0.6.

[0150] Figure 1E A semiconductor device 10c is schematically shown in accordance with an embodiment of the present disclosure. The semiconductor device 10c is similar to the semiconductor device 10b, except that in the semiconductor device 10c, the bottom profile 40P has an angled profile. In some embodiments, the side portions 40Ps and the central portion 40Pc of the bottom profile 40P are substantially linear. Each side portion 40Ps can start near the top surface 12f of the substrate and slope downward. In some embodiments, the side portions 40Ps and the central portion 40Pc form a half-hexagon. In some embodiments, a ratio of the length 40Xs to the length 40Xc is in a range between about 0.1 and about 0.6.

[0151] Figure 1F A semiconductor device 10d is schematically shown in accordance with an embodiment of the present disclosure. The semiconductor device 10d is similar to the semiconductor device 10c, except that in the semiconductor device 10d, the bottom profile 40P is substantially flat. In some embodiments, the bottom profile 40P can be a substantially flat surface disposed below the top surface 12f of the semiconductor substrate 12. Portions of the sidewalls 12s are exposed to the epitaxial source / drain region 40 and in contact with the bottom portion 41B of the first epitaxial source / drain layer 41. The bottom portion 41B of the first epitaxial source / drain layer 41 merges with the channel portion 41C grown from the bottommost semiconductor channel layer 16.

[0152] Figure 1G A semiconductor device 10e is schematically shown in accordance with an embodiment of the present disclosure. The semiconductor device 10e is similar to the semiconductor device 10a shown. In the semiconductor device 10e, portions of the mesa 12M of the sidewalls 12s are exposed to the epitaxial source / drain region 40 and in contact with the bottom portion 41B of the first epitaxial source / drain layer 41. The bottom profile 40P is rounded. In some embodiments, the bottom profile 40P can be similar to the bottom profile 40P of the semiconductor device 10a. Figure 1B Figure 1C ​The bottom profile 40P in the semiconductor device 10b shown. The bottom portion 41B of the first epitaxial source / drain layer 41 is not merged with the channel portion 41C. Because the bottom profile 40P is rounded, the bottom horizontal plane 40b is substantially lower than the exposed sidewall 12s. In some embodiments, the drop height D 40 The height H of the exposed sidewall is greater than 12s. 12 In some implementations, height H 12 With height difference D 40 The ratio is in the range of 0 to 1.0, for example, between about 0.3 and about 0.8.

[0153] Figure 1H A semiconductor device 10f is schematically shown according to an embodiment of this disclosure. The semiconductor device 10f and... Figure 1G The semiconductor device 10e shown is similar, except that in semiconductor device 10f, the bottom profile 40P is substantially flat. In some embodiments, the bottom profile 40P may be similar to... Figure 1F The semiconductor device 10d shown has a bottom profile 40P. Multiple sidewalls 12s of the mesa portion 12M are exposed to the epitaxial source / drain region 40 and contact the bottom portion 41B of the first epitaxial source / drain layer 41. The bottom portion 41B of the first epitaxial source / drain layer 41 is not merged with the channel portion 41C. Because the bottom profile 40P is flat, the bottom horizontal plane 40b is close to the height of the exposed sidewalls 12s.

[0154] Figure 1I A semiconductor device 10g is schematically shown according to an embodiment of this disclosure. The semiconductor device 10g and... Figure 1H Similar to the semiconductor device 10f shown, the difference is that in semiconductor device 10g, the top surface 41Bt of the bottom portion 41B is concave, causing the bulk epitaxial source / drain layer 43 to descend below the top surface 12f of the semiconductor substrate 12. Figure 1I As shown, the bulk epitaxial source / drain layer 43 can descend to a drop distance D below the top surface 12f of the semiconductor substrate 12. 43 In some implementations, the drop distance D 43 In the range of approximately 2nm to 15nm.

[0155] Figure 1J and Figure 1K A semiconductor device 10h according to an embodiment of this disclosure is schematically shown. The semiconductor device 10h and... Figure 1B The semiconductor device 10a shown is similar, except that in the semiconductor device 10h, the bottom portion 41B extends to the mesa portion 12M below the internal spacer 32. Figure 1K forFigure 1J A magnified view of the rectangular region 1K in the image. (See image below.) Figure 1K As shown, the first epitaxial source / drain layer 41 includes a plurality of sidewalls 12s growing from the mesa portion 12M and a bottom portion 41B grown from the top surface 36t of the buried epitaxial layer 36. The bottom portion 41B contacts the top surface 36t of the buried epitaxial layer 36 and two sidewalls 12s of the mesa portion 12M. The sidewalls 12s are curved in the xz plane extending into the mesa portion 12M. The bottom portion 41B extends a width W below the internal spacer 32. 12 In some implementations, the width W 12 Within the range of approximately 1 nm to approximately 5 nm. Therefore, the bottom portion 41B has a first width W below the top surface 12f. 41Bu A second width W is present above the top surface 12f. 41Ba Second width W 41Ba The width W of the bulk epitaxial source / drain layer 43 43 They are roughly similar. The first width W 41Bu Greater than the second width W 41Ba。 In some implementations, the first width W 41Bu Compared to the second width W 41Ba Approximately 2nm to 10nm. The bottom portion 41B of the first epitaxial source / drain layer 41 or the epitaxial source / drain region 40 has a corner formed around the lowermost internal spacer 32. In some embodiments, the angle of the corner is θ2. In some embodiments, the angle θ2 is between approximately 180° and approximately 240°. o Within the range between.

[0156] Figure 1L A semiconductor device 10h is schematically shown according to an embodiment of this disclosure. The semiconductor device 10h and... Figure 1G Similar to the semiconductor device 10e shown, the difference is that in the semiconductor device 10h, the bottom profile 40P is an angular profile, and... Figure 1E The bottom profile 40P in the illustrated semiconductor device 10c is similar. The bottom profile 40P includes side portions 40Ps and a central portion 40Pc. In some embodiments, the side portions 40Ps and the central portion 40Pc of the bottom profile 40P are substantially linear. Each side portion 40Ps may begin near the top surface 12f of the substrate and slope downwards along the sidewall 12s to the top surface 36t of the embedded epitaxial layer 36. In some embodiments, the side portions 40Ps and the central portion 40Pc form a semi-hexagon.

[0157] Figure 1M Semiconductor device 10j is schematically shown according to embodiments of this disclosure. Semiconductor device 10j is similar to... Figure 1J and Figure 1KThe semiconductor device 10h is similar to the semiconductor device 10, except that in the semiconductor device 10j, the bottom profile 40P is substantially planar, similar to Figure 1F the bottom profile 40P in the semiconductor device 10d.

[0158] Figure 1N A semiconductor device 10k is schematically shown in accordance with an embodiment of the present disclosure. The semiconductor device 10k is similar to the semiconductor device 10, except that in the semiconductor device 10k, a bottom dielectric layer 38 is formed between the epitaxial source / drain regions 40 and the buried epitaxial layer 36. The bottom dielectric layer 38 provides isolation around the epitaxial source / drain regions 40. In the semiconductor device 10, the bottom dielectric layer 38 is formed on and covers the buried epitaxial layer 36. In some embodiments, the bottom dielectric layer 38 can include a suitable dielectric material, such as a silicon nitride containing material, such as SiN, SiON, SiOCN, SiOC, SiCN, a metal oxide, such as AIO x , HfO x , or a combination thereof. In the semiconductor device 10k, the first epitaxial source / drain layer 41 does not include the bottom portion 41B because the bottom dielectric layer 38 covers the buried epitaxial layer 36 and the semiconductor substrate 12. As shown, the bulk epitaxial source / drain layer 43 is in contact with the bottom dielectric layer 38 and defines the bottom profile 40P of the epitaxial source / drain regions 40. Figure 1N

[0159] Figure 1O A semiconductor device 10m is schematically shown in accordance with an embodiment of the present disclosure. The semiconductor device 10m is similar to the semiconductor device 10k Figure 1N , except that in the semiconductor device 10m, the first epitaxial source / drain layer 41 includes a sidewall portion 41S grown from a plurality of sidewalls 12s of the mesa portion 12M. As shown, the sidewall portion 41S is in contact with the top surface 38t of the bottom dielectric layer 38 and both sidewalls 12s of the mesa portion 12M. The bottom profile 40P of the epitaxial source / drain regions 40 is defined by the bulk epitaxial source / drain layer 43 and the sidewall portion 41S of the first epitaxial source / drain layer 41. Figure 1O

[0160] Figure 1P A semiconductor device 10n is schematically shown in accordance with an embodiment of the present disclosure. The semiconductor device 10n is similar to the semiconductor device 10k Figure 1N ​​Semiconductor device 10k is similar to semiconductor device 10n, except that in semiconductor device 10k, bottom dielectric layer 38 has an opening that exposes a portion of buried epitaxial layer 36. Thus, first epitaxial source / drain layer 41 includes a bottom portion 41B that is grown from buried epitaxial layer 36. Bottom portion 41B can be disposed through a central portion of bottom dielectric layer 38. Bottom profile 40P of epitaxial source / drain region 40 is defined by bulk epitaxial source / drain layer 43 and bottom portion 41B of first epitaxial source / drain layer 41.

[0161] Figure 1Q Semiconductor device 10o is schematically shown in accordance with an embodiment of the present disclosure. Semiconductor device 10o is similar to semiconductor device 10n, except that in semiconductor device 10o, first epitaxial source / drain layer 41 includes sidewall portions 41S that are grown from multiple sidewalls 12s of mesa portion 12M. As shown, sidewall portions 41S are in contact with top surface 38t of bottom dielectric layer 38 and two sidewalls 12s of mesa portion 12M. Bottom portion 41B can be disposed through a central portion of bottom dielectric layer 38. Bottom profile 40P of epitaxial source / drain region 40 is defined by bulk epitaxial source / drain layer 43, multiple sidewall portions 41S of first epitaxial source / drain layer 41, and bottom portion 41B of first epitaxial source / drain layer 41. Figure 1O Figure 1Q Semiconductor device 10m is similar to semiconductor device 10o, except that in semiconductor device 10m, first epitaxial source / drain layer 41 includes a bottom portion 41B that is grown from buried epitaxial layer 36. As shown, bottom portion 41B is in contact with top surface 38t of bottom dielectric layer 38 and two sidewalls 12s of mesa portion 12M. Bottom portion 41B can be disposed through a central portion of bottom dielectric layer 38. Bottom profile 40P of epitaxial source / drain region 40 is defined by bulk epitaxial source / drain layer 43 and bottom portion 41B of first epitaxial source / drain layer 41.

[0162] Figure 2 is a flowchart of a method 100 of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. Figures 3A-3J Various stages of fabricating a semiconductor device 200 in accordance with an embodiment of the present disclosure are schematically shown. Semiconductor device 200 is similar to semiconductor devices 10 and 10a-10j. Alternatively, semiconductor devices 10 and 10a-10j can be fabricated using method 100.

[0163] Method 100 begins at operation 102, as shown in Figure 3A ​As shown, a plurality of semiconductor fins 220 are formed over the substrate 210. The substrate 210 is provided to form a semiconductor device 200 thereon. The substrate 210 can include a single crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 210 can include various doping configurations depending on the circuit design. For example, different doping profiles (e.g., n-well, p-well) can be formed in regions of the substrate 210 designed for different device types (e.g., n-type field effect transistor (NFET) and p-type field effect transistor (PFET)). In some embodiments, the substrate 210 can be a silicon-on-insulator (SOI) substrate including a structure for enhanced isolation (not shown).

[0164] The substrate 210 has a front surface 210f. Then, a semiconductor stack 218S is formed over the front surface 210f of the substrate 210. The stack includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate element, such as a nanosheet FET. In some embodiments, the stack includes a plurality of first semiconductor layers 214 interleaved with a plurality of second semiconductor layers 216. The first semiconductor layers 214 and the second semiconductor layers 216 have different oxidation rates and / or etch selectivities. In some embodiments, the front surface 210f of the substrate 210 can have a (100) orientation or a (110) orientation. The orientation of the front surface 210f determines the orientation of the layers in the semiconductor stack 218S and epitaxial features, such as epitaxial source / drain regions formed from semiconductor channel layers in the semiconductor stack 218S.

[0165] At a later fabrication stage, portions of the plurality of second semiconductor layers 216 form nanosheet channels in a multi-gate element. Figure 3A As shown, three first semiconductor layers 214 and three second semiconductor layers 216 are arranged in an alternating fashion as an example. Depending on the desired number of channels in the semiconductor device to be formed, more or fewer first semiconductor layers 214 and second semiconductor layers 216 can be included in the stack. In some embodiments, the number of second semiconductor layers 216 is between 1 and 10.

[0166] The first semiconductor layers 214 and the second semiconductor layers 216 can be formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the second semiconductor layers 216 comprise the same material as the substrate 210. In some embodiments, the first semiconductor layers 214 and the second semiconductor layers 216 comprise different materials than the substrate 210. In some embodiments, the first semiconductor layers 214 and the second semiconductor layers 216 are made of materials having different lattice constants. In some embodiments, the first semiconductor layers 214 comprise epitaxially grown silicon germanium (SiGe) layers and the second semiconductor layers 216 comprise epitaxially grown silicon (Si) layers. Alternatively, in some embodiments, either of the first semiconductor layers 214 and the second semiconductor layers 216 can comprise other materials, such as Ge, compound semiconductors such as SiC, GeAs, GaP, InP, InAs, and / or InSb, alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof.

[0167] The first semiconductor layers 214 in the channel regions can eventually be removed and used to define a vertical distance between adjacent channels of a subsequently formed multi-gate element. In some embodiments, the thickness of the first semiconductor layers 214 is equal to or greater than the thickness of the second semiconductor layers 216. In some embodiments, each first semiconductor layer 214 has a thickness in a range between about 3 nm and about 15 nm. In some embodiments, each second semiconductor layer 216 has a thickness in a range between about 3 nm and about 15 nm. In some embodiments, the second semiconductor layers 216 in the stack are uniform in thickness.

[0168] The semiconductor fins 220 are formed from portions of the stack and the substrate 210. The semiconductor fins 220 can be formed by patterning a hard mask (not shown) formed on the stack and one or more etching processes. Each semiconductor fin 220 has a channel portion 218 formed from the first semiconductor layers 214 and the second semiconductor layers 216 and a well portion 212 formed from the substrate 210. The semiconductor fins 220 are formed along the X-direction.

[0169] An isolation layer (not shown, but similar to the isolation layer 222) is formed in the trenches between the semiconductor fins 220. The isolation layer can be formed by a thermal oxidation process, a plasma oxidation process, a plasma nitridation process, a plasma nitride deposition process, and / or other suitable processes. Figure 1BAn isolation layer 222 is formed over the substrate 210 to cover the well portion 212 of the semiconductor fin 220. The isolation layer can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 222 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or combinations thereof. In some embodiments, the isolation layer is formed to cover the semiconductor fin 220 by a suitable deposition process (e.g., atomic layer deposition (ALD)), followed by trench etching using a suitable anisotropic etching process to expose multiple channel portions 218 of the plurality of semiconductor fins 220.

[0170] In operation 104, such as Figure 3A As shown, a sacrificial gate structure 228 and gate sidewall spacers 230 are then formed over the semiconductor fin 220. A sacrificial gate dielectric layer 224 is deposited above the exposed surface of the semiconductor device 200. The sacrificial gate dielectric layer 224 can be conformally formed over the semiconductor fin 220 and the isolation layer 222. In some embodiments, the sacrificial gate dielectric layer 224 can be deposited by CVD, sub-atmospheric CVD (SACVD), FCVD, ALD, PVD, or other suitable processes. The sacrificial gate dielectric layer 224 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material.

[0171] A sacrificial gate electrode layer 226 is deposited over a sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 may be blanket-deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer 226 is planarized. The sacrificial gate electrode layer 226 may be deposited using CVD (including LPCVD and PECVD, PVD, ALD, or other suitable processes). A patterning operation is performed over the sacrificial gate dielectric layer 224 and the sacrificial gate electrode layer 226 to form a plurality of sacrificial gate structures 228 that cover multiple portions of a semiconductor fin 220 designed as channel regions.

[0172] Next, gate sidewall spacers 230 are formed on the plurality of sidewalls of each sacrificial gate structure 228. After the sacrificial gate structure 228 is formed, the gate sidewall spacers 230 can be formed by blanket deposition of an insulating material followed by anisotropic etching to remove the insulating material from the horizontal surface. The gate sidewall spacers 230 can have a thickness in the range of about 3 nm to about 8 nm. In some embodiments, the insulating material of the gate sidewall spacers 230 is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, or combinations thereof. Figure 3A In this embodiment, the gate sidewall spacer 230 comprises two layers. In other embodiments, the gate sidewall spacer 230 may be formed of fewer or more layers of dielectric material.

[0173] In operation 106, such as Figure 3B As shown, groove etching is performed on the semiconductor fins 220 opposite to the sacrificial gate structures 228 to form source / drain grooves 234 with bottoms 234b between adjacent sacrificial gate structures 228. An etching operation is used to etch the first semiconductor layer 214 and the second semiconductor layer 216 in the semiconductor fins 220 on both sides of the sacrificial gate structures 228. In some embodiments, all layers in the stack of semiconductor fins 220, as well as a portion of the well portion 212 of the semiconductor fins 220, are etched. In some embodiments, appropriate dry etching and / or wet etching may be used to remove the first semiconductor layer 214, the second semiconductor layer 216, and the substrate 210.

[0174] In operation 108, such as Figure 3B As shown, a plurality of internal spacers 232 are formed on the exposed ends of a plurality of first semiconductor layers 214 beneath the sacrificial gate structure 228. In some embodiments, the first semiconductor layers 214 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH) solution. In some embodiments, the etching depth of the first semiconductor layers 214 is in the range of about 5 nm to about 10 nm along the X direction.

[0175] After spacer cavities are formed at opposite ends of the first semiconductor layer 214, internal spacers 232 can be formed within the spacer cavities by conformal deposition of an insulating layer. The insulating layer is then partially removed to form the internal spacers 232. The insulating layer can be formed by ALD or any other suitable method. A subsequent etching process removes most of the insulating layer except inside the cavities, forming the internal spacers 232. The internal spacers 232 comprise two or more portions, stacked alternately with the second semiconductor layer 216.

[0176] The internal spacer 232 can be formed of a single layer or multiple layers of dielectric material. In some embodiments, the internal spacer 232 may include one of silicon nitride (SiN) and silicon oxide (SiO2), SiONC, or a combination thereof. The internal spacer 232 may have a thickness in the range of about 5 nm to about 10 nm along the X direction.

[0177] In operation 110, such as Figure 3C As shown, a buried epitaxial layer 236 is formed in the lower part of the source / drain groove 234. In some embodiments, the buried epitaxial layer 236 fills the lower part of the source / drain groove 234 to a height below the front surface 210f of the substrate 210.

[0178] The material and shape of the embedded epitaxial layer 236 can be selected to achieve one or more objectives. For example, the bottom profile and crystal orientation of the subsequently formed source / drain regions can be defined. The material embedded in the epitaxial layer 236 can provide a crystal transition from the substrate 210 to the subsequently formed source / drain regions with improved adhesion. In some embodiments, the embedded epitaxial layer 236 can also be used as an alignment feature for the back-side source / drain contacts.

[0179] In some embodiments, the buried epitaxial layer 236 may be formed of a material that has etch selectivity relative to the material of the substrate 210, such as the material in the well portion 212 of the semiconductor fin 220. In some embodiments, the buried epitaxial layer 236 may also have etch selectivity relative to the insulating material in the isolation layer. In some embodiments, the buried epitaxial layer 236 is formed of a semiconductor material that has high etch selectivity relative to Si. For example, the buried epitaxial layer 236 is formed of SiGe.

[0180] The buried epitaxial layer 236 can be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. In some embodiments, the buried epitaxial layer 236 is formed of undoped SiGe. In some embodiments, the buried epitaxial layer 236 is formed of undoped SiGe with an atomic concentration of Ge in a range between about 10% and about 100%. Alternatively, the buried epitaxial layer 236 can include other materials, such as Ge, compound semiconductors such as SiC, GeAs, GaP, InP, InAs, and / or InSb, alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, the buried epitaxial layer 236 is an undoped semiconductor layer. For example, the buried epitaxial layer 236 can include Si, SiB, Si 1-x Ge x or Si 1-x Ge x B, where x is in a range between 0 and 0.5, and the B concentration is in a range between 1E19 atoms*cm -3 and 3E21 atoms*cm -3 .

[0181] As described above, the front surface 236f of the buried epitaxial layer 236 can be shaped to achieve a desired bottom profile for the source / drain regions to be formed. In some embodiments, the profile of the front surface 236f can be adjusted by adjusting the crystal growth rate along different crystallographic directions. In some embodiments, appropriate growth rates along the (100) surface and the (110) surface can be selected to achieve the desired profile. In some embodiments, two or more growth steps can be performed to achieve the desired profile.

[0182] Figure 3D and Figure 3E A method of growing the buried epitaxial layer 236 according to embodiments of the disclosure is schematically illustrated. The buried epitaxial layer 236 can be formed in two steps. First, as shown in Figure 3D , a sidewall layer 236s is conformally formed along the exposed surface of the substrate 210 in the source / drain recess 234. Next, as shown in Figure 3E , a center layer 236c is formed by a bottom-up growth process. The top surface 236t can include two sidewall portions 236ts and a central portion 236tc. In some embodiments, an angle can be formed between the sidewall portions 236ts and the central portion 236tc.

[0183] In other embodiments, the buried epitaxial layer 236 can be formed in a continuous process by adjusting the growth rate along different directions.

[0184] In operation 112, as shown in Figure 3F and Figure 3G An optional substrate pushback process is performed. In some embodiments, as shown in Figure 3F The buried epitaxial layer 236 can be formed in the z-direction or etched back to a height such that portions of the sidewall 212s of the well portion 212 (mesa portion) are exposed to the source / drain recess 234. An etching process is then performed, as shown in Figure 3G selectively etches the substrate 210 horizontally along the X-direction to form a cavity 212c underneath the front surface 210f. The sidewall 212s is pushed back to sidewall 212sp. The cavity 212c is connected with the source / drain recess 234 to provide additional volume to the source / drain region. In some embodiments, the substrate 210 can be selectively etched by using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine o-phenanthroline (EDP), or potassium hydroxide (KOH) solution. The cavity 212v is formed underneath the inner spacer 232.

[0185] The pushback operation enlarges the source / drain recess 234, thus providing increased volume for the subsequently formed source / drain region. Alternatively, the channel pushback operation can be omitted. In some embodiments, as shown in Figure 3F The etch back process of the buried epitaxial layer 236 can be performed alone without the pushback process as shown in Figure 3G

[0186] In operation 114, as shown in Figure 3H A first epitaxial source / drain layer 241 is formed in the source / drain recess 234. In some embodiments, a pre-clean process can be performed prior to epitaxial growth of the first epitaxial source / drain layer 241. The first epitaxial source / drain layer 241 is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). The first epitaxial source / drain layer 241 grows from the exposed semiconductor surfaces, i.e., the sidewall 216s of the second semiconductor layer 216 and the top surface 236t of the buried epitaxial layer 236. The first epitaxial source / drain layer 241 starts as separate portions from the exposed semiconductor surfaces. For example, the first epitaxial source / drain layer 241 includes a channel portion 241C grown from the sidewall 216s of the second semiconductor layer 216 via the source / drain recess 234, a sidewall portion 241S grown from the exposed sidewall, and a bottom portion 241B grown from the buried epitaxial layer. The channel portion 241C, the sidewall portion 241S, and the bottom portion 241B are collectively referred to as the first epitaxial source / drain layer 241.

[0187] ​The first epitaxial source / drain layer 241 is grown to a desired thickness to enable high quality crystal growth in subsequent bulk epitaxy growth. After operation 114, the channel portions 241C, the sidewall portions 241S, and the bottom portion 241B can remain separate or become merged. For example, in Figure 3H the adjacent channel portions 241C can be merged, or the lowermost channel portion 241C can be merged with the sidewall portions 241S. Alternatively, the bottom portion 241B can be merged with the sidewall portions 241S.

[0188] The first epitaxial source / drain layer 241 can include one or more layers of Si, SiP, SiC, and SiCP for NFETs, or Si, SiGe, Ge for PFETs. For PFETs, p-type dopants, such as boron (B), can also be included in the first epitaxial source / drain layer 241. For NFETs, n-type dopants, such as arsenic (As), phosphorus (P), carbon (C), or combinations thereof, can also be included in the first epitaxial source / drain layer 241.

[0189] In some embodiments, the semiconductor device 200 is a p-type device, and the first epitaxial source / drain layer 241 includes Si or SiGe with p-type dopants (e.g., B or Ga). In some embodiments, the first epitaxial source / drain layer 41 can include Si 1-x Ge x B, where x is in a range between 0 and 0.5, and the B concentration is in a range between 1E19 atoms*cm -3 and 3E21 atoms*cm -3 .

[0190] In operation 116, as shown in Figure 3I , a bulk epitaxial source / drain layer 243 is formed over the first epitaxial source / drain layer 241. The bulk epitaxial source / drain layer 243 fills the source / drain recesses 234. The first epitaxial source / drain layer 241 and the bulk epitaxial source / drain layer 243 form a plurality of epitaxial source / drain regions 240. Although Figure 3I only one layer in some embodiments, the bulk epitaxial source / drain layer 243 can include two or more layers.

[0191] The bulk epitaxial source / drain layer 243 is epitaxially grown from the first epitaxial source / drain layer 241. The bulk epitaxial source / drain layer 243 has a higher dopant concentration than the first epitaxial source / drain layer 241. In some embodiments, the composition of the bulk epitaxial source / drain layer 243 is also different from that of the first epitaxial source / drain layer 241. The bulk epitaxial source / drain layer 243 and the first epitaxial source / drain layer 241 have different crystal structures. For NFETs, the bulk epitaxial source / drain layer 243 may include one or more layers of Si, SiP, SiC, and SiCP, or for PFETs, it may include Si, SiGe, and Ge. For PFETs, a p-type dopant, such as boron (B), is also included in the bulk epitaxial source / drain layer 243. For NFETs, n-type dopants, such as arsenic (As), phosphorus (P), carbon (C), or combinations thereof, are included in the bulk epitaxial source / drain layer 243.

[0192] In some embodiments, the semiconductor device 200 is a p-type device, and the bulk epitaxial source / drain layer 243 comprises Si or SiGe with a p-type dopant (e.g., B or Ga). In some embodiments, the bulk epitaxial source / drain layer 43 may be Si. 1-x Ge x B, where x is in the range of 0.3 and 0.8 and the concentration of B is 1E20 atoms*cm. -3 and 5E21 atoms *cm -3 Within the range between.

[0193] In operation 118, such as Figure 3J As shown, a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are formed above the exposed surface. CESL 242 is formed on the epitaxial source / drain region 240 and the gate sidewall spacer 230. In some embodiments, CESL 242 has a thickness ranging from about 1 nm to about 15 nm. CESL 242 may comprise Si3N4, SiON, SiCN, or any other suitable material and may be formed by CVD, PVD, or ALD.

[0194] An interlayer dielectric (ILD) layer 244 is formed over a contact etch stop layer (CESL) 242. The material of the ILD layer 244 includes compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the ILD layer 244. After the formation of the ILD layer 244, a planarization operation, such as CMP, is performed to expose the sacrificial gate electrode layer 226 for subsequent removal of the sacrificial gate structure 228. The ILD layer 244 protects the epitaxial source / drain regions 240 during the removal of the sacrificial gate structure 228.

[0195] In operation 120, such as Figure 3J As shown, multiple alternative gate structures 250 are formed to replace the sacrificial gate structure 228. First, the sacrificial gate structure 228 is removed. Specifically, the sacrificial gate electrode layer 226 and the sacrificial gate dielectric layer 224 are removed sequentially to expose the channel portion 218. A first semiconductor layer 214 and a second semiconductor layer 216 are exposed. The first semiconductor layer 214 is then selectively removed using an etchant that has a higher etching rate on the first semiconductor layer 214 than on the second semiconductor layer 216. After removing the first semiconductor layer 214, the second semiconductor layer 216 is exposed, thereby forming a semiconductor channel region comprising multiple second semiconductor layers 216 connected to multiple epitaxial source / drain regions 240.

[0196] An alternative gate structure 250 is then formed around the channel region. A gate dielectric layer 246 is formed on each of the second semiconductor layers 216, and a gate electrode layer 248 is formed on the gate dielectric layer 246. The gate dielectric layer 246 and the gate electrode layer 248 may be referred to as the alternative gate structure 250.

[0197] The gate dielectric layer 246 can be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process, such as ALD, is used to form the gate dielectric layer 246 to ensure that a gate dielectric layer 246 with a uniform thickness is formed around each second semiconductor layer 216. In some embodiments, the thickness of the gate dielectric layer 246 is in the range of about 1 nm to about 6 nm.

[0198] The gate dielectric layer 246 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO. 2、 HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an interface layer (not shown) is formed between the second semiconductor channel layer 16 and the gate dielectric layer 246. In some embodiments, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 246 and the gate electrode layer 248.

[0199] A gate electrode layer 248 is formed on the gate dielectric layer 246 surrounding each second semiconductor layer 216 (i.e., each channel) and the gate dielectric layer 246. The gate electrode layer 248 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 248 may be formed by CVD, ALD, electroplating, or other suitable methods.

[0200] In operation 122, such as Figure 3J As shown, multiple source / drain contacts 252 can be formed. After forming the gate electrode layer 248, a planarization process, such as CMP, is performed to remove excess deposits of the gate electrode material and expose the top surface of the ILD layer 244. In some embodiments, the source / drain contacts 252 are formed in the ILD layer 244. Before forming the source / drain contacts 252, contact vias 254 are formed in the ILD layer 244, CESL 242, and a portion of the epitaxial source / drain region 240.

[0201] After the source / drain contacts 252 are formed, a front-side interconnect structure (not shown) is formed using a middle-end line process. The front-side interconnect structure includes multiple dielectric layers with multiple metal lines and vias formed therein. The metal lines and vias in the front-side interconnect structure can be formed from copper or a copper alloy using one or more damascene processes. The front-side interconnect structure may include multiple sets of interlayer dielectric (ILD) layers and intermetallic dielectric (IMD) layers.

[0202] Figure 4 This is a flowchart of a method 300 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Figures 5A-5C Various stages of manufacturing a semiconductor device 400 according to an embodiment of this disclosure are schematically shown. The semiconductor device 400 is similar to semiconductor devices 10k to 10o. The semiconductor device can be manufactured using method 300.

[0203] Method 300 is similar to method 100, except that method 300 includes operation 311 after operations 102, 104, 106, 108, and 110. After operation 110, semiconductor device 400 may be similar to semiconductor device 200 shown in Figure 3C.

[0204] In operation 311, such as Figures 5A-5BAs shown, a bottom dielectric layer 238 is formed above the buried epitaxial layer 236. The bottom dielectric layer 238 is formed on the front surface 236f of the buried epitaxial layer 236. The bottom dielectric layer 238 may also cover the exposed surface of the isolation layer. The bottom dielectric layer 238 may include one or more layers of dielectric material. The bottom dielectric layer 238 can provide electrical isolation between the well portion 212 of the substrate 210 and the source / drain regions during operation.

[0205] The bottom dielectric layer 238 can be formed via a directional deposition process, exhibiting selective growth from bottom to top towards the sidewalls. For example, the bottom dielectric layer 238 can be formed via a directional PECVD process. In some embodiments, such as Figure 5A As shown, the bottom dielectric layer 238 can be formed by depositing a conformal dielectric layer on the exposed surface, and then, as... Figure 5B As shown, the conformal dielectric layer is selectively removed from the vertical and outer surfaces, leaving a portion at the bottom of the source / drain recess 234. In some embodiments, the bottom dielectric layer 238 can be formed of any suitable dielectric material, such as silicon nitride-containing materials, such as SiN, SiON, SiOCN, SiOC, SiCN, or metal oxides, such as AlO. x HfO x , or combinations thereof.

[0206] In some embodiments, the bottom dielectric layer 238 covers the front surface 236f of the buried epitaxial layer 236. The vertical position of the bottom dielectric layer 238 depends on the shape and position of the buried epitaxial layer 236. The bottom dielectric layer 238 may have a thickness above the buried epitaxial layer 236. In some embodiments, the thickness is in the range of about 0 nm to about 30 nm.

[0207] In some implementations, such as Figure 5B As shown, an opening 239 is formed through the bottom dielectric layer 238 to expose a portion of the buried epitaxial layer 236. Depending on the device design, the opening 239 may be omitted. The opening 239 is formed so that a portion of the buried epitaxial layer 236 can be used as a seed layer during source / drain region epitaxial growth.

[0208] In some embodiments, the opening 239 can be formed by patterning using photolithography and etching through the pattern using a suitable etching process. In other embodiments, the opening 239 can be formed by directional etching.

[0209] After operation 311, operations 112, 114, 116, 118, 120, and 122 can be executed, producing results such as... Figure 5C The semiconductor device 400 shown includes a bottom dielectric layer 238 formed between a buried epitaxial layer 236 and an epitaxial source / drain region 240.

[0210] Figure 6 is a flowchart of a method of manufacturing a semiconductor device according to embodiments of the present disclosure. Figures 7A-7D Various stages of manufacturing a semiconductor device 600 according to embodiments of the present disclosure are schematically illustrated. The semiconductor device 600 is similar to the semiconductor devices 10 and 10a-10o. Alternatively, the semiconductor devices 10 and 10a-10o can be manufactured using the method 500.

[0211] The method 500 is similar to the methods 100 and 300, except that the method includes an operation 502 in which a fin structure 620 including a plurality of second semiconductor layers 216 and a plurality of sacrificial layers 614 is formed, as shown in Figure 7A The sacrificial layers 614 can be dielectric layers that can be selectively removed from the second semiconductor layers 216. The stack 618 includes the plurality of second semiconductor layers 216 and the plurality of sacrificial layers 614 arranged alternately.

[0212] The use of the plurality of sacrificial layers 614 in the fin structure 620 allows the method 500 to omit forming a plurality of internal spacers during formation of the source / drain regions. As shown in Figure 7B and Figure 7C As shown in Figure 7B a semiconductor device 600 after the operation 110 in the method 500 is schematically illustrated, Figure 7C a semiconductor device 600 after the operation 116 in the method 500 is schematically illustrated. Figure 7D a semiconductor device 600 after the operation 122 in the method 500 is schematically illustrated.

[0213] The various embodiments or examples described herein provide a number of advantages over the prior art. The semiconductor devices according to the present disclosure reduce the channel resistance (R ch ) ， improve the channel mobility, and minimize the source / drain contact resistance loading.

[0214] It should be appreciated that not all advantages are necessarily met in this document, that all embodiments or examples need not have a particular advantage, and that different embodiments or examples can provide different advantages.

[0215] Some implementations of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductor channel disposed over a top surface of a semiconductor substrate; a epitaxial source / drain region connected to the semiconductor channel, wherein the epitaxial source / drain region includes a sidewall connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate; and a buried epitaxial layer disposed below the epitaxial source / drain region, wherein a top surface of the buried epitaxial layer conforms to the bottom surface of the source / drain region, and the top surface of the buried epitaxial layer is disposed below the top surface of the semiconductor substrate.

[0216] In some implementations, the semiconductor channel includes two or more semiconductor channel layers stacked over the top surface of the semiconductor substrate.

[0217] In some implementations, the bottom surface of the epitaxial source / drain region extends below the top surface of the semiconductor substrate in a range of 5 nm to 20 nm.

[0218] In some implementations, the bottom surface includes a first sidewall portion, a second sidewall portion, and a central portion. The central portion is connected to the first sidewall portion and the second sidewall portion, wherein the first sidewall portion and the second sidewall portion are inclined downward.

[0219] In some implementations, the first sidewall portion, the second sidewall portion, and the central portion are a plurality of linear portions.

[0220] In some implementations, the first sidewall portion, the second sidewall portion, and the central portion are a plurality of rounded portions.

[0221] In some implementations, the first sidewall portion and the central portion form an angle in a range between 120° and 180°.

[0222] In some implementations, the epitaxial source / drain region is in contact with a sidewall of the semiconductor substrate disposed between the top surface of the semiconductor substrate and the bottom surface of the epitaxial source / drain region.

[0223] In some implementations, the semiconductor device further includes a bottom dielectric layer disposed between the epitaxial source / drain region and the buried epitaxial layer.

[0224] In some implementations, the bottom dielectric layer includes an opening, and the epitaxial source / drain region extends below the bottom dielectric layer through the opening to contact the buried epitaxial layer.

[0225] In some implementations, the epitaxial source / drain region has a first width above the top surface of the semiconductor substrate and a second width below the top surface of the semiconductor substrate, and the second width is greater than the first width.

[0226] Some implementations of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductor substrate; two or more semiconductor channel layers vertically stacked above a top surface of the semiconductor substrate; two or more internal spacers disposed in an alternating stack with the two or more semiconductor channel layers; and an epitaxial source / drain region including a first epitaxial source / drain layer grown from the two or more semiconductor channel layers, and a bulk epitaxial source / drain layer grown from the first epitaxial source / drain layer, wherein a bottom surface of the bulk epitaxial source / drain layer extends below the top surface of the semiconductor substrate.

[0227] Some implementations of the present disclosure provide a semiconductor device including a semiconductor substrate, two or more semiconductor channel layers, two or more internal spacers, an epitaxial source / drain region, and a buried epitaxial layer. The two or more semiconductor channel layers are vertically stacked above a top surface of the semiconductor substrate. The two or more internal spacers are disposed in an alternating stack with the two or more semiconductor channel layers. The epitaxial source / drain region has a bottom surface that extends below the top surface of the semiconductor substrate. The buried epitaxial layer is disposed below the bottom surface of the epitaxial source / drain region, a top surface of the buried epitaxial layer being disposed below the top surface of the semiconductor substrate.

[0228] In some implementations, the semiconductor device further includes the buried epitaxial layer disposed below the bottom surface of the epitaxial source / drain region, wherein the first epitaxial source / drain layer includes two or more channel portions grown from the two or more semiconductor channel layers and a bottom portion grown from the buried epitaxial layer.

[0229] In some implementations, the semiconductor device further includes a bottom dielectric layer disposed between the buried epitaxial layer and the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the buried epitaxial layer.

[0230] In some implementations, the epitaxial source / drain region is in contact with sidewalls of the semiconductor substrate disposed between the top surface of the semiconductor substrate and the bottom surface of the epitaxial source / drain region.

[0231] Some implementations provide a method of forming a semiconductor device. The method includes forming a semiconductor fin on a top surface of a semiconductor substrate, wherein the semiconductor fin includes a plurality of first semiconductor layers and a plurality of second semiconductor layers arranged in an alternating pattern; forming a recess through the semiconductor fin and into the semiconductor substrate; forming a buried epitaxial layer in the recess, wherein a top surface of the buried epitaxial layer is below a top surface of the semiconductor substrate; and growing an epitaxial source / drain region above the buried epitaxial layer, wherein a bottom surface of the epitaxial source / drain region is below the top surface of the semiconductor substrate.

[0232] In some embodiments, forming the buried epitaxial layer includes growing a conformal layer in the recess, and growing an up-from-under layer over the conformal layer.

[0233] In some embodiments, the method further includes selectively etching back the plurality of sidewalls of the semiconductor substrate between the top surface of the semiconductor substrate and the top surface of the buried epitaxial layer.

[0234] In some embodiments, the method further includes, prior to selectively etching back the semiconductor substrate, recess etching the buried epitaxial layer to expose the sidewalls of the semiconductor substrate between the top surface of the semiconductor substrate and the buried epitaxial layer.

[0235] In some embodiments, the method further includes forming a bottom dielectric layer over the buried epitaxial layer, wherein a top surface of the bottom dielectric layer is disposed below the top surface of the semiconductor substrate.

[0236] Some embodiments of the present disclosure provide a semiconductor device including a semiconductor substrate, a semiconductor channel, a buried epitaxial layer, and an epitaxial source / drain region. The semiconductor channel is disposed over a top surface of the semiconductor substrate. The buried epitaxial layer is disposed in the semiconductor substrate, wherein a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate. The epitaxial source / drain region is over the buried epitaxial layer, wherein a bottom surface of the epitaxial source / drain region is below the top surface of the semiconductor substrate, the epitaxial source / drain region has a first width above the top surface of the semiconductor substrate and a second width below the top surface of the semiconductor substrate, the second width is greater than the first width.

[0237] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a semiconductor channel disposed over a top surface of a semiconductor substrate; a epitaxial source / drain region connected to the semiconductor channel, wherein the epitaxial source / drain region includes a sidewall connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate; and a buried epitaxial layer disposed below the epitaxial source / drain region, wherein a top surface of the buried epitaxial layer conforms to the bottom surface of the epitaxial source / drain region, the top surface of the buried epitaxial layer disposed below the top surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein wherein the semiconductor channel includes two or more semiconductor channel layers stacked over the top surface of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein wherein the bottom surface of the epitaxial source / drain region extends below the top surface of the semiconductor substrate in a range of 5 nm to 20 nm.

4. The semiconductor device according to claim 3, wherein wherein the bottom surface includes: a first sidewall portion; a second sidewall portion; and a central portion connected to the first sidewall portion and the second sidewall portion, wherein the first sidewall portion and the second sidewall portion are sloped downward.

5. The semiconductor device according to any one of Claims 2 to 4, wherein wherein the epitaxial source / drain region is in contact with a sidewall of the semiconductor substrate disposed between the top surface of the semiconductor substrate and the bottom surface of the epitaxial source / drain region.

6. The semiconductor device according to any one of Claims 2 to 4, wherein further comprising a bottom dielectric layer disposed between the epitaxial source / drain region and the buried epitaxial layer.

7. A semiconductor device, characterized by comprising: Comprising: a semiconductor substrate; two or more semiconductor channel layers vertically stacked over a top surface of the semiconductor substrate; two or more internal spacers alternately stacked with the two or more semiconductor channel layers; an epitaxial source / drain region having a bottom surface extending below the top surface of the semiconductor substrate; and a buried epitaxial layer disposed below the bottom surface of the epitaxial source / drain region, wherein a top surface of the buried epitaxial layer is disposed below the top surface of the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein wherein the epitaxial source / drain region is in contact with a sidewall of the semiconductor substrate disposed between the top surface of the semiconductor substrate and the bottom surface of the epitaxial source / drain region.

9. The semiconductor device according to claim 7 or claim 8, wherein further comprising a bottom dielectric layer disposed between the buried epitaxial layer and the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the buried epitaxial layer.

10. A semiconductor device, characterized by comprising: Comprising: a semiconductor channel disposed over a top surface of a semiconductor substrate; a buried epitaxial layer disposed in the semiconductor substrate, wherein a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate; and an epitaxial source / drain region over the buried epitaxial layer, wherein a bottom surface of the epitaxial source / drain region is below the top surface of the semiconductor substrate, the epitaxial source / drain region having a first width above the top surface of the semiconductor substrate and a second width below the top surface of the semiconductor substrate, the second width being greater than the first width.

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