Light-emitting semiconductor structure

Abstract

The utility model provides a light-emitting semiconductor structure. The light-emitting semiconductor structure comprises a substrate, an anode electrode, an epitaxial structure, a gate electrode and a cathode electrode, the anode electrode is arranged on the lower surface of the substrate, the epitaxial structure is arranged on the upper surface of the substrate and comprises a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer and a light emitting layer, the first P-type semiconductor layer is arranged on the upper surface of the substrate, the first N-type semiconductor layer is arranged on the first P-type semiconductor layer, and the second N-type semiconductor layer is arranged on the second N-type semiconductor layer. The second P-type semiconductor layer is arranged on the first N-type semiconductor layer, the second N-type semiconductor layer is arranged on the second P-type semiconductor layer, and the light-emitting layer is arranged between the second P-type semiconductor layer and the second N-type semiconductor layer.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of semiconductor technology, especially relates to a light emitting semiconductor structure. BACKGROUND

[0002] The light emitting component of a general LED printer head (LPH) is implemented using a epitaxial structure, and the epitaxial structure for implementing the light emitting component includes a light emitting thyristor with a PNPN structure, i.e., the light emitting thyristor has, from bottom to top, a P-type semiconductor, an N-type semiconductor, a P-type semiconductor, and an N-type semiconductor.

[0003] However, the light emitting efficiency of the epitaxial structure of the light emitting thyristor still has a lot of room for improvement, and when manufacturing the epitaxial structure of the light emitting thyristor, the surface and the edge sidewall of the epitaxial component are often damaged or affected during the etching process, thereby affecting the driving characteristics, IV curve, and impedance characteristics of the epitaxial component. In addition, because the edge of the semiconductor has many defects, the electrons and holes injected into the epitaxial component are often affected by the edge defect traps of the semiconductor, so that the edge of the light emitting thyristor cannot effectively emit light, thereby affecting the overall light emitting efficiency of the component. SUMMARY

[0004] In some embodiments, a light emitting semiconductor structure includes a substrate, an anode electrode, an epitaxial structure, a gate electrode, and a cathode electrode; the anode electrode is disposed on the lower surface of the substrate, and the epitaxial structure is disposed on the upper surface of the substrate; the epitaxial structure includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer, and a light emitting layer; the first P-type semiconductor layer is disposed on the upper surface of the substrate, the first N-type semiconductor layer is disposed on the first P-type semiconductor layer, the second P-type semiconductor layer is disposed on the first N-type semiconductor layer, the second N-type semiconductor layer is disposed on the second P-type semiconductor layer, and the light emitting layer is disposed between the second P-type semiconductor layer and the second N-type semiconductor layer; the gate electrode is disposed on the upper surface of the second P-type semiconductor layer, and the cathode electrode is disposed on the upper surface of the second N-type semiconductor layer.

[0005] In some embodiments, the light emitting layer is a multiple quantum well layer, and the multiple quantum well layer includes a plurality of energy well layers and a plurality of energy barrier layers stacked.

[0006] In some embodiments, the light emitting layer is an intrinsic semiconductor layer.

[0007] In some embodiments, the number of the plurality of energy well layers and the plurality of energy barrier layers is 5 to 30, the material of the plurality of energy well layers is gallium arsenide (GaAs), and the material of the plurality of energy barrier layers is aluminum gallium arsenide (AlGaAs) or indium gallium phosphide (InGaP).

[0008] In some embodiments, the light emitting semiconductor structure further comprises a current flow restriction layer disposed between the light emitting layer and the second P-type semiconductor layer or between the light emitting layer and the second N-type semiconductor layer, the current flow restriction layer comprising a peripheral insulating region and a central conductive region.

[0009] In some embodiments, the peripheral insulating region is disposed directly below the cathode electrode

[0010] In some embodiments, the material of the current flow restriction layer is aluminum arsenide (AlAs), and the peripheral insulating region is formed by oxidation of aluminum (Al) in the current flow restriction layer.

[0011] In some embodiments, the first P-type semiconductor layer comprises a first buffer layer, a second buffer layer, and an anode layer, the first buffer layer is disposed on the upper surface of the substrate, the second buffer layer is disposed on the first buffer layer, and the anode layer is disposed on the second buffer layer.

[0012] In some embodiments, the second N-type semiconductor layer comprises a barrier layer, a cathode layer, and a capping layer, the barrier layer is disposed on the upper surface of the light emitting layer, the cathode layer is disposed on the barrier layer, and the capping layer is disposed on the cathode layer.

[0013] In some embodiments, a method of manufacturing a light emitting semiconductor structure includes forming a cathode electrode on an upper surface of a semiconductor base structure, the semiconductor base structure including a substrate, a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer, a light emitting layer, a current flow direction restriction layer, and a high-doped P-type semiconductor layer, the first P-type semiconductor layer disposed on an upper surface of the substrate, the first N-type semiconductor layer disposed on the first P-type semiconductor layer, the second P-type semiconductor layer disposed on the first N-type semiconductor layer, the second N-type semiconductor layer disposed on the second P-type semiconductor layer, the light emitting layer disposed between the second P-type semiconductor layer and the second N-type semiconductor layer, the current flow direction restriction layer disposed between the light emitting layer and the second P-type semiconductor layer, and the high-doped P-type semiconductor layer disposed between the light emitting layer and the current flow direction restriction layer; forming a protection layer on the cathode electrode and exposed surfaces of the semiconductor base structure; performing a first dry etching step to form a first trench on one side of a predetermined light emitting portion of the semiconductor base structure and a second trench on another side of the predetermined light emitting portion, the first trench and the second trench extending from the protection layer to the second P-type semiconductor layer without penetrating the second P-type semiconductor layer; oxidizing side surfaces of the current flow direction restriction layer through the first trench and the second trench; performing a second dry etching step to form a third trench on one side of a predetermined switching portion of the semiconductor base structure and a fourth trench on another side of the predetermined switching portion, and to extend the second trench through the second P-type semiconductor layer and the first N-type semiconductor layer to the first P-type semiconductor layer without penetrating the first P-type semiconductor layer, the third trench formed between the first trench and the predetermined switching portion, the third trench and the fourth trench extending from the protection layer to the second P-type semiconductor layer without penetrating the second P-type semiconductor layer; forming a plurality of gate electrodes on bottom surfaces of the third trench and the fourth trench; performing a third dry etching step to form a fifth trench between two adjacent gate electrodes of the fourth trench, and to extend the second trench through the first P-type semiconductor layer to the substrate without penetrating the substrate, the fifth trench extending from the bottom surface of the fourth trench to the first P-type semiconductor layer without penetrating the first P-type semiconductor layer; after the third dry etching step, integrally forming a passivation layer on exposed surfaces of the semiconductor base structure, the cathode electrode, and the plurality of gate electrodes; after integrally forming the passivation layer on the exposed surfaces of the semiconductor base structure, the cathode electrode, and the plurality of gate electrodes, performing a fourth dry etching step to form a cathode opening above the cathode electrode and a gate opening above the gate electrode; and forming a wiring layer on the passivation layer, the wiring layer electrically connected to the cathode electrode through the cathode opening and to the gate electrode through the gate opening.

[0014] The foregoing disclosure and description of the applications are illustrative and explanatory thereof and various changes in the details of the apparatus constructed and operative methods can be made by those skilled in the art without departing from the spirit of the application. Attached Figure Description

[0015] Figure 1 This is a cross-sectional schematic diagram of one embodiment of the light-emitting semiconductor structure of this utility model.

[0016] Figure 2 This is a cross-sectional schematic diagram of one embodiment of the light-emitting layer of this utility model.

[0017] Figure 3 This is a line graph comparing the luminescence intensity of the light-emitting semiconductor structure of this invention with that of existing semiconductor structures.

[0018] Figure 4A This is a cross-sectional schematic diagram of another embodiment of the light-emitting semiconductor structure of this utility model.

[0019] Figure 4B This is a cross-sectional schematic diagram of another embodiment of the light-emitting semiconductor structure of this utility model.

[0020] Figure 5A This is a cross-sectional schematic diagram of another embodiment of the light-emitting semiconductor structure of this utility model.

[0021] Figure 5B This is a cross-sectional schematic diagram of another embodiment of the light-emitting semiconductor structure of this utility model.

[0022] Figure 6 This is a top view of one embodiment of the light-emitting semiconductor array chip unit of this utility model.

[0023] Figure 7 for Figure 6 A cross-sectional view of the light-emitting semiconductor array chip cell along section line 7.

[0024] Figures 8A to 8I This is a schematic diagram illustrating the steps of one embodiment of the manufacturing method of the light-emitting semiconductor structure of this utility model.

[0025] Figure 9 This is a flowchart illustrating one embodiment of the manufacturing method of the light-emitting semiconductor structure of this utility model.

[0026] Explanation of reference numerals in the attached figures:

[0027] 1: Light-emitting semiconductor structure;

[0028] 10:Substrate;

[0029] 11: Anode electrode;

[0030] 12: First P-type semiconductor layer;

[0031] 13: First N-type semiconductor layer;

[0032] 14: second P-type semiconductor layer;

[0033] 15: light emitting layer;

[0034] 16: second N-type semiconductor layer;

[0035] 17: gate electrode;

[0036] 18: cathode electrode;

[0037] 120: first buffer layer;

[0038] 121: second buffer layer;

[0039] 122: anode layer;

[0040] 160: barrier layer;

[0041] 161: cathode layer;

[0042] 162: cover layer;

[0043] 20: epitaxial structure;

[0044] 151: energy well layer;

[0045] 152: energy barrier layer;

[0046] 19: current flow restriction layer;

[0047] 190: peripheral insulating region;

[0048] 191: central conductive region;

[0049] 21: highly doped P-type semiconductor layer;

[0050] 3: light emitting semiconductor array chip unit;

[0051] 30: transmission section;

[0052] 31: parity switch section;

[0053] 32: light emitting section;

[0054] 7: section line;

[0055] 180-181: cathode electrode;

[0056] 1800-1801: side surface of cathode electrode;

[0057] 1900-1901: side surface of peripheral insulating region;

[0058] L: length of central conductive region;

[0059] 22: semiconductor base layer structure;

[0060] 70: Protective layer;

[0061] 101-105: Grooves;

[0062] 40: Pre-set light-emitting part;

[0063] 41: Pre-ordered switch section;

[0064] 172: Gate opening;

[0065] 182: Cathode opening;

[0066] 71: Passivation layer;

[0067] 72: Line layer;

[0068] S01~S10: Steps. Detailed Implementation

[0069] Figure 1 This is a schematic cross-sectional view of one embodiment of the light-emitting semiconductor structure 1. Please refer to... Figure 1 The light-emitting semiconductor structure 1 includes a substrate 10, an anode electrode 11, an epitaxial structure 20, a gate electrode 17, and a cathode electrode 18. The anode electrode 11 is disposed on the lower surface of the substrate 10, and the epitaxial structure 20 is disposed on the upper surface of the substrate 10. The epitaxial structure 20 includes a first P-type semiconductor layer 12, a first N-type semiconductor layer 13, a second P-type semiconductor layer 14, a second N-type semiconductor layer 16, and a light-emitting layer 15. The first P-type semiconductor layer 12 is disposed on the upper surface of the substrate 10, the first N-type semiconductor layer 13 is disposed on the first P-type semiconductor layer 12, the second P-type semiconductor layer 14 is disposed on the first N-type semiconductor layer 13, the second N-type semiconductor layer 16 is disposed on the second P-type semiconductor layer 14, the light-emitting layer 15 is disposed between the second P-type semiconductor layer 14 and the second N-type semiconductor layer 16, the gate electrode 17 is disposed on the upper surface of the second P-type semiconductor layer 14, and the cathode electrode 18 is disposed on the upper surface of the second N-type semiconductor layer 16.

[0070] Figure 2 This is a schematic cross-sectional view of one embodiment of the light-emitting layer 15. Please refer to [link / reference]. Figure 1 and Figure 2 The luminescent layer 15 comprises a plurality of stacked energy sink layers 151 and a plurality of energy barrier layers 152. Figure 2 In some embodiments, the light-emitting layer 15 includes five energy trap layers 151 and five energy barrier layers 152, but the number of multiple energy trap layers 151 and multiple energy barrier layers 152 is not limited thereto. In some embodiments, the number of multiple energy trap layers 151 and multiple energy barrier layers 152 is five to 30.

[0071] In some embodiments, the material of the well layer 151 can be, but is not limited to, gallium arsenide (GaAs), and the material of the barrier layer 152 can be, but is not limited to, aluminum gallium arsenide (AlGaAs) or indium gallium phosphide (InGaP).

[0072] In some embodiments, the light emitting layer 15 is an intrinsic semiconductor layer, i.e., the light emitting layer 15 is a pure crystal semiconductor that is non-doped and has a complete lattice, and the light emitting layer 15 has equal and balanced concentrations of free electrons (negatively charged carriers) and holes (positively charged carriers) that participate in conduction. In other words, in some embodiments, the epitaxial structure 20 is a PNPIN structure rather than a PNPN structure.

[0073] In some embodiments, the material of the substrate 10 can be, but is not limited to, GaAs, the material of the anode electrode 11 can be, but is not limited to, chromium (Cr) or Au, the material of the gate electrode 17 can be, but is not limited to, Au or gold-zinc alloy (AuZn), and the material of the cathode electrode 18 can be, but is not limited to, Au, germanium (Ge), or nickel (Ni).

[0074] In some embodiments, the first P-type semiconductor layer 12 includes a first buffer layer 120, a second buffer layer 121, and an anode layer 122. The first buffer layer 120 is disposed on the upper surface of the substrate 10, the second buffer layer 121 is disposed on the first buffer layer 120, and the anode layer 122 is disposed on the second buffer layer 121. In some embodiments, the material of the first buffer layer 120 can be, but is not limited to, GaAs, and the materials of the second buffer layer 121 and the anode layer 122 can be, but are not limited to, AlGaAs.

[0075] In some embodiments, the second N-type semiconductor layer 16 includes a barrier layer 160, a cathode layer 161, and a cover layer 162. The barrier layer 160 is disposed on the upper surface of the light emitting layer 15, the cathode layer 161 is disposed on the barrier layer 160, and the cover layer 162 is disposed on the cathode layer 161. In some embodiments, the material of the cover layer 162 can be, but is not limited to, GaAs, and the materials of the barrier layer 160 and the cathode layer 161 can be, but are not limited to, AlGaAs.

[0076] In some embodiments, the thickness of the substrate 10 can be, but is not limited to, 300 micrometers (pm), the thickness of the first buffer layer 120 can be, but is not limited to, 100 nanometers (nm), the thickness of the second buffer layer 121 can be, but is not limited to, 250 nm, the thickness of the anode layer 122 can be, but is not limited to, 400 nm, the thickness of the first N-type semiconductor layer 13 can be, but is not limited to, 320 nm, the thickness of the second P-type semiconductor layer 14 can be, but is not limited to, 680 nm, the thickness of the barrier layer 160 can be, but is not limited to, 15 nm, the thickness of the cathode layer 161 can be, but is not limited to, 560 nm, and the thickness of the cover layer 162 can be, but is not limited to, 25 nm.

[0077] In some embodiments, the wavelength of the light emitted by the epitaxial structure 20 is between 760 nm and 820 nm.

[0078] Table 1 below shows the material, composition, carrier type, and dopant of each layer in one embodiment of the light emitting semiconductor structure, but the present application is not limited thereto.

[0079] Table 1

[0080]

[0081] Table 2 below shows the main peak wavelength value, thickness range, and carrier concentration range of each layer in one embodiment of the light emitting semiconductor structure 1, but the present application is not limited thereto.

[0082] Table 2

[0083]

[0084]

[0085] Figure 3 A comparison graph of the light emitting intensity of the light emitting semiconductor structure 1 and the prior art semiconductor structure. Referring to the figure, structure 2 is a prior art semiconductor structure of a light emitting thyristor using a conventional PNPN structure, and structure 1 is the light emitting semiconductor structure 1 of the epitaxial structure 20 of the present application using a PNPIN structure; the light emitting intensity of structure 1 is about 4 times that of structure 2. Figure 3 It can be seen that the light emitting semiconductor structure 1 has about 4 times the light emitting intensity of the prior art semiconductor structure. In Figure 3 In the embodiment, the number of the plurality of energy well layers 151 and the plurality of energy barrier layers 152 of the light emitting semiconductor structure 1 is 5.

[0086] Figure 4A A cross-sectional view of another embodiment of the light emitting semiconductor structure 1 is shown. Referring to the figure, Figure 4AIn some embodiments, the light emitting semiconductor structure 1 further comprises a current flow restriction layer 19 disposed between the light emitting layer 15 and the second P-type semiconductor layer 14, the current flow restriction layer 19 comprises a peripheral insulating region 190 and a central conductive region 191. Figure 4B A cross-sectional schematic view of yet another embodiment of the light emitting semiconductor structure 1. Please refer to FIG. 1C. Figure 4B In some embodiments, the current flow restriction layer 19 is disposed between the light emitting layer 15 and the second N-type semiconductor layer 16.

[0087] In some embodiments, the peripheral insulating region 190 is formed by selectively oxidizing a specific element in the material of the current flow restriction layer 19 from at least one side surface of the current flow restriction layer 19. In some embodiments, the material of the current flow restriction layer 19 can be, but is not limited to, aluminum arsenide (AlAs), and the peripheral insulating region 190 is formed by oxidizing aluminum (Al) in the current flow restriction layer 19, but the present application is not limited thereto.

[0088] Since the edge of the semiconductor has many defects, by disposing the peripheral insulating region 190, the defects of the edge of the current flow restriction layer 19 can be eliminated, and thus the current flowing through the current flow restriction layer 19 is not affected by the defects of the edge of the current flow restriction layer 19, but is concentrated to the central conductive region 191, so that the light emitting efficiency of the light emitting semiconductor structure 1 is greatly improved.

[0089] Figure 5A A cross-sectional schematic view of still another embodiment of the light emitting semiconductor structure 1. Please refer to FIG. 1D. Figure 5A In some embodiments, the light emitting semiconductor structure 1 further comprises a highly doped P-type semiconductor layer 21 disposed between the light emitting layer 15 and the current flow restriction layer 19. In some embodiments, the material of the highly doped P-type semiconductor layer 21 is the same as that of the second P-type semiconductor layer 14, and the doping concentration of the highly doped P-type semiconductor layer 21 can be, but is not limited to, 10 times the doping concentration of the second P-type semiconductor layer 14; for example, if the doping concentration of the second P-type semiconductor layer 14 is 10 17 (cm -3 ), the doping concentration of the highly doped P-type semiconductor layer 21 at this time is 10 18 (cm -3 ). Figure 5B A cross-sectional schematic view of still another embodiment of the light emitting semiconductor structure 1. Please refer to FIG. 1E. Figure 5B In some embodiments, the current flow restriction layer 19 is disposed between the light emitting layer 15 and the second N-type semiconductor layer 16.

[0090] Traditionally, the driving components of the light emitting thyristor are usually disposed in the middle or lower half of the structure. For example, if the structure of the light emitting thyristor is PNPN structure, the driving components are usually disposed in the first P-type semiconductor layer, the first N-type semiconductor layer and the second P-type semiconductor layer from bottom to top. However, during the manufacturing process, the layers where the driving components of the light emitting thyristor are disposed are often etched during the etching process, which affects the driving characteristics, driving voltage, IV curve and impedance characteristics of the light emitting thyristor, thereby increasing the time required for the light emitting thyristor to switch on and off at a frequency.

[0091] In the light emitting semiconductor structure 1, since the light emitting layer 15 and the current flow restriction layer 19 are disposed above the second P-type semiconductor layer 14 where the gate electrode 17 is disposed, only the second P-type semiconductor layer 14 needs to be etched during the manufacturing process. In other words, the first P-type semiconductor layer 12 and the first N-type semiconductor layer 13 will not be etched and will not be affected by the subsequent edge oxidation insulation process. Therefore, the preparation time for the on and off frequency of the light emitting thyristor driving part PNP transistor composed of the first P-type semiconductor layer and the first N-type semiconductor layer above the wafer substrate and the second P-type semiconductor layer will remain relatively stable and will not be affected by the etching and edge oxidation processes.

[0092] Figure 6 A top view of one embodiment of the light emitting semiconductor array chip unit 3. Please refer to Figure 6 , the light emitting semiconductor array chip unit 3 includes a transmission part 30, an odd-even switching part 31 and a light emitting part 32, the light emitting semiconductor array chip includes a plurality of light emitting semiconductor array chip units 3, and the structure of the light emitting semiconductor array chip is the light emitting semiconductor structure 1. The present application does not limit the number of light emitting semiconductor array chip units 3 included in the light emitting semiconductor array chip.

[0093] Figure 7 A cross-sectional view of the light emitting semiconductor array chip unit 3 of Figure 6 along the cross-sectional line 7. Please refer to Figure 7 In some embodiments, the cathode electrode 18 of the light emitting part 32 is a ring-shaped cathode electrode. Therefore, in Figure 7In the cross-sectional view, the cathode electrode 18 of the light emitting portion 32 has two parts (hereinafter referred to as cathode electrode 180 and cathode electrode 181 for convenience of explanation). At this time, the light emitting region of the light emitting portion 32 is the middle region surrounded by the ring-shaped cathode electrode 18. In some embodiments, the peripheral insulating region 190 of the light emitting portion 32 is disposed directly below the cathode electrode 180 and the cathode electrode 181. In some embodiments, the side surface 1900 of the peripheral insulating region 190 disposed directly below the cathode electrode 180, which is close to the center of the epitaxial structure 20, is aligned with the side surface 1800 of the cathode electrode 180, which is close to the center of the epitaxial structure 20, and the side surface 1901 of the peripheral insulating region 190 disposed directly below the cathode electrode 181, which is close to the center of the epitaxial structure 20, is aligned with the side surface 1801 of the cathode electrode 181, which is close to the center of the epitaxial structure 20. At this time, the length L of the central conductive region 191 of the light emitting portion 32 is the distance between the side surface 1800 of the cathode electrode 180, which is close to the center of the epitaxial structure 20, and the side surface 1801 of the cathode electrode 181, which is close to the center of the epitaxial structure 20.

[0094] Figures 8A to 8I A flowchart of one embodiment of a method for manufacturing a light emitting semiconductor structure 1. Please refer to Figure 9 A flowchart of one embodiment of a method for manufacturing a light emitting semiconductor structure 1. Please refer to Figures 8A to 8I and Figure 9 First, the cathode electrode 18 is formed on the upper surface of the semiconductor base structure 22 (step S01), which includes the substrate 10, the first P-type semiconductor layer 12, the first N-type semiconductor layer 13, the second P-type semiconductor layer 14, the second N-type semiconductor layer 16, the light emitting layer 15, the current flow restriction layer 19, and the high-doped P-type semiconductor layer 21. The first P-type semiconductor layer 12 is disposed on the upper surface of the substrate 10, the first N-type semiconductor layer 13 is disposed on the first P-type semiconductor layer 12, the second P-type semiconductor layer 14 is disposed on the first N-type semiconductor layer 13, the second N-type semiconductor layer 16 is disposed on the second P-type semiconductor layer 14, the light emitting layer 15 is disposed between the second P-type semiconductor layer 14 and the second N-type semiconductor layer 16, the current flow restriction layer 19 is disposed between the light emitting layer 15 and the second P-type semiconductor layer 14, and the high-doped P-type semiconductor layer 21 is disposed between the light emitting layer 15 and the current flow restriction layer 19 (as shown in Figure 8A

[0095] Next, the protective layer 70 is formed on the cathode electrode 18 and the exposed surface of the semiconductor base structure 22 (step S02) (as shown in Figure 8B ​(As shown). Then, a first dry etching step is performed to form a first trench 101 on one side of the predetermined light-emitting portion 40 of the semiconductor substrate structure 22 and to form a second trench 102 on the other side of the predetermined light-emitting portion 40 (step S03). The first trench 101 and the second trench 102 extend from the protective layer 70 to the second P-type semiconductor layer 14 but do not penetrate the second P-type semiconductor layer 14 (as shown). Figure 8C (As shown). Then, through the first trench 101 and the second trench 102, the side surface of the current flow confinement layer 19 is oxidized (step S04) (as shown). Figure 8D (As shown).

[0096] Next, a second dry etching step is performed to form a third trench 103 on one side of the predetermined switching portion 41 of the semiconductor substrate structure 22 and a fourth trench 104 on the other side of the predetermined switching portion 41, and to make the second trench 102 penetrate the second P-type semiconductor layer 14 and the first N-type semiconductor layer 13 and extend to the first P-type semiconductor layer 12 without penetrating the first P-type semiconductor layer 12 (step S05). The third trench 103 is formed between the first trench 101 and the predetermined switching portion 41, and the third trench 103 and the fourth trench 104 extend from the protective layer 70 to the second P-type semiconductor layer 14 without penetrating the second P-type semiconductor layer 14 (e.g., Figure 8E (As shown). Then, a plurality of gate electrodes 17 are formed on the bottom surfaces of the third trench 103 and the fourth trench 104 (step S06) (as shown). Figure 8F (As shown).

[0097] Next, a third dry etching step is performed to form a fifth trench 105 between adjacent gate electrodes 17 of the fourth trench 104, and to extend the second trench 102 through the first P-type semiconductor layer 12 to the substrate 10 without penetrating the substrate 10 (step S07). The fifth trench 105 extends from the bottom surface of the fourth trench 104 to the first P-type semiconductor layer 12 without penetrating the first P-type semiconductor layer 12 (e.g., ...). Figure 8G (As shown). Then, after the third dry etching step, a passivation layer 71 is integrally formed on the exposed surfaces of the semiconductor substrate structure 22, the cathode electrode 18, and the gate electrode 17 (step S08). Then, after depositing the passivation layer 71 on the exposed surfaces of the semiconductor substrate structure 22, the cathode electrode 18, and the gate electrode 17, a fourth dry etching step is performed to form a cathode opening 182 above the cathode electrode 18 and a gate opening 172 above the gate electrode 17 (step S09). Figure 8H (As shown). Finally, a circuit layer 72 is formed on the passivation layer 71 (step S10). The circuit layer 72 is electrically connected to the cathode electrode 18 through the cathode opening 182 and electrically connected to the gate electrode 17 through the gate opening 172 (as shown). Figure 8I (As shown).

[0098] In some embodiments, the method of forming the cathode electrode 18 on the upper surface of the semiconductor base structure 22 (step S01) can be, but is not limited to, plating the metal of the cathode electrode 18 on the upper surface of the semiconductor base structure 22 using an electron gun. In some embodiments, the method of forming the protective layer 70 on the exposed surfaces of the cathode electrode 18 and the semiconductor base structure 22 (step S02) can be, but is not limited to, depositing the protective layer 70 on the exposed surfaces of the cathode electrode 18 and the semiconductor base structure 22 using chemical vapor deposition (CVD). In some embodiments, the material of the protective layer 70 can be, but is not limited to, silicon nitride (SiN). In some embodiments, the thickness of the protective layer 70 can be, but is not limited to, 500 angstroms (A). In some embodiments, the operating temperature when forming the protective layer 70 on the exposed surfaces of the cathode electrode 18 and the semiconductor base structure 22 using CVD can be, but is not limited to, 320°C.

[0099] In some embodiments, the depth of the first trench 101 and the second trench 102 after step S03 can be, but is not limited to, 1000 A. In other words, the depth of the first trench 101 and the second trench 102 after step S03 in the semiconductor base structure 22 can be, but is not limited to, 1000 A. (i.e. the depth of the first trench 101 and the second trench 102 after step S03 minus the thickness of the protective layer 70 ).

[0100] In some embodiments, the depth of the third trench 103 and the fourth trench 104 can be, but is not limited to, 1000 A. In other words, the depth of the third trench 103 and the fourth trench 104 in the semiconductor base structure 22 can be, but is not limited to, 1000 A. (i.e. the depth of the third trench 103 and the fourth trench 104 minus the thickness of the protective layer 70 ). In some embodiments, the depth of the second trench 102 after step S05 can be, but is not limited to, 12000 A. In other words, the depth of the second trench 102 after the second dry etching step can be, but is not limited to, 12000 A. (i.e. the depth of the second trench 102 after step S03 plus the depth of the extension of the second trench 102 12000 A ). In some embodiments, the depth of the extension of the second trench 102 after step S05 is but the present application is not limited thereto.

[0101] In some embodiments, the method of forming the plurality of gate electrodes 17 on the bottom surfaces of the third and fourth trenches 103, 104 (step S06) can be, but is not limited to, using thermal evaporation deposition to plate the metal of the gate electrodes 17 on the bottom surfaces of the third and fourth trenches 103, 104.

[0102] In some embodiments, the depth of the fifth trench 105 can be, but is not limited to, 0.5-2.0 μm. or In some embodiments, after the third dry etching step, the method of integrally forming the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17 (step S08) can be, but is not limited to, using CVD to integrally form the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17. In some embodiments, the material of the passivation layer 71 can be, but is not limited to, SiN. In some embodiments, the thickness of the passivation layer 71 can be, but is not limited to, 0.1-0.5 μm. In some embodiments, the operating temperature when using CVD to integrally form the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17 can be, but is not limited to, 320 °C. In some embodiments, the method of forming the wiring layer 72 on the passivation layer 71 can be, but is not limited to, using electroplating to plate the wiring layer 72 on the passivation layer 71. In some embodiments, the material of the wiring layer 72 can be, but is not limited to, gold (Au).

[0103] In summary, in some embodiments, by the provision of the light emitting layer 15, the light emitting semiconductor structure 1 with the PNPIN structure has about 4 times the light emitting intensity of the prior art semiconductor structure. And by the provision of the peripheral insulation region 190 and the provision of the light emitting layer 15 and the current flow restriction layer 19 in the light emitting semiconductor structure 1 above the second P-type semiconductor layer 14 where the gate electrode 17 is located, the light emitting efficiency of the light emitting semiconductor structure 1 is further improved.

[0104] Although the technical contents of the present application have been disclosed above with reference to the preferred embodiments, the present application is not intended to be limited thereto, and any modifications and refinements made by those skilled in the art without departing from the spirit of the present application shall be encompassed within the scope of the present application, and the scope of protection of the present application shall be defined by the patentable scope.

Claims

1. A light emitting semiconductor structure, characterized by A substrate; an anode electrode disposed on a lower surface of the substrate; a epitaxial structure disposed on an upper surface of the substrate, comprising: a first P-type semiconductor layer disposed on the upper surface of the substrate; a first N-type semiconductor layer disposed on the first P-type semiconductor layer; a second P-type semiconductor layer disposed on the first N-type semiconductor layer; a second N-type semiconductor layer disposed on the second P-type semiconductor layer; and a light emitting layer disposed between the second P-type semiconductor layer and the second N-type semiconductor layer; a gate electrode disposed on an upper surface of the second P-type semiconductor layer; and a cathode electrode disposed on an upper surface of the second N-type semiconductor layer. The light emitting layer is a multiple quantum well layer, which comprises a plurality of well layers and a plurality of barrier layers stacked in groups. The light emitting layer is an intrinsic semiconductor layer. The number of the plurality of well layers and the plurality of barrier layers is 5 to 30, the material of the plurality of well layers is gallium arsenide, and the material of the plurality of barrier layers is aluminum gallium arsenide or indium gallium phosphide.

2. The light emitting semiconductor structure of claim 1, wherein, A current flow restriction layer is further disposed between the light emitting layer and the second P-type semiconductor layer or between the light emitting layer and the second N-type semiconductor layer, which comprises a peripheral insulating region and a central conductive region.

3. The light emitting semiconductor structure of claim 2, wherein, The peripheral insulating region is disposed directly below the cathode electrode.

4. The light emitting semiconductor structure of claim 3, wherein, The material of the current flow restriction layer is aluminum arsenide, and the peripheral insulating region is formed by aluminum oxidation in the current flow restriction layer.

5. The light emitting semiconductor structure of claim 4, wherein, The first P-type semiconductor layer comprises a first buffer layer, a second buffer layer, and an anode layer, the first buffer layer is disposed on the upper surface of the substrate, the second buffer layer is disposed on the first buffer layer, and the anode layer is disposed on the second buffer layer.

6. The light emitting semiconductor structure of claim 5, wherein, The second N-type semiconductor layer comprises a barrier layer, a cathode layer, and a cover layer, the barrier layer is disposed on the upper surface of the light emitting layer, the cathode layer is disposed on the barrier layer, and the cover layer is disposed on the cathode layer.

7. The light emitting semiconductor structure of claim 6, wherein the first and second semiconductor layers are formed of a material selected from the group consisting of gallium nitride, aluminum nitride, indium nitride, and alloys thereof. ​ 8. The light emitting semiconductor structure of claim 7, wherein the first and second semiconductor layers are formed of a material selected from the group consisting of gallium nitride, aluminum nitride, indium nitride, and alloys thereof. ​ 9. The light emitting semiconductor structure of claim 8, wherein, ​

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