Display device and display panel

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a through hole, a through hole packaging area surrounding the through hole and a display area surrounding the through hole packaging area. The display panel comprises a substrate, a display layer, a thin film packaging layer and a touch function layer which are sequentially arranged in a stacked mode. The display panel is provided with at least one light blocking structure surrounding the through hole in the through hole packaging area; the light blocking structure comprises a bottom metal structure located in the display layer and a top metal structure located in the touch function layer, and the bottom metal structure and the top metal structure are arranged in an overlapped mode. The display panel can reduce crosstalk interference of the display area to the through holes.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device and a display panel. Background Technology

[0002] A punch-hole display involves creating a hole in the display area of ​​the screen and placing a camera or other light-sensing element behind it, which can effectively increase the screen-to-body ratio of the display device. However, pixel emission may cause optical crosstalk to the hole, adversely affecting the performance of the light-sensing element and reducing the user experience.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display device and display panel that reduces crosstalk interference from the display area to the through hole.

[0005] According to one aspect of this disclosure, a display panel is provided, including a through-hole, a through-hole encapsulation region surrounding the through-hole, and a display region surrounding the through-hole encapsulation region; the display panel includes a substrate, a display layer, a thin film encapsulation layer, and a touch function layer sequentially stacked;

[0006] The display panel has at least one light-blocking structure surrounding the through-hole in the through-hole encapsulation area; the light-blocking structure includes a bottom metal structure in the display layer and a top metal structure in the touch function layer, and the bottom metal structure and the top metal structure are overlapped.

[0007] According to one embodiment of the present disclosure, the display layer includes at least one gate metal layer, at least one source / drain metal layer, and a pixel electrode layer sequentially stacked on one side of the substrate; the touch function layer includes a first touch metal layer and a second touch metal layer sequentially stacked on one side of the display layer.

[0008] The light-blocking structure includes at least one auxiliary trace;

[0009] The bottom metal structure of the auxiliary wiring includes at least two of the gate metal sub-wirings located in the gate metal layer, the source / drain metal sub-wirings located in the source / drain metal layer, and the electrode metal sub-wirings located in the pixel electrode layer.

[0010] The top metal structure of the auxiliary trace includes at least one of a first touch metal sub-trace located in the first touch metal layer and a second touch metal sub-trace located in the second touch metal layer.

[0011] According to an embodiment of the present disclosure, the display layer comprises a plurality of source-drain metal layers arranged in sequence; the auxiliary trace has a corresponding source-drain metal sub-trace in any one of the source-drain metal layers, and adjacent two source-drain metal sub-traces are at least partially connected to each other; the electrode metal sub-trace is at least partially connected to the surface of the source-drain metal sub-trace farthest from the substrate.

[0012] The display layer further comprises a pixel definition layer or a support column layer on the side of the pixel electrode layer away from the substrate, and the pixel definition layer or the support column layer is provided with a first insulating structure corresponding to the auxiliary trace, the first insulating structure covering each source-drain metal sub-trace and electrode metal sub-trace of the corresponding auxiliary trace.

[0013] According to an embodiment of the present disclosure, the display layer comprises a plurality of wiring unit layers arranged in sequence, and each wiring unit layer comprises a source-drain metal layer and a planarization layer on the side of the source-drain metal layer away from the substrate.

[0014] The display panel has at least one auxiliary trace group, and any one of the auxiliary trace groups comprises a plurality of auxiliary traces adjacent and surrounding the through hole in sequence.

[0015] In the same auxiliary trace group, any one of the auxiliary traces has a corresponding source-drain metal sub-trace in any one of the source-drain metal layers, and there is a gap between adjacent two source-drain metal sub-traces arranged in the same source-drain metal layer.

[0016] Any one of the planarization layers has a second insulating structure corresponding to the auxiliary trace group, and the second insulating structure covers the gap between each source-drain metal sub-trace and each source-drain metal sub-trace in the same wiring unit layer.

[0017] According to an embodiment of the present disclosure, in the same auxiliary trace group, the electrode metal sub-trace of any one of the auxiliary traces does not overlap with the electrode metal sub-trace of the remaining auxiliary traces; or, in the same auxiliary trace group, the electrode metal sub-trace of each of the auxiliary traces is connected to each other to form a whole.

[0018] According to an embodiment of the present disclosure, the display panel has at least one auxiliary trace group, and any one of the auxiliary trace groups comprises a plurality of auxiliary traces adjacent and surrounding the through hole in sequence.

[0019] In the same auxiliary trace group, the top metal structure of any one of the auxiliary traces is not connected to the top metal structure of the remaining auxiliary traces; or, in the same auxiliary trace group, the top metal structure of each of the auxiliary traces is connected to each other to form a whole.

[0020] According to an embodiment of the present disclosure, the display panel has a winding area in the through-hole packaging area; the auxiliary trace includes an inner auxiliary trace between the winding area and the through-hole, and / or an outer auxiliary trace between the winding area and the display area.

[0021] According to an embodiment of the present disclosure, the display layer includes at least one gate metal layer, at least one source-drain metal layer and a pixel electrode layer which are sequentially stacked on one side of a substrate; the touch function layer includes a first touch metal layer and a second touch metal layer which are sequentially stacked on one side of the display layer.

[0022] The light-blocking structure includes at least one packaging dam;

[0023] The bottom metal structure of the packaging dam includes at least two of a gate metal sub-block wall in the gate metal layer, a source-drain metal sub-block wall in the source-drain metal layer and an electrode metal sub-block wall in the pixel electrode layer.

[0024] The top metal structure of the packaging dam includes at least one of a first touch metal sub-block wall in the first touch metal layer and a second touch metal sub-block wall in the second touch metal layer.

[0025] According to an embodiment of the present disclosure, the display layer includes a plurality of source-drain metal layers which are sequentially stacked, the bottom metal structure of the packaging dam has a corresponding source-drain metal sub-block wall in any one of the source-drain metal layers, and adjacent two source-drain metal sub-block walls are at least partially connected to each other.

[0026] According to an embodiment of the present disclosure, the bottom metal structure of the packaging dam further includes an electrode metal sub-block wall which is at least partially connected to a surface of the source-drain metal sub-block wall farthest from the substrate.

[0027] According to an embodiment of the present disclosure, the display layer further includes a pixel definition layer or a support column layer on a side of the pixel electrode layer farthest from the substrate, the pixel definition layer or the support column layer is provided with a fourth insulating structure corresponding to the packaging dam one by one, and the fourth insulating structure covers the bottom metal structure of the corresponding packaging dam.

[0028] According to an embodiment of the present disclosure, the display panel has a transition area surrounding the through-hole in the through-hole packaging area; in the transition area close to the edge of the display area, the step difference between the surface of the thin film packaging layer farthest from the substrate and the substrate is a first step difference; in the transition area close to the edge of the through-hole, the step difference between the surface of the thin film packaging layer farthest from the substrate and the substrate is a second step difference; the first step difference is greater than the second step difference.

[0029] The metal layer of the touch function layer covers the transition area.

[0030] According to an embodiment of the present disclosure, the display panel further comprises a color filter layer on the side of the touch function layer away from the substrate;

[0031] The black matrix layer covers at least part of the through-hole packaging area.

[0032] According to another aspect of the present disclosure, a display device is provided, comprising the above display panel.

[0033] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor based on these drawings.

[0035] Figure 1 For an embodiment of the present disclosure, a schematic diagram of the planar structure of the display panel.

[0036] Figure 2 For an embodiment of the present disclosure, a schematic diagram of the partial cross-sectional structure of the display panel.

[0037] Figure 3 For an embodiment of the present disclosure, a schematic diagram of the planar structure of the display panel.

[0038] Figure 4 For an embodiment of the present disclosure, a schematic diagram of the planar structure of the display panel in the through-hole packaging area.

[0039] Figure 5 For an embodiment of the present disclosure, a schematic diagram of the cross-sectional structure of the display panel in the through-hole packaging area.

[0040] Figure 6 For an embodiment of the display device, a schematic diagram of the possible light path of the stray light.

[0041] Figure 7 For an embodiment of the present disclosure, a schematic diagram of the structure of the display panel in the through-hole packaging area.

[0042] Figure 8 For the first example of the present disclosure, a schematic diagram of the cross-sectional structure of the display panel in the through-hole packaging area.

[0043] Figure 9 For a second example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0044] Figure 10 For a third example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0045] Figure 11 For a fourth example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0046] Figure 12 For a fifth example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0047] Figure 13 For a sixth example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0048] Figure 14 For a seventh example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0049] Figure 15 For an eighth example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0050] Figure 16 For a ninth example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area.

[0051] Figure 17 For a tenth example of the present disclosure, a cross-sectional structure schematic diagram of a display panel in a through-hole packaging area. DETAILED DESCRIPTION

[0052] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any number of ways, and example implementations can be implemented using digital electronic circuitry, analog electronic circuitry, or digital circuitry in combination with analog circuitry, as desired. It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of elements are often exaggerated relative to each other. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.

[0053] Although relative terms are used in this description, such as "upper," "lower," to describe one component's relationship to another component of the icon, these terms are used only for convenience, e.g., based on the example orientation depicted in the figures. It is to be understood that if the icon's device were turned over, so that what is described as "upper" would become "lower," then the described components would be reversed. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0054] The terms "one," "a," "an," "the," and "at least one" are used to mean that "one or more" of the enumerated elements / constituents / etc. is present with the understanding that the terms "one," "a," "an," "the," and "at least one" are used in this description to mean "one or more" unless otherwise indicated. The term "or" is used in this description to mean "and / or" unless otherwise indicated. The term "including" is used in this description to mean "including, but not limited to." The term "based on" is used in this description to mean "based at least in part on."

[0055] In the embodiments of the present disclosure, the material of the metal layer can be selected from a metal element, or an alloy formed by multiple metal elements, or a metal oxide capable of conducting electricity (e.g., conductorized ITO, IGZO, etc.). The metal layer can include one film layer, or a stack of multiple sub-metal layers.

[0056] In the present disclosure, when it is described that structure A and structure B are arranged to overlap, it means that structure A and structure B are respectively in different film layers, but the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate at least partially overlap.

[0057] In the present disclosure, when it is described that structure C covers structure D, it means that structure C is located on the side of structure D away from the substrate, and the orthographic projection of structure D on the substrate is located within the orthographic projection of structure C on the substrate.

[0058] In the present disclosure, when it is described that the inside, the outside, etc. directions, the radial direction from the through hole to the display area is taken as the outward direction, and the radial direction from the display area to the through hole is taken as the inward direction. Accordingly, when it is described that the inside of a structure E / region F, it means that the structure E / region F is close to the through hole; when it is described that one side of a structure E / region F, it means that the structure E / region F is close to the display area.

[0059] In the present disclosure, structure layer X is located on the side of structure layer Y away from the substrate, which can be understood as that structure layer X is formed on the side of structure layer Y away from the substrate. When structure layer Y is a patterned structure, part of structure layer X can also be located at the same physical height as structure layer Y or below the physical height of structure layer Y, wherein the substrate is the height reference.

[0060] The present disclosure provides a display panel and a display device using the same. Figure 1 For an embodiment of the present disclosure, a schematic diagram of a planar structure of a display panel PNL (without through holes) is shown. Referring to Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located at least one side of the display area AA. In the display area AA, the display panel PNL is provided with display units DU arranged in an array, the display units DU including sub-pixels PX and pixel driving circuits PDC for driving the sub-pixels PX. The display panel PNL is not provided with display units DU in the peripheral area BB, or the display units DU provided are not used for displaying a picture. Figure 1 In an example, the display panel PNL is provided with a plurality of scan lines GL extending along a row direction DH in the display area AA, each scan line GL being provided one-to-one with each display unit row. The pixel driving circuit PDC of each display unit DU in the display unit row is electrically connected with the corresponding scan line GL. The display panel PNL is further provided with a plurality of data lines DL extending along a column direction DV in the display area AA, each data line DL being provided one-to-one with each display unit column. The pixel driving circuit PDC of each display unit DU in the display unit column is electrically connected with the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit DU is connected with one scan line GL and one data line DL. When a scan signal is loaded on the scan line GL, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PX according to the written driving voltage. It can be understood that in other embodiments of the present disclosure, the arrangement of the display units DU and the connection mode of the data lines DL, scan lines GL and the like can also be different from the example. Figure 1

[0061] Figure 2 For an embodiment of the present disclosure, a schematic diagram of a partial cross-section of a display panel PNL is shown. In Figure 2 In an example, the display panel PNL can include a substrate SBT, a display layer DPL, a thin film encapsulation layer TFE and a touch function layer TSL arranged in sequence. The display layer DPL is provided with sub-pixels PX and pixel driving circuits PDC for driving the sub-pixels PX, the thin film encapsulation layer TFE is used for encapsulating and protecting the sub-pixels PX, and the touch function layer TSL is used for realizing a touch function.

[0062] In an example, referring to Figure 2 ​The display layer DPL can include a driving layer DRL and a pixel layer PXL which are sequentially stacked on one side of the substrate SBT; the pixel layer PXL is provided with a sub-pixel PX, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixel PX. Each sub-pixel PX can emit light under the driving of the pixel driving circuit PDC to display a picture.

[0063] Optionally, the substrate SBT can be a substrate of inorganic material, a substrate of organic material, or a composite substrate formed by stacking a substrate of inorganic material and a substrate of organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can be polyimide.

[0064] Optionally, in the driving layer DRL, any one pixel driving circuit PDC can include a transistor (for example, a thin film transistor) and a storage capacitor. Further, the transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0065] It can be understood that in each transistor in the pixel driving circuit, the types of any two transistors can be the same or different. For example, in some embodiments, in one pixel driving circuit, part of the transistors can be N-type transistors and part of the transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit, the material of the active layer of part of the transistors can be low-temperature polysilicon semiconductor material, and the material of the active layer of part of the transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, part of the thin film transistors are low-temperature polysilicon transistors, and part of the thin film transistors are metal oxide transistors.

[0066] Optionally, the driving layer DRL can include a semiconductor layer SCL, a gate insulating layer GI, a gate metal layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc. which are stacked between the substrate base plate SBT and the pixel layer PXL. Each thin film transistor and storage capacitor can be formed by the semiconductor layer SCL, the gate insulating layer GI, the gate metal layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, etc. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form part of the wiring or conductive structure by being made conductive if necessary. The gate layer can be used to form one or more of the gate layer wiring such as the scan wiring, the reset control wiring, the light-emitting control wiring, etc., and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor. The source-drain metal layer can be used to form the source-drain metal layer wiring such as the data wiring, the driving power voltage wiring, etc., and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, for example, it can also include a light shielding layer between the semiconductor layer SCL and the substrate base plate SBT, etc. Any one of the above-mentioned semiconductor layer SCL, gate metal layer GT, source-drain metal layer SD, etc. can also be multi-layered as needed, for example, the driving layer DRL can include two different semiconductor layers SCL, or two or three source-drain metal layers SD, or two or three gate metal layers GT; accordingly, the insulating film layer in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) can be adaptively increased or decreased, or a new insulating film layer can be added as needed. Optionally, the driving layer DRL can also include a passivation layer, which can be arranged on the surface of the source-drain metal layer SD away from the substrate base plate SBT, so as to protect the source-drain metal layer SD.

[0067] In an embodiment of the present disclosure, the film layers between the substrate base plate SBT and the first source-drain metal layer SD1 can be collectively referred to as a transistor layer TFTL, which has the semiconductor layer SCL, the gate insulating layer GI and the gate metal layer GT required for forming the thin film transistor. For example, in the example of Figure 4 , the transistor layer TFTL includes the inorganic buffer layer BUF, the polycrystalline silicon semiconductor layer PSCL, the first gate insulating layer GI1, the first gate metal layer GT1, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, the second gate metal layer GT2 and the interlayer dielectric layer ILD which are sequentially stacked on the side of the substrate base plate SBT. In the example of Figure 4In the example of FIG. 1, the driving layer DRL includes two semiconductor layers SCL (a polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL), three gate insulating layers GI (a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), two gate metal layers GT (a first gate metal layer GT1 and a second gate metal layer GT2), two source-drain metal layers SD (a first source-drain metal layer SD1 and a second source-drain metal layer SD2), and two planarization layers PLN (a first planarization layer PLN1 and a second planarization layer PLN2). Among them, the polysilicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate metal layer GT1 can form a low-temperature polysilicon thin-film transistor, and the first gate metal layer GT1, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the second gate metal layer GT2 can form a metal oxide thin-film transistor. In this way, the display panel PNL is a display panel using the LTPO technology.

[0068] In an embodiment of the present disclosure, the structure between the transistor layer TFTL and the pixel layer PXL can be referred to as a wiring layer MRL, one of the important functions of the wiring layer MRL is to realize electrical connection between different devices, such as thin-film transistors, storage capacitors, and sub-pixels PX. Optionally, the wiring layer MRL can include one or more wiring unit layers MF, each wiring unit layer MF can include a source-drain metal layer SD and a planarization layer PLN located on the side of the source-drain metal layer SD away from the substrate SBT. It can be understood that in some examples, the wiring unit layer MF can also include a passivation layer, which can be disposed between the source-drain metal layer SD and the planarization layer PLN to protect the source-drain metal layer SD.

[0069] For example, in the example of FIG. 1, the driving layer DRL includes two semiconductor layers SCL (a polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL), three gate insulating layers GI (a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), two gate metal layers GT (a first gate metal layer GT1 and a second gate metal layer GT2), two source-drain metal layers SD (a first source-drain metal layer SD1 and a second source-drain metal layer SD2), and two planarization layers PLN (a first planarization layer PLN1 and a second planarization layer PLN2). Among them, the polysilicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate metal layer GT1 can form a low-temperature polysilicon thin-film transistor, and the first gate metal layer GT1, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the second gate metal layer GT2 can form a metal oxide thin-film transistor. In this way, the display panel PNL is a display panel using the LTPO technology. Figure 4In the example of FIG. 1, the wiring layer MRL includes a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, and a second planarization layer PLN2, which are sequentially stacked on the side of the transistor layer TFTL away from the substrate SBT. In this way, the wiring layer MRL includes two wiring unit layers MF, i.e., a first wiring unit layer MF1 (including the first source-drain metal layer SD1 and the first planarization layer PLN1) and a second wiring unit layer MF2 (including the second source-drain metal layer SD2 and the second planarization layer PLN2). When the display panel PNL needs more layers of source-drain metal layers SD, the number of wiring unit layers MF can be increased adaptively (i.e., the source-drain metal layers SD and the planarization layers PLN are increased synchronously). For example, when the display panel PNL is provided with three layers of source-drain metal layers SD, the wiring layer MRL includes a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer, and a third planarization layer, which are sequentially stacked. The third source-drain metal layer and the third planarization layer serve as a third wiring unit layer.

[0070] In an embodiment of the present disclosure, referring to FIG. 1, Figure 2 The sub-pixel PX in the pixel layer PXL is a thin-film light-emitting element, which can include two electrodes and a light-emitting functional unit interposed between the two electrodes. Figure 2 In the example of FIG. 1, the pixel layer PXL can include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML, which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings arranged one-to-one with the plurality of pixel electrodes, and any one pixel opening exposes at least a partial region of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edges of the pixel electrode and exposes at least a partial internal region of the pixel electrode, so that the pixel definition layer PXL can effectively define the actual effective region of the pixel electrode (the region directly connected to the light-emitting functional layer EFL), and further define the light-emitting region and the light-emitting area of the sub-pixel PX. The light-emitting functional layer EFL covers at least the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting functional layer EFL in the display area. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The part of the light-emitting functional layer EFL between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrode, the common electrode layer COML, and the light-emitting functional unit form the sub-pixel PX. One of the pixel electrode and the common electrode layer COML serves as an anode of the sub-pixel PX, and the other serves as a cathode of the sub-pixel PX.

[0071] In one embodiment of this disclosure, the display panel further includes a support pillar layer located on the side of the pixel definition layer (PDL) away from the substrate. Figure 2 (Not shown in the image), this support pillar layer is used to form multiple support pillars to support a precision metal mask during the vapor deposition process. In one example, the support pillar layer and the pixel definition layer (PDL) can be made of the same material and fabricated in the same process; for example, a grayscale masking process can be used on the same organic material layer to simultaneously form the pixel definition layer and the support pillar layer. In another example, after forming the pixel definition layer, a new organic material layer can be coated and patterned to form the individual support pillars of the support pillar layer.

[0072] In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer COML serves as the cathode of the sub-pixel PX.

[0073] exist Figure 2 In the example, the sub-pixel PX is an organic light-emitting diode (OLED). It is understood that in other embodiments of this disclosure, the sub-pixel may also be other types of light-emitting elements, such as current-driven light-emitting elements such as QLED, PLED, Micro LED, Mini LED, etc.

[0074] Figure 2 The illustrated display panel PNL uses LTPO technology to drive an OLED as a sub-pixel PX in its display layer DPL. It is understood that the display panel PNL of this disclosure is not limited to this; other driving technologies may be used in the driving layer DRL, and other light-emitting elements may be used in the pixel layer PXL.

[0075] exist Figure 2 In the example, the thin-film encapsulation layer TFE can be disposed on the surface of the pixel layer PXL away from the substrate SBT, and it can include alternately stacked inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the thin-film encapsulation layer TFE can also adopt other structures, such as multiple stacked inorganic encapsulation layers.

[0076] exist Figure 2In the example, the touch functionality layer TSL can be positioned on the side of the thin-film encapsulation layer TFE away from the pixel layer PXL, so that the display panel PNL has touch functionality. Figure 2 In the example, the touch functional layer TSL includes a first touch metal layer TMA, a touch insulating layer TLD, and a second touch metal layer TMB, which are sequentially stacked on the surface of the thin-film encapsulation layer TFE. It is understood that in other examples, the touch functional layer TSL may also include an insulating layer or an organic layer covering the second touch metal layer TMB.

[0077] exist Figure 2 In the example, the touch functionality layer (TSL) comprises two metal layers. It will be understood that in other embodiments of this disclosure, the touch functionality layer (TSL) may also comprise more metal layers or employ fewer metal layers.

[0078] In one embodiment of this disclosure, see Figure 2 The display panel PNL may also include a color filter layer CFL located on the side of the touch function layer TSL away from the substrate SBT. This color filter layer CFL has color filter units CFU corresponding to sub-pixels PX. For example, a red color filter unit is disposed above a red sub-pixel, a green color filter unit is disposed above a green sub-pixel, and a blue color filter unit is disposed above a blue sub-pixel. This improves the purity of the emitted color of the display panel PNL, thereby increasing its color gamut, and also reduces interference from ambient light on normal display. See one example. Figure 2 The color filter layer CFL also has a black matrix layer BM, which can be located between sub-pixels PX to reduce light crosstalk and further reduce reflection of ambient light.

[0079] In one embodiment of this disclosure, see Figure 2 The display panel PNL may also include a protective layer OC, which may be disposed on the surface of the display panel PNL away from the substrate SBT to protect the display panel PNL. Figure 2 In the example, the protective layer OC is disposed on the surface of the color filter layer CFL away from the substrate SBT.

[0080] Figure 3 This is a schematic diagram of the planar structure of a display panel PNL according to one embodiment of the present disclosure. The display panel PNL provided in this embodiment includes a through-hole HH, a through-hole encapsulation area HA surrounding the through-hole HH, and a display area AA surrounding the through-hole encapsulation area HA.

[0081] In a display device that uses this display panel PNL, a photosensitive element CA can be disposed on the back of the display panel PNL (see...). Figure 4The photosensitive element CA can be configured in a one-to-one correspondence with the through-hole HH, and the photosensitive element CA can be directly facing the corresponding through-hole HH in order to receive the light transmitted from the through-hole HH. The photosensitive element CA can be one or more light sensors, such as a camera, an optical fingerprint recognition chip, a light intensity sensor, etc. In one example, the photosensitive component can be a camera, such as a CCD (charge-coupled device) camera.

[0082] Figure 4 This is a schematic diagram of the planar structure of the display panel PNL at the through-hole encapsulation area HA in one example; Figure 5 This is a cross-sectional view of the display panel PNL at the through-hole encapsulation area HA, as shown in one example.

[0083] exist Figure 4 and Figure 5 In the example, along the direction from the display area AA towards the via HH, the via package area HA sequentially includes a winding area HA2, a first barrier area HA3, a second barrier area HA4, and a third barrier area HA5. Within the winding area HA2, the display panel PNL is provided with a transition winding CL to ensure that the signal lines around the via HH are not interrupted by the via HH. For example, the transition winding CL may include a first transition winding for ensuring electrical continuity of the scan line GL, and a second transition winding for ensuring electrical continuity of the data line DL. Depending on the needs, one or more transition windings may be provided within the winding area HA2, bypassing the via HH, for example, encircling the via HH half a turn. Depending on the needs, the transition winding CL may be disposed on one or more metal layers of the display layer DPL, for example, the transition winding CL may be disposed on one or more metal layers such as the gate metal layer GT, the source / drain metal layer SD, etc.

[0084] See Figure 4 and Figure 5 To ensure stable performance of the transition winding CL, an auxiliary line region HA1 can be provided on at least one side of the winding region HA2, and auxiliary traces ML are provided in the auxiliary line region HA1. Thus, when the transition winding CL is fabricated using processes such as photolithography, the auxiliary traces ML can ensure that each transition winding CL is in a generally uniform process environment, improving the fabrication yield of the transition winding CL. Figure 4 and Figure 5 In the example, the auxiliary line area HA1 may include an inner auxiliary line area HA11 located inside the winding area HA2 (on the side closer to the via HH) and an outer auxiliary line area HA12 located outside the winding area HA2 (on the side closer to the display area AA). Thus, the auxiliary trace ML may include an inner auxiliary trace MLA located in the inner auxiliary line area HA11 (between the winding area HA2 and the via HH), and an outer auxiliary trace MLB located in the outer auxiliary line area HA12 (between the winding area HA2 and the display area AA).

[0085] In other examples of the present disclosure, the auxiliary line region HA1 can also be provided only on one side of the winding region HA2, for example, only the inner auxiliary line region HA11 or only the outer auxiliary line region HA12; correspondingly, the auxiliary metal line ML can include only the inner auxiliary metal line MLA or only the outer auxiliary metal line MLB.

[0086] In an example, the display panel PNL can be provided with only the inner auxiliary line region HA11 and not provided with the outer auxiliary line region HA12, i.e., the display panel PNL is provided with only the inner auxiliary metal line MLA and not provided with the outer auxiliary metal line MLB. On the one hand, the distance between the winding region HA2 and the display region AA is relatively close, and the density of metal lines in the display region AA is very high, so that even if the display panel PNL is not provided with auxiliary metal lines ML between the winding region HA2 and the display region AA, the yield of the adapter winding CL will not be greatly reduced, and at the same time, the size of the through-hole packaging region HA can be reduced by default of the outer auxiliary line region HA12 to increase the display area of the display panel PNL. On the inner side of the winding region HA2, the density of metal lines is relatively low, so that the inner auxiliary line region HA11 is provided and the inner auxiliary metal line MLA is provided in the inner auxiliary line region HA11 to facilitate improving the yield of the innermost one or several adapter windings CL.

[0087] It can be understood that, according to the need of electrical connection, the auxiliary metal line ML can be disconnected if necessary to ensure the electrical connection between the adapter winding CL and the display region AA, which makes the auxiliary metal line ML have one or more discontinuities instead of being a complete continuous ring. Of course, the auxiliary metal line ML can also be a complete continuous ring.

[0088] In an example, referring to Figure 4 and Figure 5 , one or more first dams RA are provided in the first dam region HA3, and the first dam RA can be provided around the through-hole HH. The lower surface of the thin film packaging layer TFE (the surface close to the substrate SBT, for example, the lower surface of the first inorganic packaging layer CVD1) can cooperate with the first dam RA, thereby prolonging the invasion path of water and oxygen invading from the through-hole HH to the display region AA, and improving the packaging effect of the through-hole packaging region HA.

[0089] Optionally, the display panel PNL can be provided with 2-8 first dams RA in the first dam region HA3, for example, 2, 3, 4, 5, 6, 7 or 8 first dams RA.

[0090] In an example, the first dam RA can be formed by using the gate metal layer GT or the source-drain metal layer SD, for example, by using one layer of source-drain metal layer SD or multiple layers of laminated source-drain metal layer SD to form the first dam RA.

[0091] For example, the first dam RA is formed by using a source-drain metal layer SD, and the source-drain metal layer SD includes a plurality of metal sub-layers (e.g., in a Ti / Al / Ti sandwich structure, or in a Mo / Cu / Mo sandwich structure) arranged in a stack. Due to different etching rates of different metal sub-layers, the side surface of the first dam RA can be concave, e.g., the cross section of the first dam RA can be in an H shape or a T shape. Thus, when forming the thin film encapsulation layer TFE, the first dam RA can not only increase the water-oxygen invasion path, but also block the continuity of the organic encapsulation layer IJP, thereby further improving the encapsulation effect.

[0092] In an embodiment of the present disclosure, referring to Figure 4 and Figure 5 , the display panel PNL is provided with at least one encapsulation dam RD surrounding the through hole HH in the second dam wall area HA4. When preparing the thin film encapsulation layer TFE, the encapsulation dam RD can block the organic encapsulation layer IJP, so as to avoid the organic encapsulation layer IJP overflowing to the inner side of the encapsulation dam RD, thereby ensuring that the organic encapsulation layer IJP is covered by the inorganic encapsulation layer. Thus, in the second dam wall area HA4, the thin film encapsulation layer TFE can no longer be provided with the organic encapsulation layer IJP, but only with the inorganic encapsulation layer, which can cooperate with the encapsulation dam RD to achieve effective encapsulation and block water-oxygen invasion. The encapsulation dam RD is in a convex shape, which makes the water-oxygen invasion path longer, thereby improving the encapsulation effect.

[0093] In an example of the present disclosure, only one encapsulation dam RD is provided in the second dam wall area HA4, which can reduce the size of the through hole encapsulation area HA, thereby improving the display effect and user experience. It can be understood that in other embodiments of the present disclosure, the number of encapsulation dams RD can be multiple, e.g., 2-4 encapsulation dams RD surrounding the through hole HH in sequence can be provided.

[0094] In an embodiment of the present disclosure, referring to Figure 5 and Figure 5 , the display panel PNL is provided with at least one second dam RB surrounding the through hole HH in the third dam wall area HA5, e.g., 2-9 second dams RB surrounding the through hole HH in sequence can be provided. When cutting the display panel PNL to form the through hole HH, the second dam RB can suppress and block the cracks generated at the edge of the through hole HH, thereby avoiding the cracks causing the display panel PNL to be defective.

[0095] In an example, when preparing the thin film encapsulation layer TFE, the first inorganic encapsulation layer CVD1 can cooperate with the second dam RB, thereby further increasing the water-oxygen invasion path.

[0096] In an example, the second dam RB can be prepared by using at least one of the source-drain metal layer SD or the gate metal layer GT.

[0097] In an embodiment of the disclosure, referring to Figure 5 The display device can further be provided with a transparent cover plate CG, which can be disposed on the light-emitting side of the display panel PNL. For example, the transparent cover plate CG is disposed on the side of the pixel layer PXL away from the substrate SBT.

[0098] In an embodiment of the disclosure, referring to Figure 6 The display device can further be provided with a back film BF, which can be disposed on the back light side of the display panel PNL, for example, on the side of the substrate SBT away from the pixel layer PXL. The back film BF can protect and support the display panel PNL. In an example, referring to Figure 6 The back film BF can be provided with a through hole for avoiding the light-sensing element CA.

[0099] Referring to Figure 6 The display device using the display panel PNL can be provided with a light-sensing element CA, for example, a camera, at the through hole HH. If the light emitted by the display area AA irradiates the through hole HH, it will affect the final effect of the light-sensing element CA. Taking a smart phone as an example, the shooting effect of the phone becomes a key issue that the phone manufacturer and the user of the phone pay close attention to; although in most cases, the shooting effect of the phone mainly depends on the configuration and performance of the camera, it is found in applications that the problem of the light emitted by the display area AA irradiating the through hole HH will have a significant and direct impact on the shooting effect. In the present disclosure, the phenomenon that the light emitted by the display area AA irradiates the through hole HH and affects the light-sensing element CA in the through hole HH is called the crosstalk interference of the display area AA to the through hole HH. With the size of the through hole packaging area HA becoming smaller and smaller, the crosstalk interference of the display area AA to the through hole HH becomes more and more prominent. The crosstalk interference of the display area AA to the through hole HH will affect the shooting color difference and cause the consumer experience to become worse.

[0100] Figure 6 A schematic diagram of possible crosstalk light paths in the display device. In the example of Figure 7 Light path A represents that the light emitted by the sub-pixel PX is reflected by the metal layer of the touch function layer TSL and then irradiates the through hole HH. Light path B represents that the light emitted by the sub-pixel PX is reflected by the transparent cover plate CG and then irradiates the through hole HH. Light path C represents that the light emitted by the sub-pixel PX is reflected by the metal structures such as the source-drain metal layer SD and the gate metal layer GT, and then irradiates the through hole HH after being reflected by multiple film layers. Light path D represents that the light emitted by the sub-pixel PX directly irradiates the through hole HH. According to Figures 8-14It can be seen that if the structure in the through-hole packaging area HA is not improved, the light emitted by the sub-pixel PX has multiple paths to irradiate the through-hole HH, thereby causing the display area AA to have a strong level of crosstalk interference to the through-hole HH. Especially as the width of the through-hole packaging area HA decreases, some crosstalk paths will be further enhanced, thereby causing the display area AA to have more prominent crosstalk interference to the through-hole HH.

[0101] Based on this, the display panel PNL of the present disclosure improves at least one structure in the through-hole packaging area HA to weaken or eliminate the crosstalk interference of the display area AA to the through-hole HH, thereby improving the performance of the photosensitive element CA applied with the display panel PNL. Referring to Figure 8 The display panel PNL of the present disclosure has at least one light-blocking structure M0 surrounding the through-hole HH in the through-hole packaging area HA; the light-blocking structure M0 includes a bottom metal structure MA in the display layer DPL and a top metal structure MB in the touch function layer TSL, and the bottom metal structure MA and the top metal structure MB are arranged in overlap. In the present disclosure, the light-blocking structure M0 includes the bottom metal structure MA and the top metal structure MB arranged in overlap, both of which have metal materials and are not transparent to light, and the two can form a light-blocking dam to block at least part of the light from the display area AA. Moreover, since the bottom metal structure MA and the top metal structure MB are arranged in overlap, only the light that can enter between the bottom metal structure MA and the top metal structure MB can be reflected to the through-hole HH by the upper surface of the bottom metal structure MA or the lower surface of the top metal structure MB, so the bottom metal structure MA and the top metal structure MB effectively reduce the light leakage in the direction of the display area AA.

[0102] In one embodiment of the present disclosure, referring to Figure 10 The light-blocking structure M0 includes at least one auxiliary wire ML; the bottom metal structure MA of the auxiliary wire ML includes at least two of a gate metal sub-wire LG in the gate metal layer GT, a source-drain metal sub-wire LSD in the source-drain metal layer SD, and an electrode metal sub-wire LPE in the pixel electrode layer PEL; and the top metal structure MB of the auxiliary wire ML includes at least one of a first touch metal sub-wire LTA in the first touch metal layer TMA and a second touch metal sub-wire LTB in the second touch metal layer TMB.

[0103] In the conventional technology, the auxiliary wire ML only includes sub-wires in the gate metal layer GT or sub-wires in the source-drain metal layer SD. In this embodiment, more metal layers can be used to prepare the auxiliary wire ML, and the auxiliary wire ML can block light from the display area AA without adding new structures. Optionally, the adjacent two sub-wires of the bottom metal structure MA of the auxiliary wire ML are arranged in an overlapping manner. In this way, the bottom metal structure MA can have a smaller gap and a better light blocking effect.

[0104] In the embodiment of the present disclosure, the adjacent two sub-wires of the bottom metal structure MA of the auxiliary wire ML can be connected to each other or can be spaced apart by an insulating layer. For example, the bottom metal structure MA of the auxiliary wire ML can use a continuous metal stacking light blocking strategy or a non-continuous metal stacking light blocking strategy in the wiring layer MRL.

[0105] For example, in the examples of Figure 11 , Figure 13 , Figure 9 and Figure 12 , the bottom metal structure MA of the auxiliary wire ML uses a continuous metal stacking light blocking strategy in the wiring layer MRL. In these examples, the display layer DPL includes a plurality of source-drain metal layers SD arranged in sequence, the bottom metal structure MA of the auxiliary wire ML has a corresponding source-drain metal sub-wire LSD in any one of the source-drain metal layers SD, and the adjacent two source-drain metal sub-wires LSD are at least partially connected to each other on the surface; the electrode metal sub-wire LPE is at least partially connected to the surface of the source-drain metal sub-wire LSD farthest from the substrate SBT; the display layer DPL further includes a pixel definition layer PDL and / or a support column layer on the side of the pixel electrode layer PEL away from the substrate SBT, one or both of the pixel definition layer PDL and the support column layer are provided with a first insulating structure LC corresponding to the auxiliary wire ML, and the first insulating structure LC covers each source-drain metal sub-wire LSD and electrode metal sub-wire LPE of the corresponding auxiliary wire ML.

[0106] In these examples, the adjacent source-drain metal sub-wires LSD and electrode metal sub-wires LPE of the same bottom metal structure MA are stacked in sequence to form a higher metal blocking wall, which can effectively block light. The auxiliary wire ML is provided with a first insulating structure LC, which covers the metal blocking wall formed by each source-drain metal sub-wire LSD and electrode metal sub-wire LPE, thereby effectively stabilizing the structure of the metal blocking wall, for example, reducing the risk of collapse of the metal blocking wall.

[0107] For another example, in the examples of Figure 8 and Figure 11In the examples, the bottom metal structure MA of the auxiliary wire ML adopts a light-blocking strategy of a discontinuous metal stack in the wiring layer MRL. In these examples, the display layer DPL includes a plurality of wiring unit layers MF arranged in sequence, and each wiring unit layer MF includes a source-drain metal layer SD and a planarization layer PLN located on a side of the source-drain metal layer SD away from the substrate SBT. The display panel PNL has at least one auxiliary wire group MLS, and any one auxiliary wire group MLS includes a plurality of auxiliary wires ML arranged in sequence and adjacent to the via HH. In the same auxiliary wire group MLS, the bottom metal structure MA of any one auxiliary wire ML has a corresponding source-drain metal sub-wire LSD in any one source-drain metal layer SD, and has a gap between two adjacent source-drain metal sub-wires LSD in the same source-drain metal layer SD. Any one planarization layer PLN has a second insulating structure LSC corresponding to the auxiliary wire group MLS, and the second insulating structure LSC covers the gap between each source-drain metal sub-wire LSD and each source-drain metal sub-wire LSD in the same wiring unit layer MF.

[0108] In these examples, there is a risk of residual metal particles between the two adjacent source-drain metal sub-wires LSD in the same source-drain metal layer SD. If not handled, the residual metal particles will cause the panel yield to decrease. In this example, after each source-drain metal sub-wire LSD of the source-drain metal layer SD of the wiring unit layer MF is formed, the planarization layer PLN of the wiring unit layer MF needs to be prepared, and the planarization layer PLN of the wiring unit layer MF forms the second insulating structure LSC covering the adjacent source-drain metal sub-wires LSD and the gap between the adjacent source-drain metal sub-wires LSD. In this way, even if there are metal particles in the gap between the source-drain metal sub-wires LSD, the metal particles will be covered and fixed by the second insulating structure LSC and will not be transferred to other areas (such as the display area AA) in the subsequent preparation process. This can effectively improve the yield of the preparation of the display panel PNL.

[0109] In these examples, the adjacent source-drain metal sub-wires LSD of the same auxiliary wire ML can be spaced apart by the planarization layer PLN. However, considering the sequential interception of light by the auxiliary wires ML in the auxiliary wire group MLS and the width of the source-drain metal sub-wire LSD itself, the auxiliary wire ML can still play a good light-blocking effect.

[0110] In the embodiments of the present disclosure, the electrode metal sub-wires LPE of the adjacent two auxiliary wires ML of the auxiliary wire group MLS can be connected to each other as a whole, or can be independent.

[0111] For example, in the examples, the electrode metal sub-wire LPE of the auxiliary wire ML is connected to the electrode metal sub-wire LPE of the adjacent auxiliary wire ML. Figure 9 and Figure 12In the example, within the same auxiliary trace group MLS, the electrode metal sub-trace LPE of any one auxiliary trace ML does not overlap with the electrode metal sub-trace LPEs of the other auxiliary traces ML, and there is a gap between adjacent electrode metal sub-trace LPEs. Furthermore, within the same auxiliary trace group MLS, the first insulating structure LC of any one auxiliary trace ML is not connected to the first insulating structure LC of the other auxiliary traces ML, and there is a gap between adjacent first insulating structures LC. Thus, the electrode metal sub-trace LPE and the first insulating structure LC form an independent unit. This allows the first inorganic encapsulation layer CVD1 of the thin-film encapsulation layer TFE to have a more tortuous surface, thereby extending the water and oxygen intrusion path.

[0112] For another example, in Figure 8 and Figure 11 In the example, within the same auxiliary trace group MLS, the electrode metal sub-traces LPE of each auxiliary trace ML are interconnected to form a whole. In other words, the structure of the auxiliary trace group MLS located in the pixel electrode layer PEL covers the gaps between the auxiliary traces ML. Furthermore, the first insulating structure LC of each auxiliary trace ML in the same auxiliary trace group MLS is interconnected to form a whole.

[0113] In this embodiment of the disclosure, the top metal structures MB of two adjacent auxiliary traces ML of the auxiliary trace group MLS can be connected to each other as a whole, or they can be independent of each other.

[0114] For example, in Figure 9 and Figure 12 In the example, within the same auxiliary trace group MLS, the top metal structure MB of any one of the auxiliary traces ML is not connected to the top metal structures MB of the other auxiliary traces ML, and there is a gap between two adjacent top metal structures MB.

[0115] For another example, in Figures 8-14 and Figures 8-14 In the example, within the same auxiliary trace group MLS, the top metal structures MB of each auxiliary trace ML are interconnected to form a whole. In other words, the metal structure of the auxiliary trace group MLS covers the gaps between the auxiliary traces ML in the touch function layer TSL.

[0116] In this embodiment of the disclosure, the auxiliary trace ML in the touch function layer TSL may include only the first touch metal sub-trace LTA, or only the second touch metal sub-trace LTB, or a stack of the first touch metal sub-trace LTA and the second touch metal sub-trace LTB.

[0117] For example, in Figure 14In the example, the top metal structure MB of the auxiliary wire ML includes a first touch metal sub-wire LTA and a second touch metal sub-wire LTB which are stacked. Figure 8 In the example, the second touch metal sub-wire LTB has a top projection on the substrate SBT which is located within a top projection of the first touch metal sub-wire LTA on the substrate SBT. It can be understood that in other examples of the present disclosure, the second touch metal sub-wire LTB can also cover the first touch metal sub-wire LTA, for example, the top projection of the first touch metal sub-wire LTA on the substrate SBT is located within the top projection of the second touch metal sub-wire LTB on the substrate SBT.

[0118] In an embodiment of the present disclosure, the auxiliary wire ML at the portion of the touch function layer TSL can only include a metal structure, for example, only include the first touch metal sub-wire LTA or the second touch metal sub-wire LTB, or include both the first touch metal sub-wire LTA and the second touch metal sub-wire LTB which are stacked. Figure 8 In another embodiment of the present disclosure, referring to FIG. 3, the auxiliary wire ML at the portion of the touch function layer TSL can further include a third insulating structure LTC of the touch insulating layer TLD, the third insulating structure LTC is sandwiched between the first touch metal sub-wire LTA and the second touch metal sub-wire LTB, or the third insulating structure LTC covers the second touch metal sub-wire LTB. In an example, the auxiliary wire ML at the portion of the touch function layer TSL includes the first touch metal sub-wire LTA, the third insulating structure LTC and the second touch metal sub-wire LTB which are stacked in sequence. The third insulating structure LTC is arranged on a surface of the first touch metal sub-wire LTA away from the substrate SBT, and the third insulating structure LTC has a top projection on the substrate SBT which is located within a top projection of the first touch metal sub-wire LTA on the substrate SBT; the second touch metal sub-wire LTB covers the third insulating structure LTC, i.e., the second touch metal sub-wire LTB has a top projection on the substrate SBT which covers a top projection of the third insulating structure LTC on the substrate SBT. Further, the second touch metal sub-wire LTB covers the third insulating structure LTC and the first touch metal sub-wire LTA. In this way, the third insulating structure LTC can raise the top surface of the second touch metal sub-wire LTB, thereby increasing the total height of the top metal structure MB and improving the light blocking effect of the auxiliary wire ML.

[0119] In this embodiment of the disclosure, the display panel PNL can have auxiliary traces ML provided in one or both of the inner auxiliary line area HA11 and the outer auxiliary line area HA12. For example, the display panel PNL can have an inner auxiliary trace MLA provided in the inner auxiliary line area HA11, or an outer auxiliary trace MLB provided in the outer auxiliary line area HA12, or an inner auxiliary trace MLA provided in the inner auxiliary line area HA11 and an outer auxiliary trace MLB provided in the outer auxiliary line area HA12. Since the outer auxiliary trace MLB is closer to the sub-pixel PX, the outer auxiliary trace MLB has a better light-blocking effect.

[0120] The auxiliary routing ML in the embodiments of this disclosure is illustrated below with reference to several examples.

[0121] Figure 8 This is a schematic diagram of the structure of the display panel PNL in the first example of this disclosure. Figure 8 In the example, the display panel PNL has two inner auxiliary traces MLA in the inner auxiliary line area HA11, and the two inner auxiliary traces MLA are arranged around the via HH in sequence. The bottom metal structure MA of the inner auxiliary trace MLA includes a first gate metal sub-trace LG1 located in the first gate metal layer GT1, a second gate metal sub-trace LG2 located in the second gate metal layer GT2, a first source drain metal sub-trace LSD1 located in the first source drain metal layer SD1, a second source drain metal sub-trace LSD2 located in the second source drain metal layer SD2, and an electrode metal sub-trace LPE located in the pixel electrode layer PEL. The first source drain metal sub-trace LSD1, the second source drain metal sub-trace LSD2, and the electrode metal sub-trace LPE are stacked and connected in sequence, and a first insulating structure LC covers the stacked structure formed by the first source drain metal sub-trace LSD1, the second source drain metal sub-trace LSD2, and the electrode metal sub-trace LPE. The top metal structure MB of the internal auxiliary trace MLA includes a first touch metal sub-trace LTA located in the first touch metal layer TMA and a second touch metal sub-trace LTB located in the second touch metal layer TMB. The first touch metal sub-trace LTA and the second touch metal sub-trace LTB are stacked and connected sequentially. Figure 9 In the example, the two inner auxiliary traces (MLAs) are independent, and their same-layer metal structures are not interconnected. See also Figure 9 Due to the obstruction of the metal structure in the inner auxiliary trace MLA, only the light between light rays E1 and E2 can pass through the inner auxiliary trace MLA. Therefore, the inner auxiliary trace MLA can effectively reduce the crosstalk interference of the display area AA to the via HH.

[0122] Figure 9 This is a schematic diagram of the structure of the display panel PNL in the second example of this disclosure. Figure 9In the example of FIG. 1, the display panel PNL is provided with two inner auxiliary metal lines MLA in the inner auxiliary line area HA11, and the two inner auxiliary metal lines MLA are sequentially arranged around the through hole HH. The two inner auxiliary metal lines MLA form an auxiliary metal line group MLS. For any one inner auxiliary metal line MLA, the bottom metal structure MA of the inner auxiliary metal line MLA includes a first gate metal sub-line LG1 in the first gate metal layer GT1, a second gate metal sub-line LG2 in the second gate metal layer GT2, a first source-drain metal sub-line LSD1 in the first source-drain metal layer SD1, a second source-drain metal sub-line LSD2 in the second source-drain metal layer SD2, and an electrode metal sub-line LPE in the pixel electrode layer PEL. In the first wiring unit layer MF1, the first source-drain metal layer SD1 is provided with two first source-drain metal sub-lines LSD1, and the first planarization layer PLN1 is provided with a second insulating structure LSC1 covering the two first source-drain metal sub-lines LSD1 and the gap between the two first source-drain metal sub-lines LSD1, so that the metal particles between the two first source-drain metal sub-lines LSD1 can be fully covered by the second insulating structure LSC1. In the second wiring unit layer MF2, the second source-drain metal layer SD2 is provided with two second source-drain metal sub-lines LSD2, and the second planarization layer PLN2 is provided with a second insulating structure LSC2 covering the two second source-drain metal sub-lines LSD2 and the gap between the two second source-drain metal sub-lines LSD2, so that the metal particles between the two second source-drain metal sub-lines LSD2 can be fully covered by the second insulating structure LSC2. Thus, the first source-drain metal sub-line LSD1 and the second source-drain metal sub-line LSD2 are sandwiched by the second insulating structure LSC1, and the electrode metal sub-line LPE and the second source-drain metal sub-line LSD2 are sandwiched by the second insulating structure LSC2. In the example of FIG. 1, the electrode metal sub-line LPE is arranged to overlap with the two second source-drain metal sub-lines LSD2 at the same time, i.e., the electrode metal sub-lines LPE of the two inner auxiliary metal lines MLA are interconnected as a whole. The first insulating structure LC covers the electrode metal sub-line LPE. The top metal structure MB of the inner auxiliary metal line MLA includes a first touch metal sub-line LTA in the first touch metal layer TMA and a second touch metal sub-line LTB in the second touch metal layer TMB, and the first touch metal sub-line LTA and the second touch metal sub-line LTB are sequentially stacked and connected. In the example of FIG. 1, the first touch metal sub-line LTA and the second touch metal sub-line LTB are arranged to overlap with the through hole HH at the same time, i.e., the first touch metal sub-line LTA and the second touch metal sub-line LTB of the two inner auxiliary metal lines MLA are interconnected as a whole. Figure 10 In the example of FIG. 1, the electrode metal sub-line LPE is arranged to overlap with the two second source-drain metal sub-lines LSD2 at the same time, i.e., the electrode metal sub-lines LPE of the two inner auxiliary metal lines MLA are interconnected as a whole. The first insulating structure LC covers the electrode metal sub-line LPE. The top metal structure MB of the inner auxiliary metal line MLA includes a first touch metal sub-line LTA in the first touch metal layer TMA and a second touch metal sub-line LTB in the second touch metal layer TMB, and the first touch metal sub-line LTA and the second touch metal sub-line LTB are sequentially stacked and connected. In the example of FIG. 1, the first touch metal sub-line LTA and the second touch metal sub-line LTB are arranged to overlap with the through hole HH at the same time, i.e., the first touch metal sub-line LTA and the second touch metal sub-line LTB of the two inner auxiliary metal lines MLA are interconnected as a whole. Figure 10In the example, the first touch metal sub-wires LTA of the two inner auxiliary wires MLA are connected to each other as a whole, and the second touch metal sub-wires LTB of the two inner auxiliary wires MLA are connected to each other as a whole. In the example, although the existence of the second insulating structures LSC1 and LSC2 causes the light transmission gaps between the first source-drain metal sub-wires LSD1, the second source-drain metal sub-wires LSD2 and the electrode metal sub-wires LPE, the arrangement of the two rings of the inner auxiliary wires MLA further shields the light rays that are transmitted, which can effectively reduce the light transmission in the gaps.

[0123] Figure 10 FIG. 6 is a structural schematic diagram of a display panel PNL in a third example of the present disclosure. In the example, the display panel PNL is provided with an outer auxiliary wire MLA in the outer auxiliary wire area HA12. Figure 11 In the example, the display panel PNL is provided with an outer auxiliary wire MLA in the outer auxiliary wire area HA12. The bottom metal structure MA of the outer auxiliary wire MLA includes the first gate metal sub-wire LG1 in the first gate metal layer GT1, the second gate metal sub-wire LG2 in the second gate metal layer GT2, the first source-drain metal sub-wire LSD1 in the first source-drain metal layer SD1, the second source-drain metal sub-wire LSD2 in the second source-drain metal layer SD2 and the electrode metal sub-wire LPE in the pixel electrode layer PEL. The first source-drain metal sub-wire LSD1, the second source-drain metal sub-wire LSD2 and the electrode metal sub-wire LPE are sequentially stacked and connected, and the first insulating structure LC covers the stacked structure formed by the first source-drain metal sub-wire LSD1, the second source-drain metal sub-wire LSD2 and the electrode metal sub-wire LPE. The top metal structure MB of the outer auxiliary wire MLA includes the first touch metal sub-wire LTA in the first touch metal layer TMA and the second touch metal sub-wire LTB in the second touch metal layer TMB, and the first touch metal sub-wire LTA and the second touch metal sub-wire LTB are sequentially stacked and connected. In the example, the outer auxiliary wire MLA is closer to the sub-pixel PX, which makes the outer auxiliary wire MLA achieve a better light shielding effect. Figure 11 In the example, the outer auxiliary wire MLA is closer to the sub-pixel PX, which makes the outer auxiliary wire MLA achieve a better light shielding effect.

[0124] Figure 10 FIG. 7 is a structural schematic diagram of a display panel PNL in a fourth example of the present disclosure. In the example, the display panel PNL is provided with an outer auxiliary wire MLA in the outer auxiliary wire area HA12. Figure 12 In the example, the display panel PNL is provided with two outer auxiliary wires MLA that sequentially surround the through hole HH in the outer auxiliary wire area HA12. The structure of each outer auxiliary wire MLA is basically similar to the structure of the outer auxiliary wire MLA shown in the example of FIG. 6. Figure 12 In the example, the display panel PNL is provided with two outer auxiliary wires MLA that sequentially surround the through hole HH in the outer auxiliary wire area HA12. The structure of each outer auxiliary wire MLA is basically similar to the structure of the outer auxiliary wire MLA shown in the example of FIG. 6.

[0125] Figure 9 FIG. 8 is a structural schematic diagram of a display panel PNL in a fifth example of the present disclosure. In the example, the display panel PNL is provided with an outer auxiliary wire MLA in the outer auxiliary wire area HA12. Figure 13In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figure 13 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL.

[0126] Figure 8 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figure 10 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figure 14 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figure 14 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL.

[0127] Figure 8 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figure 14 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figures 8-14 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figures 8-14 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL.

[0128] It can be understood that in the example of the display panel PNL, the auxiliary metal line ML is provided with the first source / drain metal sub-line LSD1 and the second source / drain metal sub-line LSD2. Figure 15 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL.

[0129] In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL. Figure 15 In the example of the display panel PNL, two outer auxiliary metal lines MLB are arranged in the outer auxiliary line area HA12, and the two outer auxiliary metal lines MLB are sequentially arranged around the through hole HH to form an auxiliary metal line group MLS. The structure of the auxiliary metal line group MLS in the outer auxiliary line area HA12 is basically similar to the auxiliary metal line group MLS in the inner auxiliary line area HA11 as shown in the example of the display panel PNL.

[0130] In some embodiments of this disclosure, the encapsulated barrier RD can also be used as the light-blocking structure M0. See also Figure 15 The bottom metal structure MA of the encapsulation dam RD includes at least two of the following: a gate metal sub-dam located on the gate metal layer GT, a source / drain metal sub-dam DSD located on the source / drain metal layer SD, and an electrode metal sub-dam DPE located on the pixel electrode layer PEL; the top metal structure MB of the encapsulation dam RD includes at least one of the first touch metal sub-dam DTA located on the first touch metal layer TMA and the second touch metal sub-dam DTB located on the second touch metal layer TMB. In related technologies, the encapsulation dam RD is basically formed of organic materials, and its main function is to prevent the organic encapsulation layer IJP from overflowing. However, in this embodiment, by setting a metal structure in the encapsulation dam RD, the encapsulation dam RD can have a light-blocking effect.

[0131] In one embodiment of this disclosure, the display layer DPL includes multiple source / drain metal layers SD stacked sequentially. The bottom metal structure MA of the encapsulation dam RD has a corresponding source / drain metal sub-dam DSD in any one of the source / drain metal layers SD, and at least a portion of the surfaces of two adjacent source / drain metal sub-dam DSDs are connected to each other. Thus, a higher light-blocking height can be achieved by stacking the source / drain metal sub-dam DSDs.

[0132] In one embodiment of this disclosure, the bottom metal structure MA of the encapsulation dam RD further includes an electrode metal sub-dam, the electrode metal sub-dam DPE, which is at least partially interconnected with the surface of the source / drain metal sub-dam DSD furthest from the substrate SBT. Thus, the electrode metal sub-dam DPE can further increase the metal stacking height of the bottom metal structure MA, further improving the light-blocking effect.

[0133] For example, in Figure 15 In the example, the encapsulation dam RD includes a first source / drain metal sub-dam DSD1 located on the first source / drain metal layer SD1, a second source / drain metal sub-dam DSD2 located on the second source / drain metal layer SD2, and an electrode metal sub-dam DPE located on the pixel electrode layer PEL. The first source / drain metal sub-dam DSD1, the second source / drain metal sub-dam DSD2, and the electrode metal sub-dam DPE are stacked sequentially and connected to form a continuous metal stack structure. In this example, the display panel PNL has two source / drain metal layers SD, therefore two source / drain metal sub-dam DSDs are provided. It is understood that when the display panel PNL has more source / drain metal layers SD, the encapsulation dam RD can also have more source / drain metal sub-dam DSDs.

[0134] In an embodiment of the present disclosure, the display layer DPL further comprises a pixel definition layer PDL and / or a support column layer on the side of the pixel electrode layer PEL away from the substrate base plate SBT, one or both of the pixel definition layer PDL and the support column layer are provided with a fourth insulating structure DC corresponding to the encapsulation dam RD, the fourth insulating structure DC covers the bottom metal structure MA of the corresponding encapsulation dam RD. For example, in the example of Figure 15 the fourth insulating structure DC covers the metal stack formed by the first source-drain metal sub-dam DSD1, the second source-drain metal sub-dam DSD2 and the electrode metal sub-dam DPE. It can be understood that in some other embodiments of the present disclosure, the fourth insulating structure DC can also be formed by the support column layer, or be formed by the pixel definition layer and the support column layer together.

[0135] In the example of Figure 16 , the first source-drain metal sub-dam DSD1, the second source-drain metal sub-dam DSD2 and the electrode metal sub-dam DPE are sequentially stacked and connected. It can be understood that in some other embodiments of the present disclosure, a lifting unit formed by an insulating layer can also be arranged between adjacent metal layers in the first source-drain metal sub-dam DSD1, the second source-drain metal sub-dam DSD2 and the electrode metal sub-dam DPE; further, an upper metal layer can cover a lower lifting unit, so that the lower lifting unit can substantially raise the light-blocking height of the upper metal layer. For example, a first lifting unit located in the first planarization layer PLN1 can be arranged between the first source-drain metal sub-dam DSD1 and the second source-drain metal sub-dam DSD2, and the second source-drain metal sub-dam DSD2 covers the first lifting unit, which enables the second source-drain metal sub-dam DSD2 to form effective light-blocking on the side of the first lifting unit. For another example, a second lifting unit located in the second planarization layer PLN2 can be arranged between the second source-drain metal sub-dam DSD2 and the electrode metal sub-dam DPE, and the electrode metal sub-dam DPE covers the second lifting unit, which enables the electrode metal sub-dam DPE to form effective light-blocking on the side of the second lifting unit.

[0136] In the example of Figure 16In the example of FIG. 6, the top metal structure MB of the encapsulation dam RD includes a first touch metal sub-dam DTA located at the first touch metal layer TMA and a second touch metal sub-dam DTB located at the second touch metal layer TMB, where the first touch metal sub-dam DTA and the second touch metal sub-dam DTB are stacked and connected without a touch insulating layer TLD therebetween. It can be understood that in some other embodiments of the present disclosure, the encapsulation dam RD can further include a third elevated unit located at the touch insulating layer TLD, which can be located between the first touch metal sub-dam DTA and the second touch metal sub-dam DTB. Further, the second touch metal sub-dam DTB covers the third elevated unit. It can be further understood that in some other embodiments of the present disclosure, the top metal structure MB of the encapsulation dam RD can include only the first touch metal sub-dam DTA or only the second touch metal sub-dam DTB; or alternatively, the encapsulation dam RD can not include the first touch metal sub-dam DTA, but include the third elevated unit and the second touch metal sub-dam DTB covering the third elevated unit.

[0137] In some embodiments of the present disclosure, referring to FIG. 6, the display panel PNL has a transition area HA6 surrounding the through hole HH in the through hole packaging area HA; near the edge of the display area AA in the transition area HA6, the step difference between the surface of the thin film packaging layer TFE and the substrate substrate SBT is a first step difference H1; near the edge of the through hole HH in the transition area HA6, the step difference between the surface of the thin film packaging layer TFE and the substrate substrate SBT is a second step difference H2; the first step difference H1 is greater than the second step difference H2; and the metal layer of the touch function layer TSL covers the transition area HA6. Figure 16 In some embodiments of the present disclosure, referring to FIG. 6, the display panel PNL has a transition area HA6 surrounding the through hole HH in the through hole packaging area HA; near the edge of the display area AA in the transition area HA6, the step difference between the surface of the thin film packaging layer TFE and the substrate substrate SBT is a first step difference H1; near the edge of the through hole HH in the transition area HA6, the step difference between the surface of the thin film packaging layer TFE and the substrate substrate SBT is a second step difference H2; the first step difference H1 is greater than the second step difference H2; and the metal layer of the touch function layer TSL covers the transition area HA6.

[0138] Figure 16 ​Due to the obstruction of the encapsulation dam RD, the organic encapsulation layer IJP will not cross the area where the encapsulation dam RD is located. However, the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 will cross the area where the encapsulation dam RD is located and continue to extend towards the via HH to ensure that the organic encapsulation layer IJP is sealed with an inorganic layer. Therefore, along the direction from the display area AA to the via HH, the thin film encapsulation layer TFE exhibits the characteristic of the organic encapsulation layer IJP gradually disappearing and the thickness of the thin film encapsulation layer TFE decreasing within the transition region HA6. The portion of the thin film encapsulation layer TFE covering the encapsulation dam RD no longer has the organic encapsulation layer IJP, and after crossing the organic encapsulation layer IJP, it will gradually descend as the encapsulation dam RD approaches the downward slope of the via HH. Thus, at the end of the transition region HA6 near the via HH, the height of the upper surface of the thin film encapsulation layer TFE (e.g., the surface of the second inorganic encapsulation layer CVD2 away from the substrate SBT) is relatively low. In related technologies, the metal layer of the touch functional layer TSL does not cover the transition region HA6; however, in this embodiment, the metal layer of the touch functional layer TSL can cover the transition region HA6. By utilizing the step difference of the upper surface of the thin film encapsulation layer TFE on the inner side (the side near the via HH) and the outer side (the side near the display area AA) of the transition region HA6, a continuous metal structure with a large step difference is formed. This allows the metal structure of the touch functional layer TSL to have a large step difference within the transition region HA6, thereby playing the role of a metal light-blocking wall.

[0139] It is understandable that within the transition region HA6, the upper surface of the thin-film encapsulation layer TFE may not decrease sequentially from the outside to the inside (from the display area AA towards the via HH); the upper surface of the thin-film encapsulation layer TFE may have fluctuations within the transition region HA6. For example, in Figure 16 In the example, the transition region HA6 spans the encapsulation dam RD; the thin-film encapsulation layer TFE has an organic encapsulation layer IJP on the outer portion of the transition region HA6; the thin-film encapsulation layer TFE spans the encapsulation dam RD within the transition region HA6 and extends to the side of the encapsulation dam RD near the via HH. Thus, on the outer portion of the transition region HA6, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT is a first step difference H1; on the inner portion of the transition region HA6, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT is a second step difference H2; above the encapsulation dam RD, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate SBT is a third step difference H3. Figure 16In the example of FIG. 6, the first step difference H1, the third step difference H3, and the second step difference H2 decrease in turn. However, between the outer portion of the transition region HA6 and above the encapsulation dam RD, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate base plate SBT can be no greater than the third step difference H3. Of course, in other embodiments of the present disclosure, between the outer portion of the transition region HA6 and above the encapsulation dam RD, the step difference between the upper surface of the thin-film encapsulation layer TFE and the substrate base plate SBT can also be no less than the third step difference H3.

[0140] In Figure 17 In the example of FIG. 6, the first touch metal layer TMA and the second touch metal layer TMB both cover the transition region HA6. It can be understood that in some other embodiments of the present disclosure, only the first touch metal layer TMA can cover the transition region HA6, or only the second touch metal layer TMB can cover the transition region HA6.

[0141] In an embodiment of the present disclosure, referring to Figures 8-14 , the first touch metal layer TMA and the second touch metal layer TMB can also cover at least part of the region between the transition region HA6 and the display region AA, for example, cover the wire-winding region HA2 or the first dam region HA3, or cover the third dam region HA5.

[0142] In an embodiment of the present disclosure, referring to Figure 15 , the display panel PNL further includes a color filter layer CFL located on the side of the touch function layer TSL away from the substrate base plate SBT, and the color filter layer CFL has a black matrix layer BM; the black matrix layer BM covers at least part of the through-hole encapsulation region HA. In this way, when the light emitted by the sub-pixel PX directly irradiates the black matrix layer BM, or the light emitted by the sub-pixel PX is reflected by the metal, film layer, cover plate, etc. and then irradiates the black matrix layer BM, the light can be absorbed by the black matrix layer BM instead of continuing to reflect, which can effectively terminate the continuous reflection of the light and effectively reduce the number of lights entering the through-hole HH.

[0143] It can be understood that Figure 16 The example of FIG. 6 only exemplifies a scheme of improving the display panel PNL to reduce the crosstalk by the auxiliary wire ML; Figure 17 The example of FIG. 6 only exemplifies a scheme of improving the encapsulation dam RD to reduce the crosstalk; ​ The example of FIG. 6 only exemplifies a scheme of improving the coverage range of the touch function layer TSL to reduce the crosstalk; ​ The example of FIG. 6 only exemplifies a scheme of improving the coverage range of the black matrix layer BM to reduce the crosstalk. In other embodiments of the present disclosure, multiple of the above-mentioned improvement schemes can also be used at the same time.

[0144] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising a through hole, a through hole packaging area surrounding the through hole, and a display area surrounding the through hole packaging area; the display panel comprises a substrate, a display layer, a thin film packaging layer, and a touch function layer which are sequentially stacked; the display panel has at least one light blocking structure surrounding the through hole in the through hole packaging area; the light blocking structure comprises a bottom metal structure in the display layer and a top metal structure in the touch function layer, and the bottom metal structure and the top metal structure are arranged in overlap.

2. The display panel of claim 1, wherein, the display layer comprises at least one gate metal layer, at least one source-drain metal layer, and a pixel electrode layer which are sequentially stacked on one side of the substrate; the touch function layer comprises a first touch metal layer and a second touch metal layer which are sequentially stacked on one side of the display layer; the light blocking structure comprises at least one auxiliary wire; the bottom metal structure of the auxiliary wire comprises at least two of a gate metal sub-wire in the gate metal layer, a source-drain metal sub-wire in the source-drain metal layer, and an electrode metal sub-wire in the pixel electrode layer; the top metal structure of the auxiliary wire comprises at least one of a first touch metal sub-wire in the first touch metal layer and a second touch metal sub-wire in the second touch metal layer.

3. The display panel of claim 2, wherein, the display layer comprises a plurality of source-drain metal layers which are sequentially stacked; the auxiliary wire has a corresponding source-drain metal sub-wire in any one of the source-drain metal layers, and adjacent two source-drain metal sub-wires are at least partially connected to each other; the electrode metal sub-wire is at least partially connected to the surface of the source-drain metal sub-wire farthest from the substrate; the display layer further comprises a pixel definition layer or a support column layer on the side of the pixel electrode layer away from the substrate, and the pixel definition layer or the support column layer is provided with a first insulating structure corresponding to the auxiliary wire, the first insulating structure covering each source-drain metal sub-wire and electrode metal sub-wire of the corresponding auxiliary wire.

4. The display panel of claim 2, wherein, the display layer comprises a plurality of wiring unit layers which are sequentially stacked, and each wiring unit layer comprises a source-drain metal layer and a planarization layer on the side of the source-drain metal layer away from the substrate; the display panel has at least one auxiliary wire group, and any one of the auxiliary wire groups comprises a plurality of auxiliary wires which are adjacent and sequentially surround the through hole; in the same auxiliary wire group, any one of the auxiliary wires has a corresponding source-drain metal sub-wire in any one of the source-drain metal layers, and has a gap between adjacent two source-drain metal sub-wires in the same source-drain metal layer; any one of the planarization layers has a second insulating structure corresponding to the auxiliary wire group, and the second insulating structure covers the gap between each source-drain metal sub-wire and each source-drain metal sub-wire in the same wiring unit layer.

5. The display panel of claim 4, wherein, in the same auxiliary wire group, the electrode metal sub-wire of any one of the auxiliary wires does not overlap with the electrode metal sub-wire of the remaining auxiliary wires; or, in the same auxiliary wire group, the electrode metal sub-wires of each of the auxiliary wires are connected to form a whole.

6. The display panel of claim 2, wherein, The display panel has at least one auxiliary wiring group, and any one of the auxiliary wiring groups includes a plurality of auxiliary wirings which are adjacent and sequentially surround the through hole; In the same auxiliary wiring group, the top metal structure of any one of the auxiliary wirings is not connected with the top metal structure of the rest of the auxiliary wirings; or, in the same auxiliary wiring group, the top metal structures of each of the auxiliary wirings are connected to form a whole.

7. The display panel of claim 2, wherein, The display panel has a winding area in the through hole packaging area; the auxiliary wirings include inner auxiliary wirings between the winding area and the through hole, and / or include outer auxiliary wirings between the winding area and the display area.

8. The display panel according to any one of claims 1 to 7, wherein The display layer includes at least one gate metal layer, at least one source-drain metal layer and a pixel electrode layer which are sequentially arranged on one side of the substrate; the touch function layer includes a first touch metal layer and a second touch metal layer which are sequentially arranged on one side of the display layer; The light blocking structure includes at least one packaging dam; The bottom metal structure of the packaging dam includes at least two of a gate metal sub-dam, a source-drain metal sub-dam and an electrode metal sub-dam which are located in the gate metal layer, the source-drain metal layer and the pixel electrode layer respectively; The top metal structure of the packaging dam includes at least one of a first touch metal sub-dam and a second touch metal sub-dam which are located in the first touch metal layer and the second touch metal layer respectively.

9. The display panel of claim 8, wherein, The display layer includes a plurality of source-drain metal layers which are sequentially arranged, and the bottom metal structure of the packaging dam has a corresponding source-drain metal sub-dam in any one of the source-drain metal layers, and adjacent two source-drain metal sub-dams are at least partially connected to each other.

10. The display panel of claim 9, wherein, The bottom metal structure of the packaging dam further includes an electrode metal sub-dam which is at least partially connected to the surface of the source-drain metal sub-dam farthest from the substrate.

11. The display panel of claim 9, wherein, The display layer further includes a pixel definition layer or a support column layer which are located on the side of the pixel electrode layer farthest from the substrate, and the pixel definition layer or the support column layer is provided with a fourth insulating structure corresponding to the packaging dam, and the fourth insulating structure covers the bottom metal structure of the corresponding packaging dam.

12. The display panel according to any one of claims 1 to 7, wherein The display panel has a transition area surrounding the through hole in the through hole packaging area; near the edge of the display area in the transition area, the step difference between the surface of the thin film packaging layer farthest from the substrate and the substrate is a first step difference; Near the edge of the through hole in the transition area, the step difference between the surface of the thin film packaging layer farthest from the substrate and the substrate is a second step difference; The first step difference is greater than the second step difference; The metal layer of the touch function layer covers the transition area.

13. The display panel according to any one of claims 1 to 7, wherein The display panel further includes a color film layer on the side of the touch function layer farthest from the substrate, and the color film layer has a black matrix layer; The black matrix layer covers at least part of the through hole packaging area.

14. A display device comprising the display panel of any one of claims 1-13.

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